JP2023083887A - comparator - Google Patents

Abstract

To provide a comparator which has improved response characteristics without increasing a circuit current.SOLUTION: If a current flowing in a load resistor R2 is higher than a current flowing in a load resistor R1, then a shunt circuit 4 shunts a current flowing in a transistor M41 and flows a shunted portion of the current to the load resistor R1. Meanwhile, if the current flowing in the load resistor R1 is higher than the current flowing in the load resistor R2, then the shunt circuit shunts a current flowing in a transistor M42 and flows a shunted portion of the current to the load resistor R2.SELECTED DRAWING: Figure 1

Description

The present invention relates to comparators.

Global warming is thought to be caused by the increased concentration of greenhouse gases such as _CO2 , which intensified the greenhouse effect of the atmosphere. Power consumption is also becoming a big issue. A large number of semiconductor integrated circuits are used in electronic equipment, and response speed and current consumption are the main performance characteristics of comparators, which are widely used in semiconductor integrated circuits. Since the response speed and current consumption of a comparator are in inverse proportion to each other, it is intended to improve the response characteristics to an input signal without increasing the current consumption, thereby contributing to the suppression of global warming.

A circuit as shown in FIG. 6 is known as a comparator used in a semiconductor integrated circuit (see, for example, Patent Document 1). A comparator 100 shown in FIG. 6 includes a differential input section 102, a folded cascode section 103, and an output circuit 105 as main components.

The differential input unit 102 includes differential transistors M1 and M2 whose sources are commonly connected, load resistors R1 and R2 respectively connected to their drains, a common source of the transistors M1 and M2, and a positive power supply voltage VDD. and a constant current source 21 connected between them.

The folded cascode unit 103 includes transistors M3 and M4 whose sources are connected to the load resistors R1 and R2, constant current sources 311 and 312 respectively connected between their drains and the positive power supply voltage VDD, and a gate. and a transistor M5 whose drain is connected to the drain of transistor M4 and whose source is connected to the gate of transistor M4. In the folded cascode section 103, the transistor M3 and the transistor M4 are current-mirror-connected, and an output is taken out from the connection node between the drain of the transistor M4 and the constant current source 312. FIG.

Further, the transistor M5 suppresses an increase in the gate potential of the transistor M6, shortens the propagation delay time, and improves the power supply voltage dependency of the propagation delay time (see, for example, Non-Patent Document 1).

The output circuit 105 includes a transistor M6 having a gate connected to the output of the folded cascode section 103 and a source connected to the negative power supply voltage VSS, and a constant current source 51 connected between the drain and the positive power supply voltage VDD. , and is configured to take out the output signal VOUT from the connection node between the transistor M6 and the constant current source 51. FIG.

Japanese Patent No. 4677284

Haruhiko Yoshida, Practical Design of CMOS Analog IC Circuits, CQ Publisher, 2010 (p144, Figure 4.10)

A conventional comparator having the above configuration has a problem that the circuit current must be increased in order to improve the response characteristics.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a comparator with improved response characteristics without increasing the circuit current.

In order to achieve the above object, a comparator according to the present invention is characterized by the following [1] to [9].
[1]
a first differential transistor and a second differential transistor through which currents having a current ratio corresponding to the first input potential and the second input potential flow respectively;
a first load resistor connected in series with the first differential transistor;
a differential input having a second load resistor connected in series with the second differential transistor;
a third transistor folded cascode-connected to the first differential transistor; a fourth transistor folded cascode-connected to the second differential transistor; a first folded cascode section constituting one output stage;
a fifth transistor folded cascode-connected to the second differential transistor; and a sixth transistor folded cascode-connected to the first differential transistor, wherein the sixth transistor is the first differential transistor. a second folded cascode unit constituting two output stages;
and an output circuit connected to the outputs of the first and second output stages to output an output signal,
When the current flowing through the second load resistor is larger than the current flowing through the first load resistor, the current flowing through the fourth transistor is divided to flow through the first load resistor, When the current flowing through the first load resistor is larger than the current flowing through the second load resistor, a shunt circuit that divides the current flowing through the sixth transistor and flows it through the second load resistor,
Be a comparator.
[2]
The comparator according to [1],
The shunt circuit is
a seventh transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the drain or collector of the third transistor;
Be a comparator.
[3]
The comparator according to [2],
The shunt circuit is
an eighth transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the drain or collector of the fifth transistor;
the output of the first output stage is connected to the source or emitter of the seventh transistor and the drain or collector of the eighth transistor;
The drain or collector of the seventh transistor and the source or emitter of the eighth transistor are connected to the output of the second output stage,
Be a comparator.
[4]
The comparator according to [1],
The shunt circuit is
is connected between the output of the first output stage and the connection point of the first differential transistor and the first load resistor, and the gate or base is connected to the drain or collector of the third transistor; a ninth transistor with
connected between the output of the second output stage and the connection point of the second differential transistor and the second load resistor, the gate or base being connected to the drain or collector of the fifth transistor a tenth transistor,
Be a comparator.
[5]
The comparator according to any one of [1] to [4],
The output circuit is
an eleventh transistor having a gate or base connected to the output of the first output stage;
a twelfth transistor having a gate or base connected to the output of the second output stage;
a thirteenth transistor connected in series with the eleventh transistor and having a gate or base connected to the drain or collector of the twelfth transistor;
outputting the output signal from a connection point between the eleventh transistor and the thirteenth transistor;
Be a comparator.
[6]
The comparator according to [5],
The output circuit is
a fourteenth transistor connected in series with the twelfth transistor and having a gate connected to a connection point between the eleventh transistor and the thirteenth transistor;
Be a comparator.
[7]
The comparator according to [5] or [6],
the threshold voltages of the eleventh transistor and the twelfth transistor are lower than the threshold voltages of the third to sixth transistors;
Be a comparator.
[8]
The comparator according to any one of [1] to [7],
at least one of said transistors is composed of a field effect transistor;
Be a comparator.
[9]
The comparator according to any one of [1] to [8],
at least one of said transistors is composed of a bipolar transistor;
Be a comparator.

According to the present invention, it is possible to provide a comparator with improved response characteristics without increasing circuit current.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following detailed description of the invention (hereinafter referred to as "embodiment") with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing the comparator of the present invention in the first embodiment. FIG. 2 is a circuit diagram showing the comparator of the present invention in the second embodiment. FIG. 3 is a circuit diagram showing the comparator of the present invention in the third embodiment. FIG. 4 is a circuit diagram showing the comparator of the present invention in the fourth embodiment. FIG. 5 is a circuit diagram showing the comparator of the present invention in the fifth embodiment. FIG. 6 is a circuit diagram showing an example of a conventional comparator.

Specific embodiments relating to the present invention will be described below with reference to each drawing.

(First embodiment)
First, the comparator 1 of the first embodiment will be described with reference to FIG. As shown in the figure, the comparator 1 has an inverting input potential INM (=first input potential) input to the inverting input terminal T11 and a non-inverting input potential INP (=second input potential) input to the non-inverting input terminal T12. input potential) and the comparison result is output from the output terminal T3. The comparator 1 includes a differential input section 2, a folded cascode section 31 (=first folded cascode section), a folded cascode section 32 (=second folded cascode section), a shunt circuit 4, and an output circuit 5;

The differential input unit 2 includes a differential transistor M1 (=first differential transistor) and a differential transistor M2 (=second differential transistor) whose sources are commonly connected, and loads connected to their drains. A resistor R1 (=first load resistor), a load resistor R2 (=second load resistor), and a constant current source 21 are provided.

The differential transistors M1 and M2 are composed of P-channel field effect transistors. The gate of the differential transistor M1 is connected to the inverting input terminal T11, and the gate of the differential transistor M2 is connected to the non-inverting input terminal T12. Sources of the differential transistors M1 and M2 are connected in common and connected to the constant current source 21 .

A load resistor R1 is connected in series with the differential transistor M1. Specifically, load resistor R1 is connected between the drain of differential transistor M1 and negative power supply terminal T22. A negative power supply voltage VSS is supplied to the negative power supply terminal T22. A load resistor R2 is connected in series with the differential transistor M2. Specifically, load resistor R2 is connected between the drain of differential transistor M2 and negative power supply terminal T22.

The constant current source 21 is connected between the positive power supply terminal T21 and the sources of the commonly connected differential transistors M1 and M2. A positive power supply voltage VDD is supplied to the positive power supply terminal T21. The differential input unit 2 divides the constant current I1 supplied by the constant current source 21 to the differential transistors M1 and M2. The current ratio (divided current ratio) of the currents flowing through the differential transistors M1 and M2 is a value corresponding to the inverting input potential INM input to the inverting input terminal T11 and the non-inverting input potential INP input to the non-inverting input terminal T12. Become.

The folded cascode unit 31 includes a transistor M31 (=third transistor) folded cascode-connected to the differential transistor M1, and a transistor M41 (=fourth transistor) folded cascode-connected to the differential transistor M2. , and constant current sources 311 and 312 . The transistors M31 and M41 are composed of N-channel field effect transistors.

The gate and drain of the transistor M31 are connected. The transistor M31 has a source connected to a connection point between the load resistor R1 and the drain of the differential transistor M1 and a drain connected to the constant current source 311 . The transistor M41 has its gate connected to the gate and drain of the transistor M31. The transistor M41 has a source connected to a connection point between the load resistor R2 and the drain of the differential transistor M2 and a drain connected to the constant current source 312 .

A constant current source 311 is connected between the drain of the transistor M31 and the positive power supply terminal T21. A constant current source 312 is connected between the drain of the transistor M41 and the positive power supply terminal T21.

In the folded cascode section 31, the transistor M31 and the transistor M41 are current-mirror-connected, and an output is taken out from a connection node A between the transistor M41 and the constant current source 312, which constitute the first output stage. .

The folded cascode unit 32 includes a transistor M32 (=fifth transistor) that is folded cascode-connected to the differential transistor M2, a transistor M42 (=sixth transistor) that is folded cascode-connected to the differential transistor M1, Constant current sources 321 and 322 are provided. The transistors M32 and M42 are composed of N-channel field effect transistors.

The gate and drain of the transistor M32 are connected. The transistor M32 has a source connected to a connection point between the load resistor R2 and the drain of the differential transistor M2 and a drain connected to the constant current source 321 . The transistor M42 has its gate connected to the gate and drain of the transistor M32. The transistor M42 has a source connected to a connection point between the load resistor R1 and the drain of the differential transistor M1 and a drain connected to the constant current source 322 .

A constant current source 321 is connected between the drain of the transistor M32 and the positive power supply terminal T21. A constant current source 322 is connected between the drain of the transistor M42 and the positive power supply terminal T21.

In the folded cascode section 32, the transistor M32 and the transistor M42 are current-mirror-connected, and the output is taken out from the connection node B between the transistor M42 and the constant current source 322 which form the second output stage. .

The current dividing circuit 4 is a circuit that divides the current flowing through the transistor M41 and flows it to the load resistor R1 when the current flowing through the load resistor R2 is larger than the current flowing through the load resistor R1. The current dividing circuit 4 divides the current flowing through the transistor M42 and flows it through the load resistor R2 when the current flowing through the load resistor R1 is larger than the current flowing through the load resistor R2.

The current dividing circuit 4 has a transistor M101 (=seventh transistor) and a transistor M102 (=eighth transistor). The transistors M101 and M102 are composed of P-channel field effect transistors. The transistor M101 has a source connected to the connection node A, a drain connected to the connection node B, and a gate connected to a connection point between the constant current source 311 and the drain of the transistor M31.

The transistor M102 has a source connected to the connection node B, a drain connected to the connection node A, and a gate connected to a connection point between the constant current source 321 and the drain of the transistor M32.

The output circuit 5 includes transistors M6 to M8 and a constant current source 51. FIG. The transistors M6 and M7 are composed of N-channel field effect transistors. The transistor M6 (=11th transistor) has a gate connected to the connection node A, a source connected to the negative power supply terminal T22, and a drain connected to the drain of the transistor M8 and the output terminal T3. The transistor M7 (12th transistor) has a gate connected to the connection node B, a source connected to the negative power supply terminal T22, and a drain connected to the constant current source 51 .

The transistor M8 (=thirteenth transistor) is composed of a P-channel field effect transistor. Transistor M8 is connected in series with transistor M6. More specifically, the transistor M8 has a gate connected to the connection point between the drain of the transistor M7 and the constant current source 51, a source connected to the positive power supply terminal T21, and a drain connected to the drain of the transistor M6 and the output terminal T3. ing. A constant current source 51 is connected between the positive power supply terminal T21 and the drain of the transistor M7.

Next, the operation of the comparator 1 having the configuration described above will be described. First, the operation when the inverting input potential INM is higher than the non-inverting input potential INP and the output signal VOUT of the output terminal T3 is in the Low state, that is, the output signal VOUT is substantially at the negative power supply voltage VSS will be described.

When the inverting input potential INM is higher than the non-inverting input potential INP, more current I1 from the constant current source 21 flows through the differential transistor M2 than through the differential transistor M1. This reduces the voltage drop across load resistor R1 and increases the voltage drop across load resistor R2.

Then, the gate-source potential difference of the transistor M41 becomes smaller than the gate-source potential difference of the transistor M31, and the transistor M41 is turned off. When the transistor M41 is turned off, the potential of the connection node A rises. When the potential of the connection node A rises and the gate-source potential difference of the transistor M6 reaches the threshold voltage, the transistor M6 is turned on.

Further, when the gate-source potential difference of the transistor M42 becomes larger than the gate-source potential difference of the transistor M32 and the transistor M42 is turned on, the potential of the connection node B decreases. When the potential of the connection node B drops and the gate-source potential difference of the transistor M7 falls below the threshold voltage, the transistor M7 is turned off.

When the transistor M7 is turned off, the drain potential of the transistor M7 rises. When the drain potential of the transistor M7 rises, the gate potential of the transistor M8 rises accordingly, turning off the transistor M8. As a result, the output signal VOUT of the output terminal T3 becomes Low.

Further, when the transistor M41 is turned off as described above, the drain potential of the transistor M41 rises and the transistor M101 is turned on. As a result, a portion of the current from the constant current source 312 flows from the source to the drain of the transistor M101 in the ON state, flows into the transistor M42, and increases the current flowing through the load resistor R1. Also, some of the current from constant current source 312 flows from the drain to the source due to the reverse operation of transistor M102 and into transistor M42, increasing the current through load resistor R1. As a result, the potential of the connection node B becomes higher than when the transistors M101 and M102 are not connected, and can be prevented from dropping to near the negative power supply voltage VSS.

Further, when the output signal VOUT is in the Low state, the transistor M101 clamps the potential of the connection node A to a voltage obtained by adding the gate-source potential difference of the transistor M101 to the drain potential of the transistor M31. As a result, the potential of the connection node A does not rise to near the positive power supply voltage VDD.

Next, the operation when the non-inverted input potential INP is higher than the inverted input potential INM and the output signal VOUT of the output terminal T3 is in a High state, that is, the output signal VOUT is substantially at the positive power supply voltage VDD will be described.

When the non-inverted input potential INP is higher than the inverted input potential INM, more current I1 from the constant current source 21 flows through the differential transistor M1 than through the differential transistor M2. This reduces the voltage drop across load resistor R2 and increases the voltage drop across load resistor R1.

Then, the gate-source potential difference of the transistor M41 becomes larger than the gate-source potential difference of the transistor M31, and the transistor M41 is turned on. When the transistor M41 is turned on, the potential of the connection node A is lowered. When the potential of the connection node A drops and the gate-source potential difference of the transistor M6 falls below the threshold voltage, the transistor M6 is turned off. As described above, when the output signal VOUT is in the Low state, the potential of the connection node A is suppressed from rising due to the clamping of the transistor M101. Therefore, at this time, the time from when the transistor M6 is turned on to when it is turned off can be shortened.

Further, when the gate-source potential difference of the transistor M42 becomes smaller than the gate-source potential difference of the transistor M32 and the transistor M42 is turned off, the potential of the connection node B increases. When the connection node B rises and the gate-source potential difference of transistor M7 reaches the threshold voltage, transistor M7 turns on. As described above, when the output signal VOUT is in the Low state, the potential of the connection node B is suppressed from dropping by part of the current from the constant current source 312 flowing into the load resistor R1. Therefore, the time required for the transistor M7 to turn on from off can be shortened.

When the transistor M7 is turned on, the drain potential of the transistor M7 is lowered. When the drain potential of the transistor M7 drops, the gate potential of the transistor M8 drops accordingly, turning on the transistor M8. As a result, the output signal VOUT of the output terminal T3 becomes High. As described above, the time required for the transistor M6 to turn off and the time for the transistor M7 to turn on can be shortened, so that the response speed until the output signal VOUT is inverted from the low state to the high state can be increased. can.

Further, when the transistor M42 is turned off as described above, the drain potential of the transistor M42 rises and the transistor M102 is turned on. As a result, part of the current from the constant current source 322 flows from the source to the drain of the transistor M102 in the ON state, flows into the transistor M41, and increases the current flowing through the load resistor R2. Also, some of the current from constant current source 322 flows from the drain to the source due to the reverse operation of transistor M101 and into transistor M41, increasing the current through load resistor R2. As a result, the potential of the connection node A becomes higher than when the transistors M101 and M102 are not connected, and can be prevented from dropping to near the negative power supply voltage VSS.

Further, when the output signal VOUT is in a High state, the transistor M102 clamps the potential of the connection node B to a voltage obtained by adding the gate-source potential difference of the transistor M102 to the drain potential of the transistor M32. As a result, the potential of the connection node B does not rise to near the positive power supply voltage VDD.

As described above, while the output signal VOUT is in the High state, it is possible to suppress an increase in the potential of the connection node B and a decrease in the potential of the connection node A. Therefore, when the output signal is inverted to the low state, the time required for the transistor M6 to turn on and the transistor M7 to turn off can be shortened. can be made faster.

By using transistors whose threshold voltages are lower than the threshold voltages of the transistors M31, M32, M41, and M42 as the transistors M6 and M7, the time required for the transistors M6 and M7 to change from the off state to the on state can be further shortened. be able to. Thereby, the response characteristics of the output circuit 5 can be further improved.

Thus, the comparator 1 in the first embodiment has the effect of improving the response characteristics without increasing the circuit current.

(Second embodiment)
Next, the comparator 1B of the second embodiment will be described with reference to FIG. 2, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1B includes a differential input section 2, a folded cascode section 31, a folded cascode section 32, a shunt circuit 4, and an output circuit 5B. The differential input section 2, the folded cascode section 31, the folded cascode section 32, and the shunt circuit 4 have already been described in the above-described first embodiment, so detailed description thereof will be omitted here.

The output circuit 5B has transistors M6 to M9. The output circuit 5B of the second embodiment replaces the constant current source 51 of the first embodiment with a transistor M9 (=14th transistor). The transistor M9 is composed of a P-channel field effect transistor. The transistor M9 has a gate connected to the output terminal T3, a source connected to the positive power supply terminal T21, and a drain connected to the drain of the transistor M7.

A comparator 1B of the second embodiment is basically the same as that of the first embodiment, except for points described later.

That is, in the first embodiment, when the transistor M7 is on, the drain current of the transistor M7 continues to flow as a steady current. In contrast, in the second embodiment, when the transistor M7 is on, the transistor M8 is turned on, and the gate potential of the transistor M9 rises. When the gate potential of the transistor M9 rises, the transistor M9 is turned off, so the drain current does not flow as a steady current when the transistor M7 is on.

Therefore, the comparator 1B in the second embodiment has the effect of reducing current consumption and improving response characteristics.

(Third Embodiment)
Next, a comparator 1C of the third embodiment will be described with reference to FIG. In FIG. 3, the same components as those in the circuits shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1C includes a differential input section 2, a folded cascode section 31, a folded cascode section 32, a shunt circuit 4C, and an output circuit 5B. Since the differential input section 2 and the folded cascode sections 31 and 32 have already been described in the first embodiment, detailed description thereof will be omitted here. Since the output circuit 5B has already been described in the above-described second embodiment, detailed description thereof will be omitted here.

The difference between the current dividing circuit 4 of the first embodiment and the current dividing circuit 4C of the third embodiment is the connection of the drains of the transistor M101C (=the ninth transistor) and the transistor M102C (=the tenth transistor). The drain of the transistor M101C of the third embodiment is connected to the connection point between the source of the transistor M42 and the load resistor R1. The drain of the transistor M102C of the third embodiment is connected to the connection point between the source of the transistor M41 and the load resistor R2.

A comparator 1C of the third embodiment is basically the same as that of the second embodiment, except for the points described later.

In the third embodiment, when the output signal VOUT of the output terminal T3 is in the Low state, part of the current from the constant current source 312 is connected to the source of the transistor M42 via the transistor M101C. increases the current flowing into Therefore, the gate potential of the transistor M7 becomes higher than when the transistor M101C is not connected, and the time required for the transistor M7 to change from the off state to the on state is shortened. Therefore, the propagation delay time for the output signal VOUT of the output terminal T3 to change from the Low state to the High state is shortened.

Also, when the output signal VOUT of the output terminal T3 is in a High state, part of the current from the constant current source 322 increases the current flowing into the load resistor R2 connected to the source of the transistor M41 via the transistor M102C. Let Therefore, the gate potential of the transistor M6 becomes higher than when the transistor M102C is not connected, and the time required for the transistor M6 to change from the off state to the on state is shortened. Therefore, the propagation delay time for the output signal VOUT of the output terminal T3 to change from the High state to the Low state is shortened.

Therefore, the comparator 1C of the third embodiment has the effect of reducing current consumption and improving response characteristics.

(Fourth embodiment)
Next, a comparator 1D according to the fourth embodiment will be described with reference to FIG. In FIG. 4, the same components as those in the circuits shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1D includes a differential input section 2, folded cascode sections 31 and 32, a current dividing circuit 4D, and an output circuit 5B. Since the differential input section 2 and the folded cascode sections 31 and 32 have already been described in the first embodiment, detailed description thereof will be omitted here. Since the output circuit 5B has already been described in the above-described second embodiment, detailed description thereof will be omitted here.

The difference between the current dividing circuit 4 of the first embodiment and the current dividing circuit 4D of the fourth embodiment is that the current dividing circuit 4D is composed only of the transistor M101 and does not include the transistor M102.

A comparator 1D of the fourth embodiment is basically the same as that of the second embodiment, except for the points described later.

In the fourth embodiment, when the output signal VOUT of the output terminal T3 is in the Low state, part of the current from the constant current source 312 flows from the source to the drain of the transistor M101 and then flows into the drain of the transistor M42. Increase the current through load resistor R1. Also, when the output signal VOUT of the output terminal T3 is in a High state, part of the current from the constant current source 322 flows from the drain to the source of the transistor M101, then flows into the drain of the transistor M41, and flows into the load resistor R2. Increase the current that flows.

Further, the transistor M101 clamps the potential of the junction node A to the voltage obtained by adding the gate-source potential difference of the transistor M101 to the drain potential of the transistor M31, and the potential of the junction node B to the drain potential of the transistor M31. By clamping the voltage to which the drain potential difference is added, the voltage does not rise to near the positive power supply voltage VDD.

(Fifth embodiment)
Next, the comparator 1E of the fifth embodiment will be described with reference to FIG. 5, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in the figure, the comparator 1E includes a differential input section 2E, a folded cascode section 31E, a folded cascode section 32E, a shunt circuit 4E, and an output circuit 5E, as in the first embodiment. ing.

The difference between the first embodiment and the fifth embodiment is that the transistors M1E, M2E, M31E, M41E, M32E, and M42E correspond to the transistors M1, M2, M31, M41, M32, M42, M6 to M8, M101, and M102. , M6E to M8E, M101E, and M102E are reversed in conductivity type. A difference between the first embodiment and the fifth embodiment is that the relationship between the positive power terminal T21 and the negative power terminal T22 is reversed.

Similarly, in the second to fourth embodiments, the conductivity type of the transistor may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.

It should be noted that the present invention is not limited to the above-described embodiments, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary and not limited as long as the present invention can be achieved.

In the first to fifth embodiments described above, the transistors are field effect transistors, but the present invention is not limited to this. At least one or more of the transistors may be replaced with bipolar transistors. In this case, the gate of the transistor can be read as the base, the source as the emitter, and the drain as the collector.

1, 1B, 1C, 1D, 1E comparator 2, 2E differential input section 4, 4C, 4D, 4E shunt circuit 5, 5B, 5E output circuit 31, 31E folded cascode section (first folded cascode section)
32, 32E folded cascode section (second folded cascode section)
INM inverting input potential (first input potential)
INP non-inverting input potential (second input potential)
M1, M1E differential transistors (first differential transistors)
M2, M2E differential transistors (second differential transistors)
M31, M31E transistors (third transistors)
M41, M41E transistors (fourth transistors)
M32, M32E transistors (fifth transistors)
M42, M42E transistor (sixth transistor)
M101, M101E transistors (seventh transistors)
M102, M102E transistors (eighth transistors)
M101C transistor (9th transistor)
M102C transistor (tenth transistor)
M6, M6E transistors (eleventh transistors)
M7, M7E transistors (twelfth transistors)
M8, M8E transistors (13th transistors)
M9 transistor (14th transistor)
R1, R1E load resistor (first load resistor)
R2, R2E load resistor (second load resistor)

Claims (9)

a first differential transistor and a second differential transistor through which currents having a current ratio corresponding to the first input potential and the second input potential flow respectively;
a first load resistor connected in series with the first differential transistor;
a differential input having a second load resistor connected in series with the second differential transistor;
a third transistor folded cascode-connected to the first differential transistor; a fourth transistor folded cascode-connected to the second differential transistor; a first folded cascode section constituting one output stage;
a fifth transistor folded cascode-connected to the second differential transistor; and a sixth transistor folded cascode-connected to the first differential transistor, wherein the sixth transistor is the first differential transistor. a second folded cascode unit constituting two output stages;
and an output circuit connected to the outputs of the first and second output stages to output an output signal,
When the current flowing through the second load resistor is larger than the current flowing through the first load resistor, the current flowing through the fourth transistor is divided to flow through the first load resistor, When the current flowing through the first load resistor is larger than the current flowing through the second load resistor, a shunt circuit that divides the current flowing through the sixth transistor and flows it through the second load resistor,
comparator. A comparator according to claim 1, wherein
The shunt circuit is
a seventh transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the drain or collector of the third transistor;
comparator. A comparator according to claim 2,
The shunt circuit is
an eighth transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the drain or collector of the fifth transistor;
the output of the first output stage is connected to the source or emitter of the seventh transistor and the drain or collector of the eighth transistor;
The drain or collector of the seventh transistor and the source or emitter of the eighth transistor are connected to the output of the second output stage,
comparator. A comparator according to claim 1, wherein
The shunt circuit is
is connected between the output of the first output stage and the connection point of the first differential transistor and the first load resistor, and the gate or base is connected to the drain or collector of the third transistor; a ninth transistor with
connected between the output of the second output stage and the connection point of the second differential transistor and the second load resistor, the gate or base being connected to the drain or collector of the fifth transistor a tenth transistor,
comparator. The comparator according to any one of claims 1 to 4,
The output circuit is
an eleventh transistor having a gate or base connected to the output of the first output stage;
a twelfth transistor having a gate or base connected to the output of the second output stage;
a thirteenth transistor connected in series with the eleventh transistor and having a gate or base connected to the drain or collector of the twelfth transistor;
outputting the output signal from a connection point between the eleventh transistor and the thirteenth transistor;
comparator. A comparator according to claim 5,
The output circuit is
a fourteenth transistor connected in series with the twelfth transistor and having a gate connected to a connection point between the eleventh transistor and the thirteenth transistor;
comparator. A comparator according to claim 5 or 6,
the threshold voltages of the eleventh transistor and the twelfth transistor are lower than the threshold voltages of the third to sixth transistors;
comparator. The comparator according to any one of claims 1 to 7,
at least one of said transistors is composed of a field effect transistor;
comparator. The comparator according to any one of claims 1 to 8,
at least one of said transistors is composed of a bipolar transistor;
comparator.

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