JP2024043401A - comparator - Google Patents

Abstract

The present invention provides a comparator with improved response characteristics without increasing circuit current.
SOLUTION: A transition period detection unit 4 detects connection nodes A and B, which are outputs of a first output stage of a first folded cascode unit 31 and a second output stage of a second folded cascode unit 32. The drain current I M101 or I M102 of the transistor _M101 or _M102 is supplied to the constant current generating section 5 except during the transition period of inversion, and the drain current I _M101 or I _M102 is cut off during the transition period. When the constant current generator 5 receives the drain current I _M101 or I _M102 from the transition period detector 4, it reduces the drain currents I _M51 and I M11 of the transistors M51 and _M11 .
[Selection diagram] Figure 1

Description

The present invention relates to a comparator.

It is believed that global warming is caused by the greenhouse effect of the atmosphere being intensified by the increase in the concentration of greenhouse gases such as _CO2 , and with the rapid development of the information and communication society, reducing the power consumption of electronic devices has become a major issue. Many semiconductor integrated circuits are used in electronic devices, and the main performance of comparators, which are widely used in semiconductor integrated circuits, is their response speed and current consumption. Since the response speed and current consumption of a comparator are inversely proportional to each other, this technology aims to improve the response characteristics to an input signal without increasing the current consumption, thereby contributing to the suppression of global warming.

A circuit as shown in FIG. 6 is known as a comparator used in a semiconductor integrated circuit (see, for example, Patent Document 1). The comparator 100 shown in FIG. 6 is configured with a differential input section 102, a folded cascode section 103, a constant current generation section 105, and an output circuit 106 as main components. Further, in a comparator having such a circuit configuration, response characteristics are improved by increasing the current generated by the constant current generating section 105.

The differential input section 102 includes differential transistors M1 and M2 whose sources are commonly connected, load resistors R1 and R2 whose drains are respectively connected, and a common source between the differential transistors M1 and M2 and a positive power supply voltage VDD. A transistor M12 is connected between the transistor M12 and the transistor M12, which supplies a constant current.

The folded cascode section 103 includes transistors M3 and M4 whose sources are connected to load resistors R1 and R2, respectively, and transistors M13 and M14 which supply a constant current and are connected between their drains and a positive power supply voltage VDD, respectively. and a transistor M5 whose drain and gate are connected to the drain of the transistor M4, and whose source is connected to the gate of the transistor M4. In the folded cascode section 103, the transistor M3 and the transistor M4 are connected in a current mirror manner, and the output is taken out from the connection point between the drain of the transistor M4 and the drain of the transistor M14.

The output circuit 106 includes a transistor M6 whose gate is connected to the output of the folded cascode unit 103 and whose source is connected to the negative power supply voltage VSS, and a constant current source 61 connected between its drain and the positive power supply voltage VDD. It is configured such that the output signal VOUT is taken out from the connection point between the transistor M6 and the constant current source 61.

Further, the transistor M5 suppresses the rise in the gate potential of the transistor M6, shortens the propagation delay time, and improves the power supply voltage dependence of the propagation delay time (see, for example, Non-Patent Document 1).

The constant current generating section 105 includes a resistor R5 and a transistor M51 whose source is connected to the negative power supply voltage VSS via the resistor R5 and whose gate is applied with a bias potential VB. The current generated by the constant current generating section 105 is supplied to the differential input section 102 and the folded cascode section 103 through transistors M12, M13, and M14 connected in a current mirror to the transistor M11.

Patent No. 4677284

Haruhiko Yoshida, Practical Design of CMOS Analog IC Circuits, CQ Publishing, 2010 (p144, Figure 4.10)

Conventional comparators with the above configuration had the problem that the circuit current had to be increased to improve the response characteristics.

The invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a comparator with improved response characteristics without increasing circuit current.

In order to achieve the above-mentioned object, a comparator according to the present invention has the following features [1] to [10].
[1]
a differential input section having a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a potential difference between a first input potential and a second input potential, a first load resistor connected in series to the first differential transistor, and a second load resistor connected in series to the second differential transistor;
a first folded cascode section including a third transistor connected in a folded cascode manner to the first differential transistor and a fourth transistor connected in a folded cascode manner to the second differential transistor, the fourth transistor constituting a first output stage;
a second folded cascode section including a fifth transistor connected in a folded cascode manner to the second differential transistor and a sixth transistor connected in a folded cascode manner to the first differential transistor, the sixth transistor constituting a second output stage;
an output circuit connected to outputs of the first output stage and the second output stage to output an output signal;
a current generating section for generating a first current to be supplied to the differential input section, the first folded cascode section, and the second folded cascode section;
a transition period detection unit that supplies a second current to the current generating unit during a period other than a transition period during which the outputs of the first output stage and the second output stage are inverted, and cuts off the second current during the transition period;
the current generating unit reduces the first current when the second current is supplied from the transition period detecting unit;
It is a comparator.
[2]
The comparator according to [1],
the current generating unit has a seventh transistor, a third resistor connected in series to the seventh transistor, and a fourth resistor connected in series to the third resistor,
the source or emitter of the seventh transistor is connected to the third resistor;
a terminal to which a third input potential is supplied is connected to a gate or a base of the seventh transistor;
the second current is supplied only to the fourth resistor;
A comparator in which a current flowing through the seventh transistor is generated as the first current.
[3]
The comparator according to [1],
the current generating unit includes an eighth transistor, a fifth resistor connected in series to the eighth transistor, a ninth transistor, and a sixth resistor connected in series to the ninth transistor;
the eighth transistor and the fifth resistor are connected in parallel with the ninth transistor and the sixth resistor;
the source or emitter of the eighth transistor is connected to the fifth resistor;
a terminal to which a third input potential is supplied is connected to the gate or base of the eighth transistor;
the source or emitter of the ninth transistor is connected to the sixth resistor;
the terminal to which the third input potential is supplied is connected to a gate or a base of the ninth transistor;
the second current is supplied only to the sixth resistor;
a sum of currents flowing through the eighth transistor and the ninth transistor is generated as the first current;
It is a comparator.
[4]
The comparator according to [1],
the transition period detection unit includes a tenth transistor and an eleventh transistor,
the source or emitter of the tenth transistor is connected to the output of the first output stage, and the gate or base is connected to the drain or collector of the third transistor;
the source or emitter of the eleventh transistor is connected to the output of the second output stage, and the gate or base is connected to the drain or collector of the fifth transistor;
The drain or collector of each of the tenth transistor and the eleventh transistor is connected to the current generating unit.
It is a comparator.
[5]
The comparator according to [1],
the transition period detection unit includes a twelfth transistor and a thirteenth transistor,
the source or emitter of the twelfth transistor is connected to the output of the first output stage, and the gate or base is connected to the source or emitter of the third transistor;
the source or emitter of the thirteenth transistor is connected to the output of the second output stage, and the gate or base is connected to the source or emitter of the fifth transistor;
The drain or collector of each of the twelfth transistor and the thirteenth transistor is connected to the current generating unit.
It is a comparator.
[6]
The comparator according to [1],
the output circuit includes a fourteenth transistor having a gate or a base connected to the output of the first output stage;
a fifteenth transistor having a gate or a base connected to the output of the second output stage;
a sixteenth transistor connected in series with the fourteenth transistor, the gate or base of the sixteenth transistor being connected to the drain or collector of the fifteenth transistor;
The output signal is output from a connection point between the fourteenth transistor and the sixteenth transistor.
It is a comparator.
[7]
[6] The comparator according to the present invention,
the output circuit has a seventeenth transistor connected in series with the fifteenth transistor and having a gate or a base connected to a connection point between the fourteenth transistor and the sixteenth transistor;
It is a comparator.
[8]
[6] The comparator according to the present invention,
a threshold voltage of the fourteenth transistor and the fifteenth transistor is lower than a threshold voltage of the third transistor to the sixth transistor;
It is a comparator.
[9]
[8] The comparator according to any one of [1] to [8],
At least one of the transistors is a field effect transistor.
It is a comparator.
[10]
[8] The comparator according to any one of [1] to [8],
At least one of the transistors is a bipolar transistor.
It is a comparator.

According to the present invention, a comparator with improved response characteristics can be provided without increasing circuit current.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the mode for carrying out the invention (hereinafter referred to as "embodiment") described below with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing a comparator of the present invention in a first embodiment. FIG. 2 is a circuit diagram showing a comparator according to a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a comparator according to a third embodiment of the present invention. FIG. 4 is a circuit diagram showing a comparator of the present invention in a fourth embodiment. FIG. 5 is a circuit diagram showing a comparator according to a fifth embodiment of the present invention. FIG. 6 is a circuit diagram showing an example of a conventional comparator.

Specific embodiments of the present invention will be described below with reference to each figure.

(First embodiment)
First, the comparator 1 of the first embodiment will be explained with reference to FIG. 1. As shown in the figure, the comparator 1 has an inverting input potential INM (=first input potential) input to the inverting input terminal T11 and a non-inverting input potential INP (=second input potential) input to the non-inverting input terminal T12. (input potential)) and outputs the comparison result from the output terminal T3. The comparator 1 includes a differential input section 2, a folded cascode section 31 (=first folded cascode section), a folded cascode section 32 (=second folded cascode section), and a transition period detection section 4. , a constant current generating section 5 (=current generating section), and an output circuit 6.

The differential input section 2 includes a differential transistor M1 (=first differential transistor) and a differential transistor M2 (=second differential transistor) whose sources are commonly connected, and loads each connected to their drains. It includes a resistor R1 (=first load resistor), a load resistor R2 (=second load resistor), and a transistor M12 that supplies a constant current.

The differential transistors M1, M2 and transistor M12 are composed of P-channel field effect transistors. The gate of the differential transistor M1 is connected to the inverting input terminal T11, and the gate of the differential transistor M2 is connected to the non-inverting input terminal T12. The sources of the differential transistors M1 and M2 are connected to the transistor M12.

The load resistor R1 is connected between the drain of the differential transistor M1 and the negative power supply terminal T22, and the negative power supply terminal T22 is supplied with the negative power supply voltage VSS. The load resistor R2 is connected between the drain of the differential transistor M2 and the negative power supply terminal T22.

The transistor M12 has a source connected to the positive power supply terminal T21, and a drain connected to the respective sources of the differential transistors M1 and M2. A positive power supply voltage VDD is supplied to the positive power supply terminal T21. The differential input section 2 shunts the current I _M12 supplied by the transistor M12 to the differential transistors M1 and M2. The current ratio (division ratio) of the currents flowing through the differential transistors M1 and M2 has a value according to the potential difference between the inverting input potential INM and the non-inverting input potential INP.

The folded cascode section 31 includes a transistor M31 (=third transistor) connected in folded cascode to the differential transistor M1, and a transistor M41 (=fourth transistor) connected in folded cascode to the differential transistor M2. , transistors M13 and M14.

The transistors M31 and M41 are composed of N-channel field effect transistors, and the transistors M13 and M14 are composed of P-channel field effect transistors. The gate and drain of the transistor M31 are connected. The transistor M31 has a source connected to a connection point between the load resistor R1 and the drain of the differential transistor M1, and a drain connected to the drain of the transistor M13. The gate of the transistor M41 is connected to the gate and drain of the transistor M31. The transistor M41 has a source connected to a connection point between the load resistor R2 and the drain of the differential transistor M2, and a drain connected to the drain of the transistor M14.

Transistor M13 is connected between the drain of transistor M31 and positive power supply terminal T21. Transistor M14 is connected between the drain of transistor M41 and positive power supply terminal T21.

In the folded cascode section 31, the transistor M31 and the transistor M41 are connected in a current mirror, and the output is taken out at the connection point (=connection node A) between the transistor M41 and the transistor M14 that constitute the first output stage. It is configured.

The folded cascode section 32 includes a transistor M32 (=fifth transistor) connected in folded cascode to the differential transistor M2, a transistor M42 (=sixth transistor) connected in folded cascode to the differential transistor M1, It includes transistors M15 and M16.

Transistors M32 and M42 are composed of N-channel field effect transistors, and transistors M15 and M16 are composed of P-channel field effect transistors. The gate and drain of transistor M32 are connected. The source of transistor M32 is connected to the connection point between load resistor R2 and the drain of differential transistor M2, and the drain is connected to the drain of transistor M15. The gate of transistor M42 is connected to the gate and drain of transistor M32. The source of transistor M42 is connected to the connection point between load resistor R1 and the drain of differential transistor M1, and the drain is connected to the drain of transistor M16.

Transistor M15 is connected between the drain of transistor M32 and positive power supply terminal T21. Transistor M16 is connected between the drain of transistor M42 and positive power supply terminal T21.

In the folded cascode section 32, the transistor M32 and the transistor M42 are connected in a current mirror, and the output is taken out at the connection point (=connection node B) between the transistor M42 and the transistor M16 that constitutes the second output stage. It is configured.

The transition period detection unit 4 includes a transistor M101 (=10th transistor) and a transistor M102 (=11th transistor), and when it is not a transition period in which the outputs of connection nodes A and B are inverted, the transistor M101 and transistor M102 are This circuit supplies drain currents I _M101 and I _M102 (=second current) to the constant current generating section 5, and cuts off the drain currents I M101 and I _M102 of the transistors M101 and _M102 during the transition period. To explain in detail the case where it is not a transition period, if the current flowing through the load resistor R2 is larger than the current flowing through the load resistor R1, the transition period detection unit 4 divides the current supplied from the transistor M14 via the transistor M101. This circuit is used to supply a constant current to the constant current generator 5. Further, when the current flowing through the load resistor R1 is larger than the current flowing through the load resistor R2, the current supplied from the transistor M16 is shunted through the transistor M102, and the current is shunted to the constant current generating section 5.

Transistors M101 and M102 are composed of P-channel field effect transistors. The source of transistor M101 is connected to connection node A, and the gate is connected to the connection point between the drain of transistor M13 and the drain of transistor M31. The source of transistor M102 is connected to connection node B, and the gate is connected to the connection point between the drain of transistor M15 and the drain of transistor M32.

The constant current generating section 5 includes a transistor M51 (=seventh transistor), a transistor M11, a resistor R51 (=third resistor), a resistor R52 (=fourth resistor), and a bias terminal. A constant current source that generates a constant current according to the bias potential VB (=third input potential) input to T13 (=terminal) and supplies current to the differential input section 2 and folded cascode sections 31 and 32. It constitutes a circuit.

Transistor M51 is composed of an N-channel field effect transistor. The transistor M51 has a source connected to the resistor R51, a gate connected to the bias potential VB, and a drain connected to the drain and gate of the transistor M11. The resistor R52 is connected between the resistor R51 and the negative power supply terminal T22, and the connection point between the resistor R51 and the resistor R52 is connected to the respective drains of the transistors M101 and M102.

The transistor M11 is composed of a P-channel field effect transistor. The transistor M11 has a source connected to the positive power supply terminal T21, and a gate and a drain connected to the gates of the transistors M12, M13, M14, M15, and M16. That is, the transistors M12, M13, M14, M15, and M16 are connected to the transistor M11 in a current mirror, and copy and return the current flowing through the transistor M11.

The output circuit 6 includes a transistor M6 (= the 14th transistor), a transistor M7 (= the 15th transistor), a transistor M8 (= the 16th transistor), and a constant current source 61.

Transistors M6 and M7 are composed of N-channel field effect transistors. The transistor M6 has a gate connected to the connection node A, a source connected to the negative power supply terminal T22, and a drain connected to the drain of the transistor M8 and the output terminal T3. The transistor M7 has a gate connected to the connection node B, a source connected to the negative power supply terminal T22, and a drain connected to the constant current source 61.

Transistor M8 is composed of a P-channel field effect transistor. The transistor M8 is connected in series to the transistor M6, has a gate connected to the connection point between the drain of the transistor M7 and the constant current source 61, has a source connected to the positive power supply terminal T21, and has a drain connected to the drain of the transistor M6 and the output terminal T3. It is connected to the. Constant current source 61 is connected between positive power supply terminal T21 and the drain of transistor M7.

Next, the operation of the comparator 1 having the above-described configuration will be explained. First, the operation will be described when the inverting input potential INM is higher than the non-inverting input potential INP and the output signal VOUT of the output terminal T3 is in the Low state, that is, the output signal VOUT is approximately at the negative power supply voltage VSS.

When the inverting input potential INM is higher than the non-inverting input potential INP, more current _IM12 from the transistor M12 that supplies a constant current flows through the differential transistor M2 than the differential transistor M1. Therefore, the voltage drop across load resistor R1 decreases and the voltage drop across load resistor R2 increases.

Then, the gate-source potential difference of transistor M41 becomes smaller than the gate-source potential difference of transistor M31, transistor M41 turns off, and transistor M31 turns on. When transistor M41 turns off, the potential of connection node A rises. When the potential of connection node A rises and the gate-source potential difference of transistor M6 reaches the threshold voltage, transistor M6 turns on.

The gate-source potential difference of transistor M42 becomes larger than the gate-source potential difference of transistor M32, transistor M42 turns on, and transistor M32 turns off. When transistor M42 turns on, the potential of connection node B drops. When the potential of connection node B drops and the gate-source potential difference of transistor M7 falls below the threshold voltage, transistor M7 turns off.

When transistor M7 is turned off, the drain potential of transistor M7 increases. When the drain potential of the transistor M7 rises, the gate potential of the transistor M8 rises accordingly, turning off the transistor M8. As a result, the output signal VOUT of the output terminal T3 becomes a Low state.

Further, when the transistor M41 is turned off, the drain potential of the transistor M41 increases, and the transistor M101 is turned on. When the transistor M42 is turned on, the drain potential of the transistor M42 decreases, and the transistor M102 is turned off. That is, when the output signal VOUT of the output terminal T3 is in the Low state (=non-transition period), the current from the transistor M14 flows into the resistor R52 via the transistor M101 in the on state. Current from transistor M14 does not flow through resistor R51.

Next, the operation during the transition period in which the inverted input potential INM becomes lower than the non-inverted input potential INP and the output signal VOUT of the output terminal T3 transits from the Low state to the High state will be described.

During the transition period, the current flowing through the differential transistor M1 increases, the current flowing through the differential transistor M2 decreases, and the voltage drop difference between the load resistors R1 and R2 becomes smaller. Thereafter, after the currents flowing through the differential transistors M1 and M2 become equal and the voltage drop difference between the load resistors R1 and R2 becomes equal, the current flowing through the differential transistor M1 becomes larger than that flowing through the differential transistor M2. When the voltage drop difference between the load resistors R1 and R2 becomes smaller, both transistors M41 and M42 are turned on, and both transistors M101 and M102 are turned off. Therefore, the current flowing from the transistor M14 through the transistor M101 does not flow into the resistor R52.

The drain current I _M11 (=first current) of transistor M11 during the transition period when the output signal VOUT goes from a low state to a high state is expressed by Equation 1, and the drain current I _{M11_L} of transistor M11 when the output signal VOUT is in a low state (=non-transition period) is expressed by Equation 2.

Here, I _M51 is the drain current of transistor M51 during the transition period, I _{M51_L} is the drain current of transistor M51 when the output signal VOUT is in the low state (=non-transition period), VB is the bias potential, V _gsM51 is the gate-source potential of transistor M51, and I _M101 is the drain current of transistor M101.

In other words, when the output signal VOUT of the output terminal T3 is in the Low state (=non-transition period), the drain currents of the transistors M11 and M51 decrease compared to the transition period in which the output signal VOUT of the output terminal T3 goes from the Low state to the High state. . This is because the voltage drop across resistor R52 increases by the amount of current supplied to resistor R52 via transistor M101, and the potential applied across resistor R51 decreases, reducing the current flowing through resistor R51. It's for a reason.

Next, the operation when the non-inverting input potential INP is higher than the inverting input potential INM and the output signal VOUT of the output terminal T3 is in a High state, that is, the output signal VOUT is approximately equal to the positive power supply voltage VDD will be described.

When the non-inverting input potential INP is higher than the inverting input potential INM, a larger current I _M12 flows from the transistor M12 that supplies a constant current to the differential transistor M1 than to the differential transistor M2, so that the voltage drop across the load resistor R2 decreases and the voltage drop across the load resistor R1 increases.

Then, the gate-source potential difference of the transistor M41 becomes larger than the gate-source potential difference of the transistor M31, so that the transistor M41 is turned on and the transistor M31 is turned off. When the transistor M41 is turned on, the potential of the connection node A decreases. When the potential of the connection node A decreases and the gate-source potential difference of the transistor M6 becomes less than the threshold voltage, the transistor M6 is turned off.

The gate-source potential difference of transistor M42 becomes smaller than the gate-source potential difference of transistor M32, transistor M42 turns off, and transistor M32 turns on. When transistor M42 turns off, the potential of connection node B rises. When the potential of connection node B rises and the gate-source potential difference of transistor M7 reaches the threshold voltage, transistor M7 turns on.

When transistor M7 is turned on, the drain potential of transistor M7 drops. When the drain potential of transistor M7 drops, the gate potential of transistor M8 drops accordingly, turning transistor M8 on. As a result, the output signal VOUT of output terminal T3 goes high.

Further, when the transistor M42 is turned off, the drain potential of the transistor M42 increases, and the transistor M102 is turned on. When the transistor M41 is turned on, the drain potential of the transistor M41 decreases, and the transistor M101 is turned off. That is, when the output signal VOUT of the output terminal T3 is in the High state (=non-transition period), the current from the transistor M16 flows into the resistor R52 via the transistor M102 in the on state.

Next, the operation during the transition period in which the inverted input potential INM becomes higher than the non-inverted input potential INP and the output signal VOUT of the output terminal T3 transits from the High state to the Low state will be described.

During the transition period, the current flowing through the differential transistor M1 decreases, the current flowing through the differential transistor M2 increases, and the voltage drop difference between the load resistors R1 and R2 decreases. Thereafter, after the currents flowing through the differential transistors M1 and M2 become equal and the voltage drop differences between the load resistors R1 and R2 become equal, the current flowing through the differential transistor M2 becomes larger than that flowing through the differential transistor M1. When the voltage drop difference between the load resistors R1 and R2 becomes smaller, both transistors M41 and M42 are turned on, and both transistors M101 and M102 are turned off. Therefore, the current flowing from transistor M16 through transistor M102 does not flow into resistor R52.

The drain current I _M11 of the transistor M11 during the transition period from the High state to the Low state of the output signal VOUT is expressed by Formula 1, and the drain current I M11 of the transistor M11 when the output signal VOUT is the High state (=non-transition period) _{M11_H} is expressed by Equation 3.

Here, I _{M51_H} is the drain current of the transistor M51 when the output signal VOUT is in the High state (= non-transition period), VB is the bias potential, V _gsM51 is the gate-source potential of the transistor M51, and I _M102 is the drain current of the transistor M102. It is.

In other words, when the output signal VOUT of the output terminal T3 is in the High state (=non-transition period), the drain currents of the transistors M11 and M51 decrease compared to the transition period in which the output signal VOUT of the output terminal T3 goes from the High state to the Low state. . This is because the voltage drop across resistor R52 increases by the amount of current supplied to resistor R52 via transistor M102, and the potential applied across resistor R51 decreases, reducing the current flowing through resistor R51. It's for a reason.

That is, during the transition period when the output signal VOUT is inverted, the drain current of the transistor M51 does not decrease. In other words, during the transition period when the output signal VOUT is inverted, the drain current of the transistor M51 increases compared to the non-transition period.

As a result, in the transition period compared to the non-transition period, the current flowing through transistor M11 increases, and the drain currents of transistors M12, M13, M14, M15, and M16, which are current mirror connected to transistor M11 and copy and fold back the current flowing through transistor M11, also increase.

In other words, the comparator 1 in this first embodiment temporarily increases the current supplied to the differential input section 2 and the folded cascode sections 31 and 32 during the transition period when the outputs of the folded cascode sections 31 and 32 are inverted.

As a result, the response characteristics are improved without increasing current consumption.

In addition, in the first embodiment described above, folded cascode sections 31 and 32 are provided, and the gates of transistors M6 and M7 constituting the output circuit 6 are controlled by a differential output signal generated between connection nodes A and B, thereby improving the response characteristics of the change in the output signal VOUT.

Note that by using transistors M6 and M7 that have a lower threshold voltage than the transistors M31, M32, M41, and M42 that constitute the folded cascode sections 31 and 32, the transistors M6 and M7 change from an off state to an on state. The time required to do so can be further reduced. Thereby, the response characteristics of the output circuit 6 can be further improved.

Furthermore, when the output signal VOUT is in a low state, the transistor M101 clamps the potential of the connection node A to a voltage obtained by adding the gate potential of the transistor M31 to the gate-source potential difference of the transistor M101, and does not allow it to rise to near the positive power supply voltage VDD. This shortens the time it takes for the transistor M6 to change from on to off, and increases the response speed at which the output signal VOUT inverts from a low state to a high state.

Furthermore, when the output signal VOUT is in a High state, the transistor M102 clamps the potential of the connection node B at a voltage equal to the gate potential of the transistor M32 plus the gate-source potential difference of the transistor M102, and does not allow it to rise to near the positive power supply voltage VDD. . Thereby, the time during which the transistor M7 is turned from on to off can be shortened, and the response speed at which the output signal VOUT is inverted from a high state to a low state can be increased.

In other words, the transistors M101 and M102, like the transistor M5 in the conventional comparator circuit configuration example shown in FIG. 6, have improved response characteristics and play a role in improving the power supply voltage dependence of the response characteristics. Also plays a role.

Second Embodiment
Next, a comparator 1B according to a second embodiment will be described with reference to Fig. 2. In Fig. 2, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1B includes a differential input section 2, folded cascode sections 31 and 32, a transition period detection section 4, a constant current generation section 5, and an output circuit 6B. The differential input section 2, folded cascode sections 31 and 32, transition period detection section 4, and constant current generation section 5 have already been explained in the first embodiment, so detailed explanation will be omitted here.

The output circuit 6B includes transistors M6, M7, M8, and M9. In the output circuit 6B of the second embodiment, the constant current source 61 of the first embodiment is replaced with a transistor M9 (=17th transistor). Transistor M9 is composed of a P-channel field effect transistor. The transistor M9 has a gate connected to the output terminal T3, a source connected to the positive power supply terminal T21, and a drain connected to the drain of the transistor M7.

The comparator 1B of the second embodiment is basically the same as that of the first embodiment except for the points described later.

That is, in the first embodiment, when the transistor M7 is in the on state, the drain current of the transistor M7 continues to flow as a steady current. On the other hand, in the second embodiment, when the transistor M7 is in the on state, the transistor M8 is in the on state, and the gate potential of the transistor M9 is increased. When the gate potential of the transistor M9 increases, the transistor M9 is turned off, so that the drain current of the transistor M7 does not flow as a steady current when the transistor M7 is on.

Therefore, the comparator 1B in this second embodiment has the effects of reducing current consumption and improving response characteristics.

(Third embodiment)
Next, a comparator 1C according to the third embodiment will be described with reference to FIG. 3. In FIG. 3, the same components as those in the circuits shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

The comparator 1C includes a differential input section 2, folded cascode sections 31 and 32, a transition period detection section 4, a constant current generation section 5C, and an output circuit 6B. The differential input section 2, folded cascode sections 31 and 32, and transition period detection section 4 have already been described in the first embodiment, so detailed explanation will be omitted here. Since the output circuit 6B has already been explained in the second embodiment, detailed explanation will be omitted here.

The constant current generating section 5C includes a transistor M51C (=eighth transistor), a transistor M52C (=9th transistor), a transistor M11C, a resistor R51C (=fifth resistor), and a resistor R52C (=sixth transistor). (resistor)), and constitutes a constant current source circuit that generates a constant current according to the bias potential VB and supplies the current to the differential input section 2 and folded cascode sections 31 and 32.

Transistors M51C and M52C are composed of N-channel field effect transistors. The source of the transistor M51C is connected to the negative power supply terminal T22 via the resistor R51C, and the bias potential VB is applied to the gate. The transistor M52C has a source connected to the negative power supply terminal T22 via a resistor R52C, and a bias potential VB applied to the gate.

The drains of transistors M101 and M102 are connected to the connection point between the source of transistor M52C and resistor R52C.

The comparator 1C of the third embodiment is basically the same as that of the second embodiment except for the points described later.

When the output signal VOUT of the output terminal T3 is in the Low state (=non-transition period), the current from the transistor M14 flows into the resistor R52C via the transistor M101 in the on state.

When the output signal VOUT of the output terminal T3 is in the High state (=non-transition period), the current from the transistor M16 flows into the resistor R52C via the transistor M102 in the on state.

During the transition period in which the output signal VOUT of the output terminal T3 is inverted, both transistors M101 and M102 are turned off, and the current flowing from the transistors M14 and M16 through the transistors M101 and M102 does not flow into the resistor R52C.

The drain current I _M11C of the transistor M11C during the transition period when the output signal VOUT is inverted is expressed by Equation 4, and the drain current I _{M11C_L} of the transistor M11C when the output signal VOUT is in the Low state (=non-transition period) is expressed by Equation 5, and the output signal The drain current I _{M11C_H} of the transistor M11C when VOUT is in the High state (=non-transition period) is expressed by Equation 6.

Here, I _M52C is the drain current of the transistor M52C during the transition period, I _{M52C_L} is the drain current of the transistor M52C when the output signal VOUT is in the Low state (= non-transition period), and I _{M52C_H} is the drain current of the transistor M52C when the output signal VOUT is in the High state (= non-transition period). VB is the bias potential.

That is, in contrast to the transition period in which the output signal VOUT of the output terminal T3 is inverted, when the output signal VOUT is in a Low state or a High state (=non-transition period), the drain currents of the transistors M11C and M52C decrease.

That is, during the transition period in which the output signal VOUT is inverted, the drain current of the transistor M52C does not decrease. In other words, during the transition period in which the output signal VOUT is inverted, the drain current of the transistor M52C increases compared to the non-transition period. Furthermore, the drain current of the transistor M11C is the sum of the drain current of the transistor M51C and the drain current of the transistor M52C, and the drain current of the transistor M11C also increases.

As a result, in the transition period compared to the non-transition period, the current flowing through the transistor M11C increases, and the transistors M12, M13, M14, M15, M16 are connected to the transistor M11C in a current mirror and copy and fold back the current flowing through the transistor M11C. The drain current also increases.

In other words, the comparator 1C in the third embodiment temporarily increases the current supplied to the differential input section 2 and the folded cascode sections 31 and 32 during the transition period when the outputs of the folded cascode sections 31 and 32 are inverted. let

Therefore, the effect of improving response characteristics can be obtained without increasing current consumption.

(Fourth embodiment)
Next, a comparator 1D according to the fourth embodiment will be described with reference to FIG. 4. In FIG. 4, the same components as those in the circuits shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

The comparator 1D includes a differential input section 2, folded cascode sections 31 and 32, a transition period detection section 4D, a constant current generation section 5, and an output circuit 6B. The differential input section 2, folded cascode sections 31 and 32, and constant current generation section 5 have already been explained in the first embodiment, so detailed explanation will be omitted here. Since the output circuit 6B has already been explained in the second embodiment, detailed explanation will be omitted here.

The difference between the transition period detection unit 4 of the first embodiment and the transition period detection unit 4D of the fourth embodiment is the connection of the gates of the transistor M101D (=12th transistor) and the transistor M102D (=13th transistor). It is. The gate of the transistor M101D of the fourth embodiment is connected to the connection point between the source of the transistor M31 and the load resistor R1. The gate of the transistor M102D of the fourth embodiment is connected to the connection point between the source of the transistor M32 and the load resistor R2.

The comparator 1D of the fourth embodiment is basically the same as that of the second embodiment except for the points described later.

When the output signal VOUT is in the Low state, the transistor M101D clamps the potential of the connection node A at a voltage equal to the source potential of the transistor M31 plus the gate-source potential difference of the transistor M101D, and does not allow it to rise to near the positive power supply voltage VDD. As a result, the time during which the transistor M6 turns from on to off can be shortened, and the response speed at which the output signal VOUT is inverted from a low state to a high state can be increased.

Furthermore, when the output signal VOUT is in a High state, the transistor M102D clamps the potential of the connection node B to the voltage obtained by adding the gate-source potential difference of the transistor M102D to the source potential of the transistor M32, and does not allow it to rise to near the positive power supply voltage VDD. . Thereby, the time during which the transistor M7 is turned from on to off can be shortened, and the response speed at which the output signal VOUT is inverted from a high state to a low state can be increased.

In other words, the transistors M101D and M102D, like the transistor M5 in the conventional comparator circuit configuration example shown in FIG. 6, have improved response characteristics and play a role in improving the power supply voltage dependence of the response characteristics. Also plays a role.

In other words, the transition period detection section 4D is basically the same as the transition period detection section 4, except that the voltage value clamped when the connection nodes A and B rise is different.

Therefore, the comparator 1D in the fourth embodiment has the effect of improving response characteristics without increasing current consumption.

Furthermore, in the fourth embodiment described above, the gate of the transistor M101D is connected to the connection point between the source of the transistor M31 and the load resistor R1, and the gate of the transistor M102D is connected to the connection point between the source of the transistor M32 and the load resistor R2. connected to, but not limited to. The same effect can be obtained by connecting the gate of transistor M101D to the connection point between the source of transistor M32 and load resistor R2, and connecting the gate of transistor M102D to the connection point between the source of transistor M31 and load resistor R1. It's something you can get.

(Fifth embodiment)
Next, a comparator 1E according to a fifth embodiment will be described with reference to FIG. 5. In FIG. 5, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

As shown in the figure, the comparator 1E includes a differential input section 2E, folded cascode sections 31E and 32E, a transition period detection section 4E, a constant current generation section 5E, and an output It is equipped with a circuit 6E.

The difference between the first embodiment and the fifth embodiment is that the transistors M1E, M2E, and M31E correspond to the transistors M1, M2, M31, M32, M41, M42, M6 to M8, M11 to M16, M101, M102, and M51. , M32E, M41E, M42E, M6E to M8E, M11E to M16E, M101E, M102E, and M51E have their conductivity types reversed. The difference between the first embodiment and the fifth embodiment is that the relationship between the positive power terminal T21 and the negative power terminal T22 is reversed.

Similarly, in the second to fourth embodiments, the conductivity types of the transistors may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.

Similarly to the first embodiment, the fifth embodiment also has the effect of improving response characteristics without increasing current consumption.

Note that the present invention is not limited to the embodiments described above, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, arrangement location, etc. of each component in the above-described embodiments are arbitrary as long as the present invention can be achieved, and are not limited.

For example, in the first to fifth embodiments described above, the transistor is composed of a field effect transistor, but the present invention is not limited to this. At least one or more of the transistors may be replaced with a bipolar transistor. In this case, the gate of the transistor can be read as the base, the source as the emitter, and the drain as the collector.

1, 1B to 1E Comparator 2, 2E Differential input section 4, 4D, 4E Transition period detection section 5, 5C, 5E Constant current generation section (current generation section)
6, 6B, 6E: output circuit 31, 31E: folded cascode unit (first folded cascode unit)
32, 32E Folded cascode unit (second folded cascode unit)
I _M11 , I _M11C , I _M11E drain current (first current)
I _M101 , I _M102 drain current (second current)
INM Inverted input potential (first input potential)
INP Non-inverting input potential (second input potential)
M1, M1E Differential transistor (first differential transistor)
M2, M2E Differential transistor (second differential transistor)
M6, M6E transistor (14th transistor)
M7, M7E transistors (15th transistor)
M8, M8E transistors (16th transistor)
M9 transistor (17th transistor)
M31, M31E transistors (third transistors)
M32, M32E transistor (fifth transistor)
M41, M41E transistor (fourth transistor)
M42, M42E transistors (sixth transistors)
M51, M51E transistors (seventh transistor)
M51C transistor (8th transistor)
M52C transistor (9th transistor)
M101, M101E transistors (tenth transistors)
M101D Transistor (12th Transistor)
M102, M102E transistors (11th transistor)
M102D Transistor (13th Transistor)
R1, R1E Load resistor (first load resistor)
R2, R2E Load resistor (second load resistor)
R51, R51E Resistor (third resistor)
R51C Resistor (5th resistor)
R52C Resistor (6th Resistor)
R52, R52E Resistor (fourth resistor)
T13 Bias terminal (terminal)
VB Bias potential (third input potential)

Claims (10)

a differential input section having a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a potential difference between a first input potential and a second input potential, a first load resistor connected in series to the first differential transistor, and a second load resistor connected in series to the second differential transistor;
a first folded cascode section including a third transistor connected in a folded cascode manner to the first differential transistor and a fourth transistor connected in a folded cascode manner to the second differential transistor, the fourth transistor constituting a first output stage;
a second folded cascode section including a fifth transistor connected in a folded cascode manner to the second differential transistor and a sixth transistor connected in a folded cascode manner to the first differential transistor, the sixth transistor constituting a second output stage;
an output circuit connected to outputs of the first output stage and the second output stage to output an output signal;
a current generating section for generating a first current to be supplied to the differential input section, the first folded cascode section, and the second folded cascode section;
a transition period detection unit that supplies a second current to the current generating unit when it is not a transition period in which the outputs of the first output stage and the second output stage are inverted, and cuts off the second current during the transition period;
the current generating unit reduces the first current when the second current is supplied from the transition period detecting unit;
comparator. The comparator according to claim 1,
The current generating section includes a seventh transistor, a third resistor connected in series to the seventh transistor, and a fourth resistor connected in series to the third resistor,
a source or emitter of the seventh transistor is connected to the third resistor;
A terminal to which a third input potential is supplied is connected to the gate or base of the seventh transistor,
the second current is supplied only to the fourth resistor,
A comparator in which a current flowing through the seventh transistor is generated as the first current. The comparator according to claim 1,
The current generating section includes an eighth transistor, a fifth resistor connected in series with the eighth transistor, a ninth transistor, and a sixth resistor connected in series with the ninth transistor. and
the eighth transistor and the fifth resistor, the ninth transistor and the sixth resistor are connected in parallel,
a source or emitter of the eighth transistor is connected to the fifth resistor,
A terminal to which a third input potential is supplied is connected to the gate or base of the eighth transistor,
a source or emitter of the ninth transistor is connected to the sixth resistor;
The terminal to which the third input potential is supplied is connected to the gate or base of the ninth transistor,
the second current is supplied only to the sixth resistor,
A sum of currents flowing through the eighth transistor and the ninth transistor is generated as the first current.
comparator. The comparator according to claim 1,
The transition period detection section includes a tenth transistor and an eleventh transistor,
The source or emitter of the tenth transistor is connected to the output of the first output stage, and the gate or base is connected to the drain or collector of the third transistor,
The source or emitter of the eleventh transistor is connected to the output of the second output stage, and the gate or base is connected to the drain or collector of the fifth transistor,
a drain or a collector of each of the tenth transistor and the eleventh transistor is connected to the current generating section;
comparator. The comparator according to claim 1,
The transition period detection section includes a twelfth transistor and a thirteenth transistor,
The source or emitter of the twelfth transistor is connected to the output of the first output stage, and the gate or base is connected to the source or emitter of the third transistor,
The source or emitter of the thirteenth transistor is connected to the output of the second output stage, and the gate or base is connected to the source or emitter of the fifth transistor,
a drain or a collector of each of the twelfth transistor and the thirteenth transistor is connected to the current generating section;
comparator. 2. The comparator of claim 1,
the output circuit includes a fourteenth transistor having a gate or a base connected to the output of the first output stage;
a fifteenth transistor having a gate or a base connected to the output of the second output stage;
a sixteenth transistor connected in series with the fourteenth transistor, the gate or base of the sixteenth transistor being connected to the drain or collector of the fifteenth transistor;
The output signal is output from a connection point between the fourteenth transistor and the sixteenth transistor.
comparator. The comparator according to claim 6,
The output circuit includes a seventeenth transistor connected in series with the fifteenth transistor, and whose gate or base is connected to a connection point between the fourteenth transistor and the sixteenth transistor.
comparator. The comparator according to claim 6,
the threshold voltages of the fourteenth transistor and the fifteenth transistor are lower than the threshold voltages of the third to sixth transistors;
comparator. The comparator according to any one of claims 1 to 8,
at least one of the transistors is comprised of a field effect transistor;
comparator. The comparator according to any one of claims 1 to 8,
at least one of the transistors is comprised of a bipolar transistor;
comparator.

Images