JP2023083889A - comparator - Google Patents

Abstract

To provide a comparator which has improved response characteristics without increasing a circuit current.SOLUTION: If a current flowing in a load resistor R2 is higher than a current flowing in a load resistor R1, then a shunt circuit 4 shunts a current flowing in a transistor M4 and flows a shunted portion of the current to the load resistor R1. Meanwhile, if the current flowing in the load resistor R1 is higher than the current flowing in the load resistor R2, then the shunt circuit shunts a current flowing in a transistor M3 and flows a shunted portion of the current to the load resistor R2.SELECTED DRAWING: Figure 1

Description

The present invention relates to comparators.

Global warming is thought to be caused by the increased concentration of greenhouse gases such as _CO2 , which intensified the greenhouse effect of the atmosphere. Power consumption is also becoming a big issue. A large number of semiconductor integrated circuits are used in electronic equipment, and response speed and current consumption are the main performance characteristics of comparators, which are widely used in semiconductor integrated circuits. Since the response speed and current consumption of a comparator are in inverse proportion to each other, it is intended to improve the response characteristics to an input signal without increasing the current consumption, thereby contributing to the suppression of global warming.

A circuit as shown in FIG. 6 is known as a comparator used in a semiconductor integrated circuit (see, for example, Patent Document 1). A comparator 100 shown in FIG. 6 includes a differential input section 102, a folded cascode section 103, and an output circuit 105 as main components.

The differential input unit 102 includes differential transistors M1 and M2 whose sources are commonly connected, load resistors R1 and R2 respectively connected to their drains, a common source of the transistors M1 and M2, and a positive power supply voltage VDD. and a constant current source 21 connected between them.

The folded cascode unit 103 includes transistors M3 and M4 whose sources are connected to the load resistors R1 and R2, constant current sources 31 and 32 respectively connected between their drains and the positive power supply voltage VDD, and a gate. and a transistor M5 whose drain is connected to the drain of transistor M4 and whose source is connected to the gate of transistor M4. In the folded cascode section 103, the transistor M3 and the transistor M4 are current-mirror-connected, and an output is taken out from the connection node between the drain of the transistor M4 and the constant current source 32. FIG.

Further, the transistor M5 suppresses an increase in the gate potential of the transistor M6, shortens the propagation delay time, and improves the power supply voltage dependency of the propagation delay time (see, for example, Non-Patent Document 1).

The output circuit 105 includes a transistor M6 having a gate connected to the output of the folded cascode section 103 and a source connected to the negative power supply voltage VSS, and a constant current source 51 connected between the drain and the positive power supply voltage VDD. , and is configured to take out the output signal VOUT from the connection node between the transistor M6 and the constant current source 51. FIG.

Japanese Patent No. 4677284

Haruhiko Yoshida, Practical Design of CMOS Analog IC Circuits, CQ Publisher, 2010 (p144, Figure 4.10)

A conventional comparator having the above configuration has a problem that the circuit current must be increased in order to improve the response characteristics.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a comparator with improved response characteristics without increasing the circuit current.

In order to achieve the above object, a comparator according to the present invention is characterized by the following [1] to [9].
[1]
a first differential transistor and a second differential transistor through which currents having a current ratio corresponding to the first input potential and the second input potential flow respectively;
a first load resistor connected in series with the first differential transistor;
a differential input having a second load resistor connected in series with the second differential transistor;
a third transistor folded-cascode-connected to the first differential transistor; and a fourth transistor folded-cascode-connected to the second differential transistor, the third transistor being the third transistor. a folded cascode unit that constitutes one output stage and the fourth transistor constitutes a second output stage;
A comparator comprising an output circuit connected to the outputs of the first output stage and the second output stage and outputting an output signal,
When the current flowing through the second load resistor is larger than the current flowing through the first load resistor, the current flowing through the fourth transistor is shunted to flow through the first load resistor, and a shunt circuit for shunting the current flowing through the third transistor and flowing it through the second load resistor when the current flowing through the first load resistor is larger than the current flowing through the second load resistor; ,
Be a comparator.
[2]
The comparator according to [1],
The shunt circuit is
a fifth transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the gates of the third transistor and the fourth transistor; have
Be a comparator.
[3]
The comparator according to [2],
The shunt circuit is
a sixth transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the gates of the third transistor and the fourth transistor; have
the drain or collector of the fifth transistor and the source or emitter of the sixth transistor are connected to the output of the first output stage;
The output of the second output stage is connected to the source or emitter of the fifth transistor and the drain or collector of the sixth transistor,
Be a comparator.
[4]
The comparator according to any one of [1] to [3],
The folded cascode section has a third resistor connected between the commonly connected gates or bases of the third transistor and the fourth transistor and a power supply voltage.
Be a comparator.
[5]
The comparator according to any one of [1] to [4],
The output circuit is
a seventh transistor having the gate or base connected to the output of the first output stage;
an eighth transistor having the gate or base connected to the output of the second output stage;
a ninth transistor connected in series with the eighth transistor and having a gate or base connected to the drain or collector of the seventh transistor;
outputting the output signal from a connection point between the eighth transistor and the ninth transistor;
Be a comparator.
[6]
The comparator according to [5],
The output circuit is
a tenth transistor connected in series with the seventh transistor and having a gate connected to a connection point between the eighth transistor and the ninth transistor;
Be a comparator.
[7]
The comparator according to [5] or [6],
threshold voltages of the seventh transistor and the eighth transistor are lower than threshold voltages of the third transistor and the fourth transistor;
Be a comparator.
[8]
The comparator according to any one of [1] to [7],
at least one of said transistors is composed of a field effect transistor;
Be a comparator.
[9]
The comparator according to any one of [1] to [8],
at least one of said transistors is composed of a bipolar transistor;
Be a comparator.

According to the present invention, it is possible to provide a comparator with improved response characteristics without increasing circuit current.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following detailed description of the invention (hereinafter referred to as "embodiment") with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing the comparator of the present invention in the first embodiment. FIG. 2 is a circuit diagram showing the comparator of the present invention in the second embodiment. FIG. 3 is a circuit diagram showing the comparator of the present invention in the third embodiment. FIG. 4 is a circuit diagram showing the comparator of the present invention in the fourth embodiment. FIG. 5 is a circuit diagram showing the comparator of the present invention in the fifth embodiment. FIG. 6 is a circuit diagram showing an example of a conventional comparator.

Specific embodiments relating to the present invention will be described below with reference to each drawing.

(First embodiment)
First, the comparator 1 of the first embodiment will be described with reference to FIG. As shown in the figure, the comparator 1 has an inverting input potential INM (=first input potential) input to the inverting input terminal T11 and a non-inverting input potential INP (=second input potential) input to the non-inverting input terminal T12. input potential) and the comparison result is output from the output terminal T3. The comparator 1 includes a differential input section 2 , a folded cascode section 3 , a shunt circuit 4 and an output circuit 5 .

The differential input unit 2 includes a differential transistor M1 (=first differential transistor) and a differential transistor M2 (=second differential transistor) whose sources are commonly connected, and loads connected to their drains. A resistor R1 (=first load resistor), a load resistor R2 (=second load resistor), and a constant current source 21 are provided.

The differential transistors M1 and M2 are composed of P-channel field effect transistors. The gate of the differential transistor M1 is connected to the inverting input terminal T11, and the gate of the differential transistor M2 is connected to the non-inverting input terminal T12. Sources of the differential transistors M1 and M2 are connected in common and connected to the constant current source 21 .

A load resistor R1 is connected in series with the differential transistor M1. Specifically, load resistor R1 is connected between the drain of differential transistor M1 and negative power supply terminal T22. A negative power supply voltage VSS is supplied to the negative power supply terminal T22. A load resistor R2 is connected in series with the differential transistor M2. Specifically, load resistor R2 is connected between the drain of differential transistor M2 and negative power supply terminal T22.

The constant current source 21 is connected between the positive power supply terminal T21 and the sources of the commonly connected differential transistors M1 and M2. A positive power supply voltage VDD is supplied to the positive power supply terminal T21. The differential input unit 2 divides the constant current I1 supplied by the constant current source 21 to the differential transistors M1 and M2. The current ratio (divided current ratio) of the currents flowing through the differential transistors M1 and M2 is a value corresponding to the inverting input potential INM input to the inverting input terminal T11 and the non-inverting input potential INP input to the non-inverting input terminal T12. Become.

The folded cascode unit 3 includes a transistor M3 (=third transistor) folded cascode-connected to the differential transistor M1, and a transistor M4 (=fourth transistor) folded cascode-connected to the differential transistor M2. , resistors R3 and R4, and constant current sources 31 and 32, respectively. The transistors M3 and M4 are composed of N-channel field effect transistors.

A resistor R3 is connected between the gate and the drain of the transistor M3. The transistor M3 has a source connected to a connection point between the load resistor R1 and the drain of the differential transistor M1 and a drain connected to the constant current source 31 . The transistor M4 has a gate connected to the gate of the transistor M3, and a resistor R4 is connected between the gate and the drain. The transistor M4 has a source connected to a connection point between the load resistor R2 and the drain of the differential transistor M2 and a drain connected to the constant current source 32 .

A constant current source 31 is connected between the drain of the transistor M3 and the positive power supply terminal T21. A constant current source 32 is connected between the drain of the transistor M4 and the positive power supply terminal T21.

The folded cascode unit 3 includes a connection node A between the drain of the transistor M3 forming the first output stage and the constant current source 31, and a connection node A between the drain of the transistor M4 forming the second output stage and the constant current source 32. From the connection node B, it is configured to take out the output.

The current dividing circuit 4 is a circuit that divides the current flowing through the transistor M4 and flows it to the load resistor R1 when the current flowing through the load resistor R2 is larger than the current flowing through the load resistor R1. The current dividing circuit 4 divides the current flowing through the transistor M3 and flows it through the load resistor R2 when the current flowing through the load resistor R1 is larger than the current flowing through the load resistor R2.

The current dividing circuit 4 has a transistor M91 (=fifth transistor) and a transistor M92 (=sixth transistor). The transistors M91 and M92 are composed of P-channel field effect transistors. The transistor M91 has a source connected to the connection node B, a drain connected to the connection node A, and a gate connected to the gates of the transistors M3 and M4. The transistor M92 has a source connected to the connection node A, a drain connected to the connection node B, and a gate connected to the gates of the transistors M3 and M4.

The output circuit 5 includes transistors M 5 to M 7 and a constant current source 51 . The transistors M5 and M6 are composed of N-channel field effect transistors. The transistor M5 (=eighth transistor) has a gate connected to the connection node B, a source connected to the negative power supply terminal T22, and a drain connected to the drain of the transistor M7 and the output terminal T3. The transistor M6 (=seventh transistor) has a gate connected to the connection node A, a source connected to the negative power supply terminal T22, and a drain connected to the constant current source 51 .

The transistor M7 (=the ninth transistor) is composed of a P-channel field effect transistor. Transistor M7 is connected in series with transistor M5. More specifically, the transistor M7 has a gate connected to the connection point between the drain of the transistor M6 and the constant current source 51, a source connected to the positive power supply terminal T21, and a drain connected to the drain of the transistor M5 and the output terminal T3. ing. A constant current source 51 is connected between the positive power supply terminal T21 and the drain of the transistor M6.

Next, the operation of the comparator 1 having the configuration described above will be described. First, the operation when the inverting input potential INM is higher than the non-inverting input potential INP and the output signal VOUT of the output terminal T3 is in the Low state, that is, the output signal VOUT is substantially at the negative power supply voltage VSS will be described.

When the inverting input potential INM is higher than the non-inverting input potential INP, more current I1 from the constant current source 21 flows through the differential transistor M2 than through the differential transistor M1. This reduces the voltage drop across load resistor R1 and increases the voltage drop across load resistor R2.

Then, the gate-source potential difference of the transistor M4 becomes smaller than the gate-source potential difference of the transistor M3, the transistor M3 is turned on, and the transistor M4 is turned off. When the transistor M3 is turned on, the potential of the connection node A is lowered. When the potential of the connection node A drops and the gate-source potential difference of the transistor M6 falls below the threshold voltage, the transistor M6 is turned off. On the other hand, when the transistor M4 is turned off, the potential of the connection node B rises. When the potential of the connection node B rises and the gate-source potential difference of the transistor M5 reaches the threshold voltage, the transistor M5 is turned on.

When the transistor M6 is turned off, the drain potential of the transistor M6 rises. When the drain potential of the transistor M6 rises, the gate potential of the transistor M7 rises accordingly, turning off the transistor M7. As a result, the output signal VOUT of the output terminal T3 becomes Low.

Further, when the potential of the connection node A decreases and the potential of the connection node B increases, the transistor M91 is turned on. This causes a portion of the current from constant current source 32 to flow from the source to the drain of transistor M91 and into transistor M3, increasing the current through load resistor R1. Also, some of the current from constant current source 32 flows from the drain to the source due to the reverse operation of transistor M92 and flows into transistor M3, increasing the current through load resistor R1. As a result, the potential of the connection node A becomes higher than when the transistors M91 and M92 are not connected, and can be prevented from dropping to near the negative power supply voltage VSS.

When the output signal VOUT is in the Low state, the transistor M91 clamps the potential of the connection node B to a voltage obtained by adding the gate potential difference of the transistor M91 to the gate potentials of the transistors M3 and M4. As a result, the potential of the connection node B does not rise to near the positive power supply voltage VDD. The gate potentials of the transistors M3 and M4 become an intermediate voltage between the potential of the junction node A and the potential of the junction node B due to the action of the resistors R3 and R4.

Next, the operation when the non-inverted input potential INP is higher than the inverted input potential INM and the output signal VOUT of the output terminal T3 is in a High state, that is, the output signal VOUT is substantially at the positive power supply voltage VDD will be described.

When the non-inverted input potential INP is higher than the inverted input potential INM, more current I1 from the constant current source 21 flows through the differential transistor M1 than through the differential transistor M2. This reduces the voltage drop across load resistor R2 and increases the voltage drop across load resistor R1.

Then, the gate-source potential difference of the transistor M3 becomes smaller than the gate-source potential difference of the transistor M4, the transistor M4 is turned on, and the transistor M3 is turned off. When the transistor M4 is turned on, the potential of the connection node B decreases. When the potential of the connection node B drops and the gate-source potential difference of the transistor M5 falls below the threshold voltage, the transistor M5 is turned off. As described above, when the output signal VOUT is in the Low state, the potential of the connection node B is suppressed from rising by the clamping of the transistor M91, so the time from turning on to turning off the transistor M5 can be shortened. .

Further, when the transistor M3 is turned off, the potential of the connection node A rises. When the potential of the connection node A rises and the gate-source potential difference of the transistor M6 reaches the threshold voltage, the transistor M6 is turned on. As described above, when the output signal VOUT is in the Low state, the gate potential of the transistor M6 is suppressed from being lowered by part of the current from the constant current source 32 flowing into the load resistor R1. can shorten the time from off to on.

When the transistor M6 is turned on, the drain potential of the transistor M6 is lowered. When the drain potential of the transistor M6 drops, the gate potential of the transistor M7 drops accordingly, turning on the transistor M7. As a result, the output signal VOUT of the output terminal T3 becomes High. As described above, it is possible to shorten the time required for the transistor M5 to turn off and the transistor M6 to turn on. can.

As described above, when the potential of the connection node A increases and the potential of the connection node B decreases, the transistor M92 is turned on. This causes a portion of the current from the constant current source 31 to flow from the source to the drain of the transistor M92 and into the transistor M4, increasing the current flowing through the load resistor R2. Also, a portion of the current from constant current source 31 flows from the drain to the source due to the reverse operation of transistor M91 and flows into transistor M4, increasing the current flowing through load resistor R2. As a result, the potential of the connection node B becomes higher than when the transistors M91 and M92 are not provided, and can be prevented from dropping to near the negative power supply voltage VSS.

Further, when the output signal VOUT is in a High state, the transistor M92 clamps the potential of the connection node A to a voltage obtained by adding the gate potential difference of the transistor M92 to the gate potentials of the transistors M3 and M4. As a result, the potential of the connection node A does not rise close to the positive power supply voltage VDD.

As described above, while the output signal VOUT is in the High state, it is possible to suppress the decrease in the gate potential of the transistor M5 and the increase in the gate potential of the transistor M6. Therefore, when the output signal is inverted to the low state, the time required for the transistor M5 to be turned on and the transistor M6 to be turned off can be shortened. can be made faster.

By making the threshold voltages of the transistors M5 and M6 lower than those of the transistors M3 and M4, the time required for the transistors M5 and M6 to change from the off state to the on state can be further shortened. Thereby, the response characteristics of the output circuit 5 can be further improved.

Thus, the comparator 1 in the first embodiment has the effect of improving the response characteristics without increasing the circuit current.

(Second embodiment)
Next, the comparator 1B of the second embodiment will be described with reference to FIG. 2, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1B includes a differential input section 2, a folded cascode section 3, a shunt circuit 4, and an output circuit 5B. The differential input section 2, the folded cascode section 3, and the shunt circuit 4 have already been described in the above-described first embodiment, so detailed description thereof will be omitted here.

The output circuit 5B has transistors M5 to M8. The output circuit 5B of the second embodiment replaces the constant current source 51 of the first embodiment with a transistor M8 (=tenth transistor). The transistor M8 is composed of a P-channel field effect transistor. The transistor M8 has a gate connected to the output terminal T3, a source connected to the positive power supply terminal T21, and a drain connected to the drain of the transistor M6.

A comparator 1B of the second embodiment is basically the same as that of the first embodiment, except for points described later.

That is, in the first embodiment, when the transistor M6 is on, the drain current of the transistor M6 continues to flow as a steady current. In contrast, in the second embodiment, when the transistor M6 is on, the transistor M7 is turned on, and the gate potential of the transistor M8 rises. When the gate potential of the transistor M8 rises, the transistor M8 is turned off, so the drain current does not flow as a steady current when the transistor M6 is on.

Therefore, the comparator 1B in the second embodiment has the effect of reducing current consumption and improving response characteristics.

(Third embodiment)
Next, a comparator 1C of the third embodiment will be described with reference to FIG. In FIG. 3, the same components as those in the circuits shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1C includes a differential input section 2, a folded cascode section 3C, a shunt circuit 4, and an output circuit 5B. Since the differential input section 2 and the shunt circuit 4 have already been described in the above-described first embodiment, detailed description thereof will be omitted here. Since the output circuit 5B has already been described in the above-described second embodiment, detailed description thereof will be omitted here.

A difference between the folded cascode section 3 of the first embodiment and the folded cascode section 3C of the third embodiment is that a resistor R5 (=third resistor) is provided. A resistor R5 is connected between the gates of the transistors M3 and M4 and the negative power supply terminal T22.

A comparator 1C of the third embodiment is basically the same as that of the second embodiment, except for the points described later.

In the first embodiment, changes in the drain potentials of the transistors M3 and M4 propagate as noise to the gates of the transistors M3 and M4 via the gate-drain parasitic capacitances of the transistors M3 and M4. In the third embodiment, by connecting the resistor R5, fluctuations in the gate potentials of the transistors M3 and M4 are suppressed, the circuit operation is stabilized, and the transmission delay time is improved.

Therefore, the comparator 1C of the third embodiment has the effect of improving the response characteristics without increasing the circuit current.

(Fourth embodiment)
Next, a comparator 1D according to the fourth embodiment will be described with reference to FIG. In FIG. 4, the same components as those in the circuits shown in FIGS. 1, 2 and 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1D includes a differential input section 2, a folded cascode section 3C, a shunt circuit 4D, and an output circuit 5B. Since the differential input unit 2 has already been described in the above-described first embodiment, detailed description thereof will be omitted here. The folded cascode section 3C has already been described in the above-described third embodiment, so detailed description thereof will be omitted here. Since the output circuit 5B has already been described in the above-described second embodiment, detailed description thereof will be omitted here.

The difference between the current dividing circuit 4 of the first embodiment and the current dividing circuit 4D of the fourth embodiment is that the current dividing circuit 4D is composed only of the transistor M91 and does not include the transistor M92.

In the fourth embodiment, when the output signal VOUT of the output terminal T3 is in the Low state, part of the current from the constant current source 32 flows from the source to the drain of the transistor M91 and then flows into the drain of the transistor M3. Increase the current through load resistor R1. Also, when the output signal VOUT of the output terminal T3 is in a High state, part of the current from the constant current source 31 flows from the drain to the source of the transistor M91, then flows into the drain of the transistor M4, and flows into the load resistor R2. Increase the current that flows.

Further, the transistor M91 clamps the potential of the connection node A to a voltage obtained by adding the gate potential of the transistors M3 and M4 to the gate-drain potential difference of the transistor M91, and sets the potential of the connection node B to the gate potential of the transistors M3 and M4. By clamping the voltage to which the gate-source potential difference of M91 is added, it is prevented from rising to near the positive power supply voltage VDD.

(Fifth embodiment)
Next, the comparator 1E of the fifth embodiment will be described with reference to FIG. 5, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in the figure, the comparator 1E includes a differential input section 2E, a folded cascode section 3E, a shunt circuit 4E, and an output circuit 5E, as in the first embodiment.

The difference between the first embodiment and the fifth embodiment is that the conductivity types of the transistors M1E to M7E, M91E, and M92E corresponding to the transistors M1 to M7, M91, and M92 are reversed. A difference between the first embodiment and the fifth embodiment is that the relationship between the positive power terminal T21 and the negative power terminal T22 is reversed.

Similarly, in the second to fourth embodiments, the conductivity type of the transistor may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.

It should be noted that the present invention is not limited to the above-described embodiments, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary and not limited as long as the present invention can be achieved.

In the first to fifth embodiments described above, the transistors are field effect transistors, but the present invention is not limited to this. At least one or more of the transistors may be replaced with bipolar transistors. In this case, the gate of the transistor can be read as the base, the source as the emitter, and the drain as the collector.

1, 1B, 1C, 1D, 1E Comparator 2, 2E Differential input section 3, 3C, 3E Folded cascode section 4, 4D, 4E Current dividing circuit 5, 5B, 5E Output circuit A Connection node (first output stage output)
B connection node (output of the second output stage)
INM inverting input potential (first input potential)
INP non-inverting input potential (second input potential)
M1, M1E differential transistors (first differential transistors)
M2, M2E differential transistors (second differential transistors)
M3, M3E transistors (third transistors)
M4, M4E transistors (fourth transistors)
M5, M5E transistors (eighth transistors)
M6, M6E transistors (seventh transistors)
M7, M7E transistors (9th transistors)
M8 transistor (tenth transistor)
M91, M91E transistors (fifth transistors)
M92, M92E transistors (sixth transistors)
R1, R1E load resistor (first load resistor)
R2, R2E load resistor (second load resistor)
R5 load resistor (third resistor)
VOUT output signal

Claims (9)

a first differential transistor and a second differential transistor through which currents having a current ratio corresponding to the first input potential and the second input potential flow respectively;
a first load resistor connected in series with the first differential transistor;
a differential input having a second load resistor connected in series with the second differential transistor;
a third transistor folded-cascode-connected to the first differential transistor; and a fourth transistor folded-cascode-connected to the second differential transistor, the third transistor being the third transistor. a folded cascode unit that constitutes one output stage and the fourth transistor constitutes a second output stage;
A comparator comprising an output circuit connected to the outputs of the first output stage and the second output stage and outputting an output signal,
When the current flowing through the second load resistor is larger than the current flowing through the first load resistor, the current flowing through the fourth transistor is shunted to flow through the first load resistor, and a shunt circuit for shunting the current flowing through the third transistor and flowing it through the second load resistor when the current flowing through the first load resistor is larger than the current flowing through the second load resistor; ,
comparator. A comparator according to claim 1, wherein
The shunt circuit is
a fifth transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the gates of the third transistor and the fourth transistor; have
comparator. A comparator according to claim 2,
The shunt circuit is
a sixth transistor connected between the output of the first output stage and the output of the second output stage, the gate or base of which is connected to the gates of the third transistor and the fourth transistor; have
the drain or collector of the fifth transistor and the source or emitter of the sixth transistor are connected to the output of the first output stage;
The output of the second output stage is connected to the source or emitter of the fifth transistor and the drain or collector of the sixth transistor,
comparator. The comparator according to any one of claims 1 to 3,
The folded cascode section has a third resistor connected between the commonly connected gates or bases of the third transistor and the fourth transistor and a power supply voltage.
comparator. The comparator according to any one of claims 1 to 4,
The output circuit is
a seventh transistor having the gate or base connected to the output of the first output stage;
an eighth transistor having the gate or base connected to the output of the second output stage;
a ninth transistor connected in series with the eighth transistor and having a gate or base connected to the drain or collector of the seventh transistor;
outputting the output signal from a connection point between the eighth transistor and the ninth transistor;
comparator. A comparator according to claim 5,
The output circuit is
a tenth transistor connected in series with the seventh transistor and having a gate connected to a connection point between the eighth transistor and the ninth transistor;
comparator. A comparator according to claim 5 or 6,
threshold voltages of the seventh transistor and the eighth transistor are lower than threshold voltages of the third transistor and the fourth transistor;
comparator. The comparator according to any one of claims 1 to 7,
at least one of said transistors is composed of a field effect transistor;
comparator. The comparator according to any one of claims 1 to 8,
at least one of said transistors is composed of a bipolar transistor;
comparator.

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