JP2023087513A - comparator - Google Patents

Abstract

To provide a comparator with improved response characteristics without increasing a circuit current.SOLUTION: A differential input part 2 has: a constant current source 21 and a constant current source 22; and a differential transistor M1 and a differential transistor M2 which are supplied with currents from the constant current source 21 and the constant current source 22, respectively. An output unit 3 is made up of transistors, and it outputs a result of comparison between the currents flowing to the differential transistor M1 and the differential transistor M2. A current control unit 4 causes the constant current source 22 to supply the currents to the differential transistor M1 and the differential transistor M2 only during a transition period when the output from the output unit 3 is inverted.SELECTED DRAWING: Figure 1

Description

The present invention relates to comparators.

Global warming is thought to be caused by the increased concentration of greenhouse gases such as _CO2 , which intensified the greenhouse effect of the atmosphere. Power consumption is also becoming a big issue. A large number of semiconductor integrated circuits are used in electronic equipment, and response speed and current consumption are the main performance characteristics of comparators, which are widely used in semiconductor integrated circuits. Since the response speed and current consumption of a comparator are in inverse proportion to each other, it is intended to improve the response characteristics to an input signal without increasing the current consumption, thereby contributing to the suppression of global warming.

2. Description of the Related Art As a comparator used in a semiconductor integrated circuit, a circuit as shown in FIG. 4 is known (see Patent Documents 1 and 2, for example). A comparator 100 shown in FIG. 4 is configured with a differential input section 101, an output section 102, and an output buffer circuit 103 as main components.

The differential input section 101 includes differential transistors M1 and M2 whose sources are commonly connected, load transistors M3 and M4 whose drains are respectively connected, and a voltage between the common source of the transistors M1 and M2 and the positive power supply voltage VDD. and a constant current source 21 connected to .

The output section 102 comprises transistors M5 and M6 which are current-mirror-connected to the load transistors M3 and M4, respectively, and transistors M7 and M8 which are respectively connected between the drains of the load transistors M3 and M4 and the positive power supply voltage VDD. The transistors M7 and M8 are current-mirror connected, and an output is taken out through an output buffer circuit 103 from a connection node between the drain of the transistor M6 and the drain of the transistor M8.

The conventional comparator 100 described above has a problem that the circuit current must be increased in order to improve the response characteristics.

Japanese Patent No. 5141289 JP-A-7-245552

SUMMARY OF THE INVENTION It is an object of the present invention to provide a comparator with improved response characteristics without increasing the circuit current.

In order to achieve the above object, a comparator according to the present invention is characterized by the following [1] to [9].
[1]
A first current source and a second current source, and currents from the first current source and the second current source are supplied, and a current ratio corresponding to the first input potential and the second input potential a differential input having a first differential transistor and a second differential transistor through which current respectively flows;
an output unit composed of transistors for outputting a comparison result of currents flowing through the first differential transistor and the second differential transistor;
a current control unit that supplies current from the second current source to the first differential transistor and the second differential transistor only during a transition period in which the output of the output unit is inverted;
Be a comparator.
[2]
In the comparator according to [1],
The output unit has a first output circuit and a second output circuit that output mutually inverted comparison results,
the current control unit includes a third transistor and a fourth transistor connected in series between the second current source and the first differential transistor and the second differential transistor;
the gate or base of the third transistor is connected to the output of the first output circuit;
the gate or base of the fourth transistor is connected to the output of the second output circuit;
Be a comparator.
[3]
In the comparator according to [2],
The first output circuit includes a fifth transistor that folds current flowing through the first differential transistor, and a sixth transistor that folds current flowing through the second differential transistor. of transistors make up the output stage,
The second output circuit has a seventh transistor that folds a current flowing through the first differential transistor, and an eighth transistor that folds a current flowing through the second differential transistor. of transistors make up the output stage,
Be a comparator.
[4]
In the comparator according to [3],
the differential input section includes a ninth load transistor serially connected to the first differential transistor and a tenth load transistor serially connected to the second differential transistor;
the fifth transistor and the seventh transistor are current-mirror connected to the ninth load transistor;
the sixth transistor and the eighth transistor are current-mirror connected to the tenth load transistor;
The first output circuit includes an eleventh transistor serially connected to the fifth transistor, and a twelfth transistor current-mirror-connected to the eleventh transistor for folding back the current flowing through the eleventh transistor. wherein the sixth transistor and the twelfth transistor are connected in series, and the connection point is an output;
The second output circuit includes a thirteenth transistor connected in series with the eighth transistor, and a fourteenth transistor current-mirror-connected to the thirteenth transistor to turn back the current flowing through the thirteenth transistor. wherein the seventh transistor and the fourteenth transistor are connected in series, and the connection point serves as an output;
Be a comparator.
[5]
In the comparator according to [4],
The current control section includes a fifteenth transistor diode-connected between the sixth transistor and the twelfth transistor, and a sixteenth transistor diode-connected between the seventh transistor and the fourteenth transistor. and a transistor of
the gate or base of the third transistor is connected to the gate or base of the fifteenth transistor;
the gate or base of the fourth transistor is connected to the gate or base of the sixteenth transistor;
Be a comparator.
[6]
In the comparator according to any one of [2] to [5],
The comparator includes an output buffer circuit to which the output of the first output circuit and the output of the second output circuit are connected and which outputs an output signal.
[7]
In the comparator according to [6],
The output buffer circuit includes a seventeenth transistor whose gate or base is connected to the output of the first output circuit, and an eighteenth transistor whose gate or base is connected to the output of the second output circuit. wherein the threshold voltages of the seventeenth transistor and the eighteenth transistor are lower than the threshold voltage of at least one of the transistors forming the output section;
Be a comparator.
[8]
In the comparator according to any one of [1] to [7],
At least one or more of the transistors is composed of a field effect transistor,
Be a comparator.
[9]
In the comparator according to any one of [1] to [8],
At least one or more of the transistors are composed of bipolar transistors,
Be a comparator.

According to the present invention, it is possible to provide a comparator with improved response characteristics without increasing circuit current.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following detailed description of the invention (hereinafter referred to as "embodiment") with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing the comparator of the present invention in the first embodiment. FIG. 2 is a circuit diagram showing the comparator of the present invention in the second embodiment. FIG. 3 is a circuit diagram showing the comparator of the present invention in the third embodiment. FIG. 4 is a circuit diagram showing an example of a conventional comparator.

Specific embodiments relating to the present invention will be described below with reference to each drawing.

(First embodiment)
First, the comparator 1 of the first embodiment will be described with reference to FIG. As shown in the figure, the comparator 1 has an inverting input potential (=first input potential) input to the inverting input terminal T11 and a non-inverting input potential (=second input potential) input to the non-inverting input terminal T12. potential), and outputs the comparison result from the output terminal T3. The comparator 1 includes a differential input section 2 , an output section 3 , a current control section 4 and an output buffer circuit 5 .

The differential input unit 2 includes a differential transistor M1 (=first differential transistor), a differential transistor M2 (=second differential transistor), and a load transistor M3 (=ninth differential transistor) whose sources are commonly connected. load transistor), a load transistor M4 (=tenth load transistor), a constant current source 21 (first current source), and a constant current source 22 (=second current source).

The differential transistors M1 and M2 are composed of P-channel field effect transistors. The gate of the differential transistor M1 is connected to the inverting input terminal T11, and the gate of the differential transistor M2 is connected to the non-inverting input terminal T12. Sources of the differential transistors M1 and M2 are connected in common and connected to constant current sources 21 and 22, respectively.

The load transistors M3 and M4 are composed of N-channel field effect transistors. A load transistor M3 is connected in series with the differential transistor M1. Specifically, the load transistor M3 has a drain connected to the drain of the differential transistor M1 and a source connected to the negative power supply terminal T22. A negative power supply voltage VSS is supplied to the negative power supply terminal T22. Load transistor M4 is connected in series with differential transistor M2. More specifically, the load transistor M4 has a drain connected to the drain of the differential transistor M2 and a source connected to the negative power supply terminal T22. The gates and drains of the load transistors M3 and M4 are connected.

The constant current sources 21 and 22 are connected in parallel between the positive power supply terminal T21 and the commonly connected sources of the differential transistors M1 and M2. A positive power supply voltage VDD is supplied to the positive power supply terminal T21. The differential input section 2 divides the current (I1+I2) supplied by the constant current sources 21 and 22 to the differential transistors M1 and M2. A current ratio (divided current ratio) between the currents flowing through the differential transistors M1 and M2 is a value corresponding to the inverting input potential INM and the non-inverting input potential INP.

The output unit 3 outputs a comparison result of currents flowing through the differential transistor M1 and the differential transistor M2. In this embodiment, the output section 3 has an output circuit 31 (=first output circuit) and an output circuit 32 (=second output circuit). The output circuit 31 and the output circuit 32 output mutually inverted comparison results.

Specifically, when the current flowing through the differential transistor M2 is larger than the current flowing through the differential transistor M1, the output circuit 31 outputs a Low state (=negative power supply voltage VSS), and the output circuit 32 outputs a High state (=positive power supply voltage VSS). power supply voltage VDD). On the other hand, when the current flowing through the differential transistor M1 is larger than the current flowing through the differential transistor M2, the output circuit 31 outputs a High state and the output circuit 32 outputs a Low state.

First, the output circuit 31 will be described. The output circuit 31 has a transistor M51, a transistor M61, a transistor M71, and a transistor M81. The transistors M51 and M61 are composed of N-channel field effect transistors. The transistor M51 has a gate connected to the gate and drain of the load transistor M3, and a source connected to the negative power supply terminal T22. That is, the transistor M51 is current-mirror-connected to the load transistor M3, and copies and returns the current flowing through the load transistor M3. The transistor M61 has a gate connected to the gate and drain of the load transistor M4, and a source connected to the negative power supply terminal T22. That is, the transistor M61 is current-mirror-connected to the load transistor M4, and copies and loops back the current flowing through the load transistor M4.

The transistors M71 and M81 are composed of P-channel field effect transistors. The sources of the transistors M71 and M81 are connected in common and connected to the positive power supply terminal T21. The drain of the transistor M71 is connected to the drain of the transistor M51, and the transistors M71 and M51 are connected in series. The gate of the transistor M81 is connected to the gate and drain of the transistor M71. That is, the transistor M81 is current-mirror-connected to the transistor M71, and copies and loops back the current flowing through the transistor M71.

The drain of the transistor M81 is connected to the drain of the transistor M61, and the transistors M81 and M61 are connected in series to form an output stage. A connection node A between the transistor M61 and the transistor M81 is the output of the output circuit 31 .

Next, the output circuit 32 will be explained. The output circuit 32 has a transistor M52, a transistor M62, a transistor M72 and a transistor M82. The transistors M52 and M62 are composed of N-channel field effect transistors. The transistor M52 has a gate connected to the gate and drain of the load transistor M3, and a source connected to the negative power supply terminal T22. That is, the transistor M52 is current-mirror-connected to the load transistor M3, and copies and loops back the current flowing through the load transistor M3. The transistor M62 has a gate connected to the gate and drain of the load transistor M4, and a source connected to the negative power supply terminal T22. That is, the transistor M62 is current-mirror-connected to the load transistor M4, and copies and folds the current flowing through the load transistor M4.

The transistors M72 and M82 are composed of P-channel field effect transistors. The sources of the transistors M72 and M82 are connected in common and connected to the positive power supply terminal T21. The drain of the transistor M82 is connected to the drain of the transistor M62, and the transistors M82 and M62 are connected in series. The gate of the transistor M72 is connected to the gate and drain of the transistor M82. That is, the transistor M72 is current-mirror-connected to the transistor M82, and copies and folds back the current flowing through the transistor M82.

The drain of the transistor M72 is connected to the drain of the transistor M52, and the transistors M72 and M52 are connected in series. A connection node B between the transistor M72 and the transistor M52 is the output of the output circuit 32. FIG.

The current control unit 4 supplies current from the constant current source 22 to the differential transistors M1 and M2 only during the transition period in which the outputs of the output circuits 31 and 32 are inverted. The current control unit 4 has transistors M91 and M92. The transistors M91 and M92 are composed of P-channel field effect transistors. Transistors M91 and M92 are connected in series between constant current source 22 and the sources of differential transistors M1 and M2. The transistor M91 has a source connected to the constant current source 22, a drain connected to the source of the transistor M92, and a gate connected to the connection node A. The transistor M92 has a source connected to the drain of the transistor M91, a drain connected to the sources of the differential transistors M1 and M2, and a gate connected to the connection node B.

The output buffer circuit 5 is connected to the connection nodes A and B and outputs an output signal VOUT. The output buffer circuit 5 has transistors M 11 to M 16 and an inverter circuit 51 . The transistors M11 and M12 are composed of N-channel field effect transistors. The transistor M11 has a gate connected to the connection node A and a source connected to the negative power supply terminal T22. The transistor M12 has a gate connected to the connection node B and a source connected to the negative power supply terminal T22.

The transistors M13 to M16 are composed of P-channel field effect transistors. The transistor M13 has a source connected to the positive power supply terminal T21, a drain connected to the source of the transistor M15 described later, and a gate connected to the drain of the transistor M12. The transistor M14 has a source connected to the positive power supply terminal T21, a drain connected to the source of the transistor M16 described later, and a gate connected to the drain of the transistor M11.

The transistor M15 has a source connected to the drain of the transistor M13 and a gate and drain connected to the drain of the transistor M11. The transistor M16 has a source connected to the drain of the transistor M14 and a gate and drain connected to the drain of the transistor M12.

The inverter circuit 51 has an input connected to a connection node between the drain of the transistor M15 and the drain of the transistor M11, and an output connected to the output terminal T3.

Next, the operation of the comparator 1 having the configuration described above will be described. First, the operation will be described when the inverting input potential INM is higher than the non-inverting input potential INP and the output of the output terminal T3 is in a low state, that is, the output signal is approximately the negative power supply voltage VSS.

When the inverting input potential INM is higher than the non-inverting input potential INP, more current flows from the constant current source 21 to the differential transistor M2 than to the differential transistor M1, and the load transistor M4 flows more than the load transistor M3. more current flows in the direction of Therefore, more current flows through the transistors M61 and M62 that are current-mirror-connected to the load transistor M4 than to the transistors M51 and M52 that are current-mirror-connected to the load transistor M3.

A small current flowing through transistor M51 flows through transistor M71 and is copied to the drain current of transistor M81. Since the transistor M81 operates to allow a small current to flow and the transistor M61 operates to allow a large current to flow, the connection node A is in the Low state. When the connection node A goes low, the transistor M11 is turned off. When the transistor M11 turns off, the drain potential of the transistor M11 rises, so the transistor M14 turns off.

Also, the large current flowing through the transistor M62 flows through the transistor M82 and is copied to the drain current of the transistor M72. Since the transistor M72 operates to allow a large current to flow and the transistor M52 operates to allow a small current to flow, the connection node B becomes High. When the connection node B becomes High, the transistor M12 is turned on. When the transistor M12 is turned on, the drain potential of the transistor M12 is lowered, so that the transistor M13 is turned on.

As described above, when the transistor M11 is turned off and the transistor M13 is turned on, a High potential is input to the inverter circuit 51, and a Low output signal VOUT is output from the output terminal T3.

When the output signal VOUT is in the Low state, the connection node A is in the Low state and the connection node B is in the High state as described above, so the transistor M91 is turned on and the transistor M92 is turned off.

Next, the operation when the non-inverted input potential INP is higher than the inverted input potential INM and the output of the output terminal T3 is in a High state, that is, the output signal VOUT is substantially at the positive power supply voltage VDD will be described.

When the non-inverting input potential INP is higher than the inverting input potential INM, more current flows from the constant current source 21 to the differential transistor M1 than to the differential transistor M2, and the load transistor M3 flows more than the load transistor M4. more current flows in the direction of Therefore, more current flows through the transistors M51 and M52 that are current-mirror-connected to the load transistor M3 than to the transistors M61 and M62 that are current-mirror-connected to the load transistor M4.

The large current flowing through transistor M51 flows through transistor M71 and is copied to the drain current of transistor M81. Since the transistor M81 operates to allow a large current to flow and the transistor M61 operates to allow a small current to flow, the connection node A becomes High. When the connection node A becomes High, the transistor M11 is turned on. When the transistor M11 is turned on, the drain potential of the transistor M11 is lowered, so that the transistor M14 is turned on.

Also, the small current flowing through the transistor M62 flows through the transistor M82 and is copied to the drain current of the transistor M72. Since the transistor M72 operates to allow a small current to flow and the transistor M52 operates to allow a large current to flow, the connection node B is in the Low state. When the connection node B goes low, the transistor M12 is turned off. When the transistor M12 is turned off, the drain potential of the transistor M12 is increased, so that the transistor M13 is turned off.

As described above, when the transistor M11 is turned on and the transistor M13 is turned off, a low state potential is input to the inverter circuit 51, and a high state output signal VOUT is output from the output terminal T3.

When the output signal VOUT is in the High state, the connection node A is in the High state and the connection node B is in the Low state as described above, so the transistor M91 is turned off and the transistor M92 is turned on.

Next, the operation when the output signal VOUT of the output terminal T3 changes from the Low state to the High state is as follows.

At this time, the potential of the connection node A changes from Low to High, and the transistor M91 changes from ON to OFF. On the other hand, the connection node B changes from High to Low, and the transistor M92 changes from off to on.

As a result, during the period in which the potentials of the connection node A and the connection node B change, there is a period in which the transistor M91 and the transistor M92 are turned on at the same time. During that period, in addition to the current supplied from the constant current source 21, the current supplied from the constant current source 22 flows through the transistors M91 and M92 as tail currents of the differential transistors M1 and M2.

Next, the operation when the output signal VOUT of the output terminal T3 changes from the High state to the Low state is as follows.

At this time, the potential of the connection node A changes from High to Low, and the transistor M91 changes from off to on. On the other hand, the connection node B changes from Low to High, and the transistor M92 changes from ON to OFF.

As a result, during the period in which the potentials of the connection node A and the connection node B change, there is a period in which the transistor M91 and the transistor M92 are turned on at the same time. During that period, in addition to the current supplied from the constant current source 21, the current supplied from the constant current source 22 flows through the transistors M91 and M92 as tail currents of the differential transistors M1 and M2.

In the first embodiment described above, the tail current is temporarily increased to the current (I1+I2) during the transition period in which the outputs of the output circuits 31 and 32 are inverted, and the tail current is increased after the outputs of the output circuits 31 and 32 are inverted. The current is returned to I1. As a result, it is possible to obtain the effect of improving the response characteristics when the output signal VOUT changes without increasing the current consumption.

Further, in the above-described first embodiment, the output circuits 31 and 32 are provided, and the gates of the transistors M11 and M12 constituting the output buffer circuit 5 are controlled by differential output signals generated between the connection nodes A and B. As a result, the response characteristics of the output signal VOUT from the output terminal T3 are also improved.

By lowering the threshold voltage of at least one of the transistors M51, M61, M52, and M62 constituting the output circuits 31 and 32, the transistors M11 and M12 change from the off state to the on state. The time required for the output buffer circuit 5 is shortened, and the response characteristic of the output buffer circuit 5 is further improved.

(Second embodiment)
Next, the comparator 1B of the second embodiment will be described with reference to FIG. 2, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in the figure, the comparator 1B includes a differential input section 2, an output section 3 having output circuits 31 and 32, a current control section 4B, and an output buffer circuit 5, as in the first embodiment. I have it. Since the differential input section 2, the output circuits 31 and 32, and the output buffer circuit 5 are the same as those of the above-described first embodiment, detailed description thereof will be omitted here.

The difference between the first embodiment and the second embodiment is that the current control section 4B has transistors M101 and M102 in addition to the transistors M91 and M92.

The transistors M101 and M102 are composed of P-channel field effect transistors. The transistor M101 has a source connected to the drain of the transistor M81, and a gate and a drain connected to the drain of the transistor M61 and the gate of the transistor M91. The transistor M102 has a source connected to the drain of the transistor M72, and a gate and a drain connected to the drain of the transistor M52 and the gate of the transistor M92.

Next, the operation of the comparator 1B having the configuration described above will be described. A comparator 1B having such a configuration is basically the same as that of the first embodiment, except for points described later.

That is, in the first embodiment, the gate potentials of the transistors M91 and M92 in the OFF state are near the positive power supply voltage VDD. The gate potential in the off state becomes low. As a result, the timing delay at which the transistors M91 and M92 change from the off state to the on state is shortened.

Therefore, the comparator 1B in the second embodiment has the effect of further improving the response characteristics without increasing the current consumption.

(Third embodiment)
Next, a comparator 1C of the third embodiment will be described with reference to FIG. 3, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in the figure, the comparator 1C includes a differential input section 2C, output circuits 31C and 32C, a current control section 4C, and an output buffer circuit 5C, as in the first embodiment.

The difference between the first embodiment and the third embodiment is that the transistors M1C to M4C corresponding to the transistors M1 to M4, M51, M52, M61, M62, M71, M72, M81, M82, M91, M92, M11 to M16 , M51C, M52C, M61C, M62C, M71C, M72C, M81C, M82C, M91C, M92C, M11C to M16C are reversed. A difference between the first embodiment and the third embodiment is that the relationship between the positive power terminal T21 and the negative power terminal T22 is reversed.

In the third embodiment, similarly to the first embodiment, it is possible to obtain the effect of further improving the response characteristics without increasing current consumption.

It should be noted that the present invention is not limited to the above-described embodiments, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary and not limited as long as the present invention can be achieved.

For example, in the first to third embodiments described above, the transistors M1(C) to M4(C), M51(C), M52(C), M61(C), M62(C), M71(C), M72 (C), M81(C), M82(C), M91(C), M92(C), M101, M102, M11(C) to M16(C) consisted of field effect transistors. is not limited to Transistors M1(C)-M4(C), M51(C), M52(C), M61(C), M62(C), M71(C), M72(C), M81(C), M82(C) , M91(C), M92(C), M101, M102, M11(C) to M16(C) may be composed of bipolar transistors. In this case, description can be made by replacing the gate of the transistor with the base, the source with the emitter, and the drain with the collector.

In addition, in the first to third embodiments described above, two transistors M51(C) and M52(C) are connected to the gate of one load transistor M3(C), but this is not the only option. . Two load transistors M3(C) may be provided and transistors M51(C) and M52(C) may be connected respectively. Similarly, two load transistors M4(C) may be provided and connected to transistors M61(C) and M62(C), respectively.

In the first to third embodiments described above, the output circuits 31(C) and 32(C) include transistors M51(C) and M51(C) which are current-mirror connected to the load transistors M3(C) and M4(C). Although it is composed of M52(C), M61(C), and M62(C), it is not limited to this. The output circuits 31(C) and 32(C) may output the comparison result of the differential transistors M1(C) and M2(C) and output the mutually inverted outputs. For example, the output circuits 31(C) and 32(C) may be composed of transistors that are folded cascode-connected to the differential transistors M1(C) and M2(C).

1, 1B, 1C comparator 2, 2C differential input section 3, 3C output section 4, 4B, 4C current control section 5, 5C output buffer circuit 21, 21C constant current source (first current source)
22, 22C constant current source (second current source)
31, 31C output circuit (first output circuit)
32, 32C output circuit (second output circuit)
INM inverting input potential (first input potential)
INP non-inverting input potential (second input potential)
M1, M1C differential transistor (first differential transistor)
M2, M2C differential transistors (second differential transistors)
M3, M3C load transistors (ninth load transistors)
M4, M4C load transistor (tenth load transistor)
M11, M11C transistors (17th transistors)
M12, M12C transistor (18th transistor)
M51, M51C transistors (fifth transistors)
M52, M52C transistors (seventh transistors)
M61, M61C transistors (sixth transistors)
M62, M62C transistor (eighth transistor)
M71, 71C transistor (eleventh transistor)
M72, M72C transistor (14th transistor)
M81, M81C transistors (12th transistors)
M82, M82C transistor (13th transistor)
M91, M91C transistors (third transistors)
M92, M92C transistor (fourth transistor)
M101 transistor (15th transistor)
M102 transistor (16th transistor)
VOUT output signal

Claims (9)

A first current source and a second current source, and currents from the first current source and the second current source are supplied, and a current ratio corresponding to the first input potential and the second input potential a differential input having a first differential transistor and a second differential transistor through which current respectively flows;
an output unit composed of transistors for outputting a comparison result of currents flowing through the first differential transistor and the second differential transistor;
a current control unit that supplies current from the second current source to the first differential transistor and the second differential transistor only during a transition period in which the output of the output unit is inverted;
comparator. The comparator of claim 1, wherein
The output unit has a first output circuit and a second output circuit that output mutually inverted comparison results,
the current control unit includes a third transistor and a fourth transistor connected in series between the second current source and the first differential transistor and the second differential transistor;
the gate or base of the third transistor is connected to the output of the first output circuit;
the gate or base of the fourth transistor is connected to the output of the second output circuit;
comparator. A comparator according to claim 2, wherein
The first output circuit includes a fifth transistor that folds current flowing through the first differential transistor, and a sixth transistor that folds current flowing through the second differential transistor. of transistors make up the output stage,
The second output circuit has a seventh transistor that folds a current flowing through the first differential transistor, and an eighth transistor that folds a current flowing through the second differential transistor. of transistors make up the output stage,
comparator. A comparator according to claim 3, wherein
the differential input section includes a ninth load transistor serially connected to the first differential transistor and a tenth load transistor serially connected to the second differential transistor;
the fifth transistor and the seventh transistor are current-mirror connected to the ninth load transistor;
the sixth transistor and the eighth transistor are current-mirror connected to the tenth load transistor;
The first output circuit includes an eleventh transistor serially connected to the fifth transistor, and a twelfth transistor current-mirror-connected to the eleventh transistor for folding back the current flowing through the eleventh transistor. wherein the sixth transistor and the twelfth transistor are connected in series, and the connection point is an output;
The second output circuit includes a thirteenth transistor connected in series with the eighth transistor, and a fourteenth transistor current-mirror-connected to the thirteenth transistor to turn back the current flowing through the thirteenth transistor. wherein the seventh transistor and the fourteenth transistor are connected in series, and the connection point serves as an output;
comparator. A comparator according to claim 4, wherein
The current control section includes a fifteenth transistor diode-connected between the sixth transistor and the twelfth transistor, and a sixteenth transistor diode-connected between the seventh transistor and the fourteenth transistor. and a transistor of
the gate or base of the third transistor is connected to the gate or base of the fifteenth transistor;
the gate or base of the fourth transistor is connected to the gate or base of the sixteenth transistor;
comparator. In the comparator according to any one of claims 2 to 5,
A comparator comprising an output buffer circuit to which the output of the first output circuit and the output of the second output circuit are connected and which outputs an output signal. A comparator according to claim 6, wherein
The output buffer circuit includes a seventeenth transistor whose gate or base is connected to the output of the first output circuit, and an eighteenth transistor whose gate or base is connected to the output of the second output circuit. wherein the threshold voltages of the seventeenth transistor and the eighteenth transistor are lower than the threshold voltage of at least one of the transistors forming the output section;
comparator. In the comparator according to any one of claims 1 to 7,
At least one or more of the transistors is composed of a field effect transistor,
comparator. In the comparator according to any one of claims 1 to 8,
At least one or more of the transistors are composed of bipolar transistors,
comparator.

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