JP2023083888A - comparator - Google Patents

Abstract

To provide a comparator which has improved response characteristics without increasing a circuit current.SOLUTION: A transistor M3 is connected to a differential transistor M1 in the manner of a folded-cascode connection. A transistor M4 is connected to a differential transistor M2 in the manner of a folded-cascode connection. When the transistor M4 is in its on-state, a transistor M7 controls reduction in a drain potential of the transistor M4.SELECTED DRAWING: Figure 1

Description

The present invention relates to comparators.

Global warming is thought to be caused by the increased concentration of greenhouse gases such as _CO2 , which intensified the greenhouse effect of the atmosphere. Power consumption is also becoming a big issue. A large number of semiconductor integrated circuits are used in electronic equipment, and response speed and current consumption are the main performance characteristics of comparators, which are widely used in semiconductor integrated circuits. Since the response speed and current consumption of a comparator are in inverse proportion to each other, it is intended to improve the response characteristics to an input signal without increasing the current consumption, thereby contributing to the suppression of global warming.

2. Description of the Related Art As a comparator used in a semiconductor integrated circuit, a circuit as shown in FIG. 4 is known (see, for example, Patent Document 1). The comparator 100 shown in FIG. 4 is configured with a differential input section 102, a folded cascode section 103, and an output circuit 104 as main components.

The differential input unit 102 includes differential transistors M1 and M2 whose sources are commonly connected, load resistors R1 and R2 respectively connected to their drains, a common source of the transistors M1 and M2, and a positive power supply voltage VDD. and a constant current source 21 connected between them.

The folded cascode unit 103 includes transistors M3 and M4 whose sources are connected to the load resistors R1 and R2, constant current sources 31 and 32 respectively connected between their drains and the positive power supply voltage VDD, and a gate. and a transistor M5 whose drain is connected to the drain of transistor M4 and whose source is connected to the gate of transistor M4. In the folded cascode section 103, the transistor M3 and the transistor M4 are current-mirror-connected, and an output is taken out from the connection node between the drain of the transistor M4 and the constant current source 32. FIG.

Further, the transistor M5 is turned on when the current flowing through the transistor M2 is larger than the current flowing through the transistor M1, suppressing the increase in the gate potential of the transistor M6, shortening the propagation delay time, and reducing the propagation delay time. The power supply voltage dependency is improved (see, for example, Non-Patent Document 1).

The output circuit 104 includes a transistor M6 having a gate connected to the output of the folded cascode section 103 and a source connected to the negative power supply voltage VSS, and a constant current source 41 connected between the drain and the positive power supply voltage VDD. , and is configured to take out the output signal VOUT from the connection node between the transistor M6 and the constant current source 41. FIG.

Japanese Patent No. 4677284

Haruhiko Yoshida, Practical Design of CMOS Analog IC Circuits, CQ Publisher, 2010 (p144, Figure 4.10)

A conventional comparator having the above configuration has a problem that the circuit current must be increased in order to improve the response characteristics.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a comparator with improved response characteristics without increasing the circuit current.

In order to achieve the above object, a comparator according to the present invention is characterized by the following [1] to [6].
[1]
a differential input unit having a first differential transistor and a second differential transistor through which currents having a current ratio corresponding to the first input potential and the second input potential flow respectively;
a folded cascode unit having a third transistor folded cascode connected to the first differential transistor and a fourth transistor folded cascode connected to the second differential transistor;
and an output circuit connected to the drain or collector of the fourth transistor and outputting an output signal,
The folded cascode section is a comparator having a voltage clamping element that limits an increase or decrease in drain potential or collector potential of the fourth transistor when the fourth transistor is in an ON state.
[2]
The comparator according to [1],
The voltage clamp element clamps the drain potential or collector potential of the fourth transistor to a voltage corresponding to the drain potential or collector potential of the third transistor.
Be a comparator.
[3]
The comparator according to [2],
The voltage clamping element comprises a fifth transistor diode-connected between the drain or collector of the third transistor and the drain or collector of the fourth transistor.
Be a comparator.
[4]
The comparator according to [3],
The folded cascode unit has a resistor connected between the gate and drain or between the base and collector of the fifth transistor,
Be a comparator.
[5]
The comparator according to any one of [1] to [4],
the output circuit has a sixth transistor having a gate or base connected to the drain or collector of the fourth transistor;
the threshold voltage of the sixth transistor is lower than the threshold voltages of the third transistor and the fourth transistor;
Be a comparator.
[6]
The comparator according to any one of [1] to [5],
at least one of said transistors is composed of a field effect transistor;
Be a comparator.
[7]
The comparator according to any one of [1] to [6],
at least one of said transistors is composed of a bipolar transistor;
Be a comparator.

According to the present invention, it is possible to provide a comparator with improved response characteristics without increasing circuit current.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following detailed description of the invention (hereinafter referred to as "embodiment") with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing the comparator of the present invention in the first embodiment. FIG. 2 is a circuit diagram showing the comparator of the present invention in the second embodiment. FIG. 3 is a circuit diagram showing the comparator of the present invention in the third embodiment. FIG. 4 is a circuit diagram showing an example of a conventional comparator.

Specific embodiments relating to the present invention will be described below with reference to each drawing.

(First embodiment)
First, the comparator 1 of the first embodiment will be described with reference to FIG. As shown in the figure, the comparator 1 has an inverting input potential INM (=first input potential) input to the inverting input terminal T11 and a non-inverting input potential INP (=second input potential) input to the non-inverting input terminal T12. input potential) and the comparison result is output from the output terminal T3. The comparator 1 has a differential input section 2 , a folded cascode section 3 and an output circuit 4 .

The differential input unit 2 includes a differential transistor M1 (=first differential transistor) and a differential transistor M2 (=second differential transistor) whose sources are commonly connected, and loads connected to their drains. A resistor R1, a load resistor R2, and a constant current source 21 are provided.

The differential transistors M1 and M2 are composed of P-channel field effect transistors. The gate of the differential transistor M1 is connected to the inverting input terminal T11, and the gate of the differential transistor M2 is connected to the non-inverting input terminal T12. Sources of the differential transistors M1 and M2 are connected in common and connected to the constant current source 21 .

A load resistor R1 is connected in series with the differential transistor M1. Specifically, load resistor R1 is connected between the drain of differential transistor M1 and negative power supply terminal T22. A negative power supply voltage VSS is supplied to the negative power supply terminal T22. A load resistor R2 is connected in series with the differential transistor M2. Specifically, load resistor R2 is connected between the drain of differential transistor M2 and negative power supply terminal T22.

The constant current source 21 is connected between the positive power supply terminal T21 and the sources of the commonly connected differential transistors M1 and M2. A positive power supply voltage VDD is supplied to the positive power supply terminal T21. The differential input unit 2 divides the constant current I1 supplied by the constant current source 21 to the differential transistors M1 and M2. The current ratio (divided current ratio) of the currents flowing through the differential transistors M1 and M2 is a value corresponding to the inverting input potential INM input to the inverting input terminal T11 and the non-inverting input potential INP input to the non-inverting input terminal T12. Become.

The folded cascode unit 3 includes a transistor M3 (=third transistor) that is folded cascode-connected to the differential transistor M1, and a transistor M4 (=fourth transistor) that is folded cascode-connected to the differential transistor M2. , and constant current sources 31 and 32 for clamping the drain potential of the transistor M4. The transistors M3 to M5 and M7 are composed of N-channel field effect transistors.

The gate and drain of the transistor M3 are connected. The transistor M3 has a source connected to a connection point between the load resistor R1 and the drain of the differential transistor M1 and a drain connected to the constant current source 31 . The transistor M4 has a gate connected to the gate/drain of the transistor M3. The transistor M4 has a source connected to a connection point between the load resistor R2 and the drain of the differential transistor M2 and a drain connected to the constant current source 32 .

A constant current source 31 is connected between the drain of the transistor M3 and the positive power supply terminal T21. A constant current source 32 is connected between the drain of the transistor M4 and the positive power supply terminal T21.

The transistor M5 has its gate and drain connected to the connection node A between the drain of the transistor M4 and the constant current source 32, and its source connected to the gate and drain of the transistor M3 and the gate of the transistor M4. The transistor M7 (=fifth transistor, voltage clamping element) has its gate and drain connected to the connection node between the drain of the transistor M3 and the constant current source 31, and its source connected to the connection node A. That is, the transistor M7 is diode-connected between the drain of the transistor M3 and the drain of the transistor M4.

The folded cascode section 3 is configured to extract an output from a connection node A between the drain of the transistor M4 and the constant current source 32. FIG.

The output circuit 4 includes a transistor M6 (=sixth transistor) and a constant current source 41 . The transistor M6 is composed of an N-channel field effect transistor. The transistor M 6 has a gate connected to the connection node A, a source connected to the negative power supply terminal T 22 , and a drain connected to the constant current source 41 . A constant current source 41 is connected between the drain of the transistor M6 and the positive power supply terminal T21.

Next, the operation of the comparator 1 having the configuration described above will be described. First, the operation when the inverting input potential INM is higher than the non-inverting input potential INP and the output signal VOUT of the output terminal T3 is in the Low state, that is, the output signal VOUT is substantially at the negative power supply voltage VSS will be described.

When the inverting input potential INM is higher than the non-inverting input potential INP, more current I1 from the constant current source 21 flows through the differential transistor M2 than through the differential transistor M1. This reduces the voltage drop across load resistor R1 and increases the voltage drop across load resistor R2.

Then, the gate-source potential difference of the transistor M4 becomes smaller than the gate-source potential difference of the transistor M3, and the transistor M4 is turned off. When the transistor M4 is turned off, the potential of the connection node A rises. When the potential of the connection node A rises and the gate-source potential difference of the transistor M6 reaches the threshold voltage, the transistor M6 is turned on. As a result, the output signal VOUT of the output terminal T3 becomes Low.

Further, when the potential of the junction node A rises and the gate-source potential difference of the transistor M5 reaches the threshold voltage, the transistor M5 is turned on. Therefore, the potential of the connection node A is clamped by the sum of the drain potential (=gate potential) of the transistor M3 and the gate-source potential of the transistor M5, and does not rise to near the positive power supply voltage VDD.

Next, the operation when the non-inverted input potential INP is higher than the inverted input potential INM and the output signal VOUT of the output terminal T3 is in a High state, that is, the output signal VOUT is substantially at the positive power supply voltage VDD will be described.

When the non-inverted input potential INP is higher than the inverted input potential INM, more current I1 from the constant current source 21 flows through the differential transistor M1 than through the differential transistor M2. This reduces the voltage drop across load resistor R2 and increases the voltage drop across load resistor R1.

Then, the gate-source potential difference of the transistor M4 becomes larger than the gate-source potential difference of the transistor M3, and the transistor M4 is turned on. When the transistor M4 is turned on, the potential of the connection node A is lowered. When the potential of the connection node A drops and the gate-source potential difference of the transistor M6 falls below the threshold voltage, the transistor M6 is turned off. As a result, the output signal VOUT of the output terminal T3 becomes High.

Further, when the potential of the connection node A drops and the gate-source potential difference of the transistor M7 reaches the threshold voltage, the transistor M7 is turned on. Therefore, the potential of the connection node A is clamped by the voltage obtained by subtracting the gate-source potential of the transistor M7 from the drain potential (=gate potential) of the transistor M3, and does not drop to near the negative power supply voltage VSS.

As described above, when the output signal VOUT is in the Low state and the transistor M4 is in the OFF state, the transistor M5 works to suppress the increase in the gate potential of the transistor M6. As a result, the time required for the transistor M6 to turn off can be shortened, so that the response speed of the output signal VOUT can be increased from the low state to the high state.

Further, as described above, when the output signal VOUT is in the High state and the transistor M4 is in the ON state, the transistor M7 works to suppress the decrease in the gate potential of the transistor M6. Therefore, the time required for the transistor M6 to turn on can be shortened, and the response speed until the output signal VOUT is inverted from the high state to the low state can be increased.

By setting the threshold voltage of the transistor M6 to be lower than the threshold voltages of the transistors M3 and M4, the time required for the transistor M6 to change from the off state to the on state can be further shortened. Thereby, the response characteristics of the output circuit 4 can be further improved.

Thus, the comparator 1 in the first embodiment has the effect of improving the response characteristics without increasing the circuit current.

(Second embodiment)
Next, the comparator 1B of the second embodiment will be described with reference to FIG. 2, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The comparator 1B has a differential input section 2, a folded cascode section 3B, and an output circuit 4. FIG. Since the differential input section 2 and the output circuit 4 have already been described in the first embodiment, detailed description thereof will be omitted here.

The difference between the folded cascode section 3B of the second embodiment and the folded cascode section 3 of the first embodiment is that a resistor R3 is provided between the drain and gate of the transistor M7.

A comparator 1B of the second embodiment is basically the same as that of the first embodiment, except for points described later.

That is, in the first embodiment, the potential of the connection node A at which the transistor M4 is on is clamped by the gate-source potential of the transistor M7. On the other hand, in the second embodiment, in addition to the potential between the gate and source of the transistor M7, the current of the constant current source 31 and the voltage drop due to the resistor R3 are added.

Therefore, the potential of the connection node A when the transistor M4 is on becomes higher than when the resistor R3 is not connected, and the time required for the transistor M6 to change from off to on is shortened. , the propagation delay time in which the output signal VOUT of the output terminal T3 changes from the High state to the Low state is further shortened as compared with the first embodiment.

Thus, the comparator 1B in the second embodiment has the effect of improving the response characteristics without increasing the circuit current.

(Third embodiment)
Next, a comparator 1C of the third embodiment will be described with reference to FIG. 3, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in the figure, the comparator 1C includes a differential input section 2C, a folded cascode section 3C, and an output circuit 4C, as in the first embodiment.

The difference between the first embodiment and the third embodiment is that the conductivity types of the transistors M1C to M7C corresponding to the transistors M1 to M7 are reversed. A difference between the first embodiment and the third embodiment is that the relationship between the positive power terminal T21 and the negative power terminal T22 is reversed.

In the third embodiment, when the output signal VOUT is High, the transistor M4C is turned off. When the gate-source potential difference of the transistor M4C becomes smaller than the gate-source potential difference of the transistor M3C and the transistor M4C is turned off, the potential of the junction node A decreases. When the potential of the junction node A drops and the gate-source potential difference of the transistor M5C reaches the threshold voltage, the transistor M5C is turned on. Therefore, the potential of the connection node A is clamped by the voltage obtained by subtracting the gate-source potential of the transistor M5C from the drain potential (=gate potential) of the transistor M3C, and does not drop to near the negative power supply voltage VSS.

As a result, it is possible to shorten the time from turning on to turning off the transistor M6C, so that it is possible to speed up the response speed until the output signal VOUT is inverted from the High state to the Low state.

On the other hand, when the output signal VOUT is in the Low state, the transistor M4C is turned on. When the gate-source potential difference of the transistor M4C becomes larger than the gate-source potential difference of the transistor M3C and the transistor M4C is turned on, the potential of the junction node A rises. When the potential of the junction node A rises and the gate-source potential difference of the transistor M7C reaches the threshold voltage, the transistor M7C is turned on. Therefore, the potential of the connection node A is clamped by the sum of the drain potential (=gate potential) of the transistor M3C and the gate-source potential of the transistor M7C, and does not rise to near the positive power supply voltage VDD.

As a result, the time from off to on of the transistor M6C can be shortened, so that the response speed until the output signal VOUT is inverted from the Low state to the High state can be increased.

Similarly, in the second embodiment, the conductivity type of the transistor may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.

It should be noted that the present invention is not limited to the above-described embodiments, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary and not limited as long as the present invention can be achieved.

In the first to third embodiments described above, the transistors are field effect transistors, but the present invention is not limited to this. At least one or more of the transistors may be replaced with bipolar transistors. In this case, the gate of the transistor can be read as the base, the source as the emitter, and the drain as the collector.

1, 1B, 1C Comparator 2, 2C Differential input section 3, 3B, 3C Folded cascode section 4, 4C Output circuit INM Inverted input potential (first input potential)
INP non-inverting input potential (second input potential)
M1, M1C differential transistor (first differential transistor)
M2, M2C differential transistors (second differential transistors)
M3, M3C transistors (third transistors)
M4, M4C transistors (fourth transistors)
M5, M5C transistors M6, M6C transistors (sixth transistors)
M7, M7C transistors (fifth transistor, voltage clamp element)
R3 resistor

Claims (7)

a differential input unit having a first differential transistor and a second differential transistor through which currents having a current ratio corresponding to the first input potential and the second input potential flow respectively;
a folded cascode unit having a third transistor folded cascode connected to the first differential transistor and a fourth transistor folded cascode connected to the second differential transistor;
and an output circuit connected to the drain or collector of the fourth transistor and outputting an output signal,
The folded cascode section has a voltage clamp element that limits an increase or decrease in drain potential or collector potential of the fourth transistor when the fourth transistor is in an ON state. A comparator according to claim 1, wherein
The voltage clamp element clamps the drain potential or collector potential of the fourth transistor to a voltage corresponding to the drain potential or collector potential of the third transistor.
comparator. A comparator according to claim 2,
The voltage clamping element comprises a fifth transistor diode-connected between the drain or collector of the third transistor and the drain or collector of the fourth transistor.
comparator. A comparator according to claim 3,
The folded cascode unit has a resistor connected between the gate and drain or between the base and collector of the fifth transistor,
comparator. The comparator according to any one of claims 1 to 4,
the output circuit has a sixth transistor having a gate or base connected to the drain or collector of the fourth transistor;
the threshold voltage of the sixth transistor is lower than the threshold voltages of the third transistor and the fourth transistor;
comparator. The comparator according to any one of claims 1 to 5,
at least one of said transistors is composed of a field effect transistor;
comparator. The comparator according to any one of claims 1 to 6,
at least one of said transistors is composed of a bipolar transistor;
comparator.

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