CN117850524A - Bias current generating circuit and chip - Google Patents

Abstract

Embodiments of the present disclosure provide a bias current generation circuit and a chip. The bias current generation circuit includes: the bias voltage generating circuit, the first bias current generating circuit and the second bias current generating circuit. The bias voltage generating circuit is configured to generate a first bias voltage signal, a second bias voltage signal and a third bias voltage signal, and to provide the first bias voltage signal to the first bias current generating circuit via a first node, the second bias voltage signal to the second bias current generating circuit via a second node, and the third bias voltage signal to the second bias current generating circuit via a third node; the first bias current generating circuit is configured to generate a PMOS bias current signal according to the first bias voltage signal; the second bias current generating circuit is configured to generate an NMOS bias current signal based on the second bias voltage signal and the third bias voltage signal.

Description

Bias current generating circuit and chip

Technical Field

The embodiment of the disclosure relates to the technical field of integrated circuits, in particular to a bias current generating circuit and a chip.

Background

In analog integrated circuits, bias current is an important reference source for the circuit to function properly, and thus bias current generation circuits are an indispensable module for analog chips.

Fig. 1 is an exemplary circuit diagram of a bias current generation circuit 100. The NMOS transistors Mn1, mn2 and the resistor R1 form a negative feedback loop, so that the point a potential is va=vgs_mn1, the point B potential is vb=vgs_mn1+vgs_mn2, where vgs_mn1 is the gate-source voltage of the NMOS transistor Mn1, and vgs_mn2 is the gate-source voltage of the NMOS transistor Mn 2. The current flowing through the NMOS transistor Mn1 is thus the current I across the resistor R0 _R0 ＝[Vcc–(Vgs_Mn1+Vgs_Mn2)]R0, the current flowing through the NMOS transistor Mn2 and the PMOS transistor Mp1 are the current I across the resistor R1 _R1 =vgs_mn1/R1. The PMOS transistors Mp2 and Mp1 form a current mirror circuit, and the aspect ratio of the PMOS transistor Mp2 is proportional to the aspect ratio of the PMOS transistor Mp1, and assuming that the ratio is k, the drain-source current of the PMOS transistor Mp2 is ip=k×vgs_mn1/R1, which is the bias current generated by the circuit 100, and the bias current is a PMOS bias current signal.

However, in a typical analog integrated circuit, both PMOS bias current signals and NMOS bias current signals are necessary, and the bias current generating circuit 100 can only supply PMOS bias current and cannot generate NMOS bias current signals.

Disclosure of Invention

The embodiment of the disclosure aims to provide a bias current generating circuit and a chip, which can generate a PMOS bias current signal and an NMOS bias current signal simultaneously without generating redundant current branches, reduce the waste of current and ensure the simple circuit structure.

To achieve the above object, a first aspect of an embodiment of the present disclosure provides a bias current generating circuit, including: the bias voltage generating circuit, the first bias current generating circuit and the second bias current generating circuit. Wherein the bias voltage generating circuit is configured to generate a first bias voltage signal, a second bias voltage signal, and a third bias voltage signal, and to provide the first bias voltage signal to the first bias current generating circuit via a first node, the second bias voltage signal to the second bias current generating circuit via a second node, and the third bias voltage signal to the second bias current generating circuit via a third node; the first bias current generating circuit is configured to generate a PMOS bias current signal according to the first bias voltage signal; the second bias current generating circuit is configured to generate an NMOS bias current signal based on the second bias voltage signal and the third bias voltage signal.

In some embodiments of the present disclosure, the bias voltage generating circuit includes: the first resistor, the first transistor, the second transistor, the third transistor and the second resistor. Wherein a first end of the first resistor is coupled to a first voltage end, and a second end of the first resistor is coupled to a second pole of the second transistor, a control pole of the third transistor, and the second node; the control electrode of the first transistor is coupled with the second electrode of the first transistor and the first node, and the first electrode of the first transistor is coupled with the first voltage end; a control electrode of the second transistor is coupled to the first electrode of the third transistor, the first end of the second resistor and the third node, and the first electrode of the second transistor is coupled to a second voltage end; a second pole of the third transistor is coupled to the first node; the second end of the second resistor is coupled to the second voltage end.

In some embodiments of the present disclosure, the first bias current generating circuit includes: and a fourth transistor. The control electrode of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the output terminal of the PMOS bias current signal.

In some embodiments of the present disclosure, the second bias current generating circuit includes: and a fifth transistor. The control electrode of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the output end of the NMOS bias current signal.

In some embodiments of the disclosure, the first transistor is a PMOS transistor, and the second transistor and the third transistor are both NMOS transistors.

In some embodiments of the present disclosure, the fourth transistor is a PMOS transistor and the aspect ratio of the fourth transistor is proportional to the aspect ratio of the first transistor.

In some embodiments of the present disclosure, the fifth transistor is an NMOS transistor, and the aspect ratio of the fifth transistor is proportional to the aspect ratio of the third transistor.

In some embodiments of the disclosure, the third transistor and the fifth transistor form a differential pair, and the NMOS bias current signal is obtained by dividing a tail current source signal of the differential pair by a ratio of a width to length ratio between the fifth transistor and the third transistor.

In some embodiments of the present disclosure, the NMOS bias current signal is positively correlated with the third bias voltage signal.

According to a second aspect of the present disclosure, a chip is provided. The chip comprises a bias current generating circuit according to the first aspect of the present disclosure.

Additional features and advantages of embodiments of the present disclosure will be set forth in the detailed description which follows.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the embodiments of the disclosure. In the drawings:

FIG. 1 is an exemplary circuit diagram of a bias current circuit;

FIG. 2 is an exemplary circuit diagram of a bias current generation circuit that may generate a PMOS bias current signal and an NMOS bias current signal simultaneously;

FIG. 3 is a schematic block diagram of a bias current generation circuit according to an embodiment of the present disclosure;

FIG. 4 is an exemplary circuit diagram of a bias current generating circuit according to an embodiment of the present disclosure;

fig. 5 is an exemplary circuit diagram of a differential pair of transistors in a bias current generating circuit according to an embodiment of the present disclosure.

Elements in the figures are illustrated schematically and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

In all embodiments of the present disclosure, since the source and drain of a Metal Oxide Semiconductor (MOS) transistor are symmetrical and the on-current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control pole and the remaining two terminals of the MOS transistor are referred to as the first pole and the second pole, respectively. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

Fig. 2 shows an exemplary circuit diagram of a bias current generation circuit 200 capable of generating both PMOS bias current signals and NMOS bias current signals. The circuit 200 is a current mirror circuit formed by adding a PMOS transistor Mp3 having a mirror image relationship with the PMOS transistor Mp1, and an NMOS transistor Mn3 and an NMOS transistor Mn4 to the circuit 100. Since the width-to-length ratio of the PMOS transistor Mp3 and the PMOS transistor Mp1 are equal, the current of the branch of the PMOS transistor Mp3 and the NMOS transistor Mn3 is I _R1 =vgs_mn1/R1. The ratio between the width-to-length ratio of the NMOS transistor Mn4 and the width-to-length ratio of the NMOS transistor Mn3 is m, and the drain-source current in=m×vgs_mn1/R2 of the NMOS transistor Mn4 is the generated NMOS bias current signal. The current in the branches of PMOS transistor Mp3 and NMOS transistor Mn3 flows from supply voltage Vcc to GND, which does not contribute to the subsequent circuit and causes a large quiescent current consumption for low power products.

In order to achieve that the PMOS bias current signal and the NMOS bias current signal can be generated simultaneously, and no redundant current branches are generated, the circuit structure is guaranteed to be simple, and fig. 3 shows a schematic block diagram of a bias current generating circuit 300 according to an embodiment of the present disclosure. As shown in fig. 3, the bias current generating circuit 300 may include: the bias voltage generating circuit 310, the first bias current generating circuit 320, and the second bias current generating circuit 330.

The bias voltage generating circuit 310 may be coupled to the first bias current generating circuit 320, the second bias current generating circuit 330, the first voltage terminal V1 and the second voltage terminal V2. The first bias current generating circuit 320 may be coupled to the bias voltage generating circuit 310, the first voltage terminal V1 and the output terminal Ip of the PMOS bias current signal. The second bias current generating circuit 330 may be coupled to the bias voltage generating circuit 310 and the output terminal In of the NMOS bias current signal.

Wherein the bias voltage generating circuit 310 may be configured to generate a first bias voltage signal VN1, a second bias voltage signal VN2 and a third bias voltage signal VN3, and to provide the first bias voltage signal VN1 to the first bias current generating circuit 320 via a first node N1, the second bias voltage signal VN2 to the second bias current generating circuit 330 via a second node N2, and the third bias voltage signal VN3 to the second bias current generating circuit 330 via a third node N3. The first bias current generating circuit 320 may be configured to generate a PMOS bias current signal Ip according to the first bias voltage signal VN 1. The second bias current generating circuit 330 may be configured to generate an NMOS bias current signal In according to the second bias voltage signal VN2 and the third bias voltage signal VN3.

By the bias current generating circuit 300 of the embodiment of the present disclosure, in the case that the PMOS bias current signal and the NMOS bias current signal can be simultaneously generated, no unnecessary current branch is generated, no current is wasted, and the circuit structure is ensured to be simple.

Fig. 4 shows an exemplary circuit diagram of the bias current generating circuit 300 according to an embodiment of the present disclosure. As shown in fig. 4, the bias voltage generating circuit 310 may include: the first resistor R1, the first transistor M1, the second transistor M2, the third transistor M3 and the second resistor R2. The first end of the first resistor R1 is coupled to the first voltage end V1, and the second end of the first resistor R1 is coupled to the second pole of the second transistor M2, the control pole of the third transistor M3, and the second node N2. The control electrode of the first transistor M1 is coupled to the second electrode of the first transistor M1 and the first node N1, and the first electrode of the first transistor M1 is coupled to the first voltage terminal V1. The control electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3, the first end of the second resistor R2, and the third node N3, and the first electrode of the second transistor M2 is coupled to the second voltage end V2. The second pole of the third transistor M3 is coupled to the first node N1. The second end of the second resistor R2 is coupled to the second voltage end V2.

The first bias current generating circuit 320 may include: and a fourth transistor M4. The control electrode of the fourth transistor M4 is coupled to the first node N1, the first electrode of the fourth transistor M4 is coupled to the first voltage terminal V1, and the second electrode of the fourth transistor M4 is coupled to the output terminal of the PMOS bias current signal.

The second bias current generating circuit 330 may include: and a fifth transistor M5. The control electrode of the fifth transistor M5 is coupled to the second node N2, the first electrode of the fifth transistor M5 is coupled to the third node N3, and the second electrode of the fifth transistor M5 is coupled to the output terminal of the NMOS bias current signal.

In the example of fig. 4, the high voltage signal Vcc is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 and the fourth transistor M4 are PMOS transistors, and the second transistor M2, the third transistor M3 and the fifth transistor M5 are NMOS transistors. In addition, the width-to-length ratio of the fourth transistor M4 is proportional to the width-to-length ratio of the first transistor M1, for example, the width-to-length ratio of the fourth transistor M4 is k times the width-to-length ratio of the first transistor M1. The width-to-length ratio of the fifth transistor M5 is proportional to the width-to-length ratio of the third transistor M3, for example, the width-to-length ratio of the fifth transistor M5 is M times the width-to-length ratio of the third transistor M3. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 4 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the example shown in fig. 4.

The operation of the bias current generating circuit 300 according to the embodiment of the present disclosure is described below with reference to the example of fig. 4.

In the embodiment of the present disclosure, the bias voltage generating circuit 310 provides the first bias voltage signal VN1 to the fourth transistor M4 through the first node N1, and the first transistor M1 and the fourth transistor M4 constitute a current mirror circuit, and the width-to-length ratio of the fourth transistor M4 is k times that of the first transistor M1, so that the PMOS bias current signal output by the fourth transistor M4 is k times that of the current flowing through the first transistor M1. Meanwhile, since the third bias voltage signal VN3 is equal to the gate-source voltage of the second transistor M2, and the current flowing through the first transistor M1 is equal to the current flowing through the third transistor M3, that is, VN 3/r2=vgs_m2/R2, where VN3 is the voltage of the third node N3 and vgs_m2 is the gate-source voltage of the second transistor M2. Thus, PMOS bias current signal ip=k×vgs_m2/R2.

For the NMOS bias current signal, the bias voltage generating circuit 310 provides the second bias voltage signal VN2 and the third bias voltage signal VN3 to the second bias current generating circuit 330, that is, the node voltage VN2 of the second node N2 and the node voltage VN3 of the third node N3. Wherein the second bias voltage signal vn2=vgs_m2+vgs_m3_m5, wherein vgs_m3_m5 is the gate-source voltage of the third transistor M3 and the fifth transistor M5. In addition, since the third transistor M3 and the fifth transistor M5 form a differential pair, as shown in the circuit example diagram of fig. 5, the gates of the third transistor M3 and the fifth transistor M5 are both coupled to the second node N2, and thus the current flowing through the second resistor R2 can be used as the tail current of the differential pair of the third transistor M3 and the fifth transistor M5. Since the gate-source voltages of the third transistor M3 and the fifth transistor M5 are equal, the tail current can be distributed in proportion to the width-to-length ratio of the third transistor M3 and the fifth transistor M5 in the differential pair. Since the ratio of the width to length ratio of the fifth transistor M5 to the third transistor M3 is M, the current flowing through the second resistor R2 can be set to 1: the ratio of M is distributed to the third transistor M3 and the fifth transistor M5, that is, the drain-source current i3=vgs_m2/r2×1/(1+m) flowing through the third transistor M3, the drain-source current i5=vgs_m2/r2×m/(1+m) flowing through the fifth transistor M5, and thus the NMOS bias current signal is the drain-source current I5 of the fifth transistor M5.

In the embodiment of the present disclosure, if the current flowing through the first transistor M1 is set equal to the current flowing through the PMOS transistor Mp1 in the circuit 100 shown in fig. 1, the equation i3=vgs_m2/r2×1/(1+m) =vgs_mn1/R1, i.e., r2=r1×1/(1+m) can be obtained, wherein the second transistor M2 in fig. 4 is the NMOS transistor Mn1 in fig. 1, i.e., vgs_m2=vgs_mn1. It can be seen that the resistance of the second resistor R2 generating the NMOS bias current signal in fig. 4 is 1/(1+m) times that of the resistor R1 in comparison with that of the resistor R1 in fig. 1.

In summary, compared with the existing bias current generation circuit, the bias current generation circuit 300 in the embodiment of the disclosure can save one current branch, reduce the current waste, reduce the resistance area, and save the chip area and the power consumption under the condition of generating the PMOS bias current signal and the NMOS bias current signal simultaneously.

The embodiment of the disclosure also provides a chip. The chip includes a bias current generating circuit according to an embodiment of the present disclosure. The chip can be used in the field of industrial control, for example.

The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is for example an industrial control device.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A bias current generating circuit, comprising: a bias voltage generating circuit, a first bias current generating circuit and a second bias current generating circuit,

wherein the bias voltage generating circuit is configured to generate a first bias voltage signal, a second bias voltage signal, and a third bias voltage signal, and to provide the first bias voltage signal to the first bias current generating circuit via a first node, the second bias voltage signal to the second bias current generating circuit via a second node, and the third bias voltage signal to the second bias current generating circuit via a third node;

the first bias current generating circuit is configured to generate a PMOS bias current signal according to the first bias voltage signal;

the second bias current generating circuit is configured to generate an NMOS bias current signal based on the second bias voltage signal and the third bias voltage signal.

2. The bias current generating circuit according to claim 1, wherein the bias voltage generating circuit comprises: a first resistor, a first transistor, a second transistor, a third transistor, and a second resistor,

wherein a first end of the first resistor is coupled to a first voltage end, and a second end of the first resistor is coupled to a second pole of the second transistor, a control pole of the third transistor, and the second node;

the control electrode of the first transistor is coupled with the second electrode of the first transistor and the first node, and the first electrode of the first transistor is coupled with the first voltage end;

a control electrode of the second transistor is coupled to the first electrode of the third transistor, the first end of the second resistor and the third node, and the first electrode of the second transistor is coupled to a second voltage end;

a second pole of the third transistor is coupled to the first node;

the second end of the second resistor is coupled to the second voltage end.

3. The bias current generating circuit according to claim 2, wherein the first bias current generating circuit includes: a fourth transistor is provided which is connected to the first transistor,

the control electrode of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the output terminal of the PMOS bias current signal.

4. The bias current generating circuit according to claim 2, wherein the second bias current generating circuit includes: a fifth transistor is provided which has a third transistor,

the control electrode of the fifth transistor is coupled to the second node, the first electrode of the fifth transistor is coupled to the third node, and the second electrode of the fifth transistor is coupled to the output end of the NMOS bias current signal.

5. The bias current generating circuit of claim 2, wherein said first transistor is a PMOS transistor, and said second transistor and said third transistor are both NMOS transistors.

6. The bias current generating circuit of claim 3, wherein said fourth transistor is a PMOS transistor and an aspect ratio of said fourth transistor is proportional to an aspect ratio of said first transistor.

7. The bias current generating circuit according to claim 4, wherein the fifth transistor is an NMOS transistor, and wherein an aspect ratio of the fifth transistor is proportional to an aspect ratio of the third transistor.

8. The bias current generating circuit according to claim 7, wherein the third transistor and the fifth transistor form a differential pair, and wherein the NMOS bias current signal is obtained by dividing a tail current source signal of the differential pair by a ratio of a width to a length of the fifth transistor to a width of the third transistor.

9. The bias current generating circuit of claim 8, wherein said NMOS bias current signal is positively correlated with said third bias voltage signal.

10. A chip, comprising: the bias current generating circuit according to any one of claims 1 to 9.