US7457090B2 - Use of a known common-mode voltage for input overvoltage protection in pseudo-differential receivers - Google Patents
Use of a known common-mode voltage for input overvoltage protection in pseudo-differential receivers Download PDFInfo
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- US7457090B2 US7457090B2 US10/988,122 US98812204A US7457090B2 US 7457090 B2 US7457090 B2 US 7457090B2 US 98812204 A US98812204 A US 98812204A US 7457090 B2 US7457090 B2 US 7457090B2
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- 230000000295 complement effect Effects 0.000 claims description 6
- 230000002596 correlated effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 16
- 230000011664 signaling Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
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- 230000001066 destructive effect Effects 0.000 description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- H03F1/52—Circuit arrangements for protecting such amplifiers
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- the present invention relates to semiconductor integrated circuits and, in particular to differential receivers and the protection of low voltage input devices against large input voltages.
- Advancements in semiconductor fabrication technology enable the geometries of semiconductor devices to be progressively reduced so that more devices can fit on a single integrated circuit.
- core voltages of integrated circuits are being reduced to prevent damage to the small devices and to reduce overall power consumption.
- power supplies are now being reduced from 3.3 volts to much lower voltages such as 2.5 volts, 1.8 volts and 1.5 volts.
- these low voltage devices are often interconnected at a board level to other devices that may operate at higher supply voltages. Also, these devices may be exposed to reflections and other events causing voltage spikes that can damage these small devices.
- an integrated circuit having a differential or pseudo-differential receiver can incorporate voltage-tolerant transistors within the receiver, which can handle larger input voltage swings and can provide a buffer to the smaller, more fragile core devices on the integrated circuit.
- voltage-tolerant transistors typically have lower performance and consume a larger silicon area and more power than a typical transistor.
- the fastest, smallest transistors that are available in the technology can be used for the receiver. These transistors have the highest switching speeds and consume the least area and power. Often, however, the fastest transistors available in a technology are low-voltage transistors, which may not be able to directly tolerate certain signal levels. When this is the case, some sort of over-voltage protection network is required to prevent destructive voltages from reaching the low-voltage transistors in the receiver.
- An example of an input overvoltage protection circuit includes a pass gate, which clamps the differential input signals to a desired voltage.
- a receiver can be constructed from 1.5V ⁇ 10% transistors and used in a two-volt signaling environment.
- the pass gate protection circuit can use an internally generated bias voltage to limit the differential input signal to a maximum of 1.5 ⁇ 10%.
- this type of a protection circuit can be difficult to implement. If the voltage to which the signal is limited is less than the zero-crossing point of the differential signals, the receiver may never trip. If the voltage limit is greater than the zero-crossing point but simply to close to the zero-cross point, then the input protection circuit can introduce a large timing distortion to the input signals, which reduces performance of the receiver. Improved overvoltage protection circuits are therefore desired for integrated circuit applications such as differential or pseudo-differential receivers. Improved bias generators are also desired for generating the bias voltages used by the protection circuit without consuming a relatively large area and power.
- One embodiment of the present invention is directed to a method of protecting elements of a receiver from overvoltages.
- the method includes: receiving a pseudo-differential signal comprising a true signal and a reference voltage; limiting the true signal to a protection voltage, which is correlated to the reference voltage, to produce a protected true signal; and applying the protected true signal and the reference voltage to the receiver.
- Another embodiment of the present invention is directed to a method of protecting a receiver from overvoltages.
- the method includes: receiving a pseudo-differential signal comprising a true signal and a reference voltage; summing the reference voltage with another voltage to produce a protection voltage; limiting the true signal to the protection voltage to produce a protected true signal; and applying the protected true signal and the reference voltage to the receiver.
- the system includes a pseudo-differential signal input, a bias generator, a voltage protection circuit and a receiver.
- the pseudo-differential signal input includes a true signal input and a reference voltage input.
- the bias generator generates a bias voltage as a function of a voltage on the reference voltage input.
- the voltage protection circuit is coupled to the true signal input and has a protected true signal output that is limited to a protection voltage as a function of the bias voltage.
- the receiver includes true and complement inputs, which are coupled to the protected true signal output and the reference voltage input, respectively.
- FIG. 1 is a diagram illustrating a full-differential receiver.
- FIG. 2 is a diagram illustrating a pseudo-differential receiver.
- FIG. 3 is a diagram illustrating an input overvoltage protection circuit coupled to the full-differential receiver shown in FIG. 1 .
- FIG. 4 is a diagram illustrating a bias circuit for generating a bias voltage for the protection circuit shown in FIG. 3 .
- FIG. 5 is a diagram illustrating an input overvoltage protection circuit coupled to the pseudo-differential amplifier shown in FIG. 2 .
- FIG. 6 is a graph illustrating timing distortion that can be introduced by the overvoltage protection circuit.
- FIG. 7 is a diagram illustrating a voltage bias circuit, which bases the bias voltage for the protection circuit on the reference voltage from a pseudo-differential input signal.
- FIG. 8 is a graph illustrating reduced timing distortion achieved with the bias circuit shown in FIG. 7 .
- FIG. 9 is a schematic diagram illustrating a DC summing circuit, which can be used for generating a protection voltage in accordance with one embodiment of the present invention.
- FIG. 10 is a schematic diagram illustrating a DC voltage summing circuit according to an alternative embodiment of the present invention.
- FIG. 11 is a graph illustrating the output of the voltage summing circuit shown in FIG. 10 versus temperature for a range of manufacturing tolerances.
- FIG. 12 is a graph illustrating the difference between an ideal output voltage and the actual output of the circuit shown in FIG. 10 over a wide range of voltage tolerances.
- an over-voltage protection circuit which limits the input voltages of the receiver to a voltage that is based on a known common-mode voltage in a pseudo-differential signaling environment.
- Pseudo-differential signaling has become increasing popular for transmitting signals from one location to another. Pseudo-differential signaling has many of the benefits of full-differential signaling, but requires approximately half of the pins (or number of required electrical connections) as compared to full-differential signaling.
- FIG. 1 is a diagram illustrating a typical full-differential receiver 10 on an integrated circuit.
- the integrated circuit has a pair of input pins 12 , labeled “Vtrue” and “Vcomp” for receiving a pair of true and complement differential input signals, respectively.
- Differential receiver 10 includes true and complement voltage inputs labeled “Vtrue” and “Vcomp” for receiving the true and complement signals from pins 12 .
- receiver 10 outputs a logic low or “0” level when Vtrue ⁇ Vcomp, and outputs a logic high or “1” level when Vtrue>Vcomp.
- the integrated circuit has a voltage supply rail VDDIO and a corresponding ground supply rail (not shown in FIG. 1 ) for biasing the transistors in the input-output region of the integrated circuit, including the input transistors within receiver 10 .
- the integrated circuit can also have other voltage supplies, such as a core voltage supply VDD for biasing the transistors in the core region of the integrated circuit.
- the voltage level on VDDIO is typically higher than the core supply voltage.
- the full differential receiver 10 shown in FIG. 1 requires two electrical input connections (pins 12 ) for each differential signal path. Therefore, a 32-bit wide bus would require 64 signal pins.
- FIG. 2 is a diagram illustrating a pseudo-differential receiver 20 , having a pair of input pins 22 , labeled “Vtrue” and “Vref” for receiving a true input signal and a reference voltage, respectively.
- Receiver 20 includes true and complement voltage inputs labeled “Vtrue” and “Vcomp” for receiving the true and reference signals from pins 22 .
- Vtrue true and complement voltage inputs labeled “Vtrue” and “Vcomp” for receiving the true and reference signals from pins 22 .
- receiver 20 outputs a logic low or “0” level when Vtrue ⁇ Vref, and outputs a logic high or “1” level when Vtrue>Vref.
- the common-mode or “zero-crossing” voltage, Vcommon-mode, of the pseudo-differential input signal is fixed at Vref. Since Vref is fixed, a pseudo-differential signal requires only one electrical connection for each data path, plus one connection for the reference voltage. Therefore, a 32-bit wide bus would require 32 input pins plus a Vref pin. As result, pseudo-differential receivers have approximately half the “pin count” (or required number of electrical connections) as compared to full-differential receivers.
- FIG. 3 is a diagram illustrating an input overvoltage protection circuit 30 coupled between the full-differential receiver 10 (shown in FIG. 1 ) and the differential input pins 12 .
- protection circuit 30 includes a pair of pass gate transistors MN 1 and MN 2 , which are coupled in series with the differential input pins 12 .
- Pass gate transistors MN 1 and MN 2 have their control inputs, or gates, coupled to a bias voltage Vbias.
- the bias voltage Vbias is set such that the voltages applied to the Vtrue and Vcomp inputs of differential receiver 10 , at nodes 16 and 18 , do not exceed a predetermined protection voltage, Vprotection.
- receiver 10 can be constructed from faster, low-voltage transistors, which are biased between a lower supply voltage, such as VDD 15 , having a voltage of 1.5v ⁇ 10%.
- VDD 15 a lower supply voltage
- Vbias is therefore set to limit the voltages at the inputs of receiver 10 to 1.5V ⁇ 10%.
- FIG. 4 is a schematic diagram illustrating a bias circuit 40 for generating the bias voltage Vbias for protection circuit 30 .
- Bias circuit 40 includes amplifier 42 , current source 44 , P-channel transistor MP 1 and N-channel transistor MN 3 .
- Amplifier 42 is biased between a 3.3 volt supply rail VDD 33 and ground supply rail VSS.
- the non-inverting input of amplifier 42 is coupled to the protection voltage Vprotect, which is the desired voltage to which the incoming differential signal should be limited.
- Vprotect is coupled to voltage supply rail VDD 15 , which has an actual voltage of 1.5v 10%.
- Amplifier 42 has an output coupled to the gate of transistor MN 3 and to bias output Vbias.
- Transistor MN 3 is coupled in series with transistor MP 1 between voltage supply terminal VDD 33 and current source 44 .
- Current source 44 is coupled between the source of MN 3 and VSS.
- the source of transistor MN 3 is coupled in a feedback path to the inverting input of amplifier 42 .
- the gate of MP 1 is coupled to VSS.
- amplifier 42 adjusts the voltage level on its output at the gate of transistor MN 3 such that the source of MN 3 is forced to 1.5V ⁇ 10%.
- Current source 44 preferably supplies a current that is less than the input bias current of receiver 10 . Since the gates of transistors MN 1 and MN 2 in FIG. 3 are coupled to the same bias voltage as the gate of MN 3 and the transistors have roughly the same drain-source current levels, the sources of transistors MN 1 and MN 2 are limited to 1.5V ⁇ 10%.
- FIG. 5 is a diagram illustrating input voltage protection circuit 30 coupled to the pseudo-differential amplifier 20 shown in FIG. 2 .
- the data signal Vtrue is passed through protection circuit 30 to the Vtrue input of receiver 20 .
- the reference voltage Vref is coupled to the Vcomp input of receiver 20 , which therefore resides at 1V.
- Protection circuit 30 limits the voltage on node 50 to Vprotect based on the bias voltage Vbias. For example as described with reference to FIG. 4 , Vbias can be set to limit the voltage on node 50 to 1.5V ⁇ 10%. With protection circuit 30 , the input elements of receiver 20 can be implemented with low-voltage transistors, which are biased between VDD 15 and VSS.
- Vprotect is less than the zero-crossing voltage (Vcommon-mode or Vref), the receiver will never trip. Even if Vprotect is greater than but close to the zero-crossing voltage, input protection circuit 30 can introduce a large timing distortion to the input signals.
- the protection voltage Vprotect should therefore be set as high above the zero-crossing voltage as possible while still protecting the small input devices within the receiver from damaging voltage levels.
- FIG. 6 is a graph illustrating timing distortion that can be introduced by voltage protection circuit 30 when the bias voltage Vbias is based solely on the voltage of a voltage supply rail, such as VDD 15 , within the integrated circuit.
- waveform 60 represents the voltage on unprotected input pin Vtrue in FIG. 5
- waveform 62 represents the protected Vtrue on node 50 after protection circuit 30 .
- Vprotect set at 1.5V ⁇ 10%, the lowest value of Vprotect is therefore 1.35V, which is close to the 1V zero-crossing voltage on Vref. This results in timing distortion and delay, shown at arrows 64 , as Vtrue crosses the common-mode voltage.
- the response at the output of protection circuit 30 becomes distorted relative to the response at the input, particularly when Vprotect comes close to the common-mode voltage.
- the timing distortion through the voltage protection circuit is minimized by correlating the protection voltage to the actual common-mode voltage. If the common-mode voltage is higher in a particular system environment, the protection voltage also increases, thereby maintaining a sufficient “head room” between the two values.
- the common-mode, zero-crossing voltage Vref is known.
- the protection voltage Vprotect can be based in whole or in part on Vref itself rather than on some other voltage in the system. By doing so, the difference between Vprotect and the zero-crossing voltage can be maximized.
- FIG. 7 is a diagram illustrating a voltage bias circuit 70 according to one embodiment of the present invention.
- Bias circuit 70 includes amplifier 72 , current source 74 , P-channel transistor MP 2 and N-channel transistor MN 4 .
- Voltage bias circuit 70 is similar to voltage bias circuit 40 shown in FIG. 4 , but the non-inverting input of amplifier 72 is coupled to a protection voltage level Vprotect, which is a function of Vref (as opposed to some other voltage level in the system).
- Vprotect protection voltage level
- Amplifier 72 sets the voltage level on Vbias such that the protected Vtrue voltage on node 50 ( FIG. 5 ) is limited to Vprotect.
- the input transistors in pseudo-differential receiver 20 can tolerate 1.5V ⁇ 10%.
- the power supply voltages have 10% tolerances, and Vref can range from 0.8V to 1.0V.
- Table 1 shows sample comparisons of the difference between Vprotect and Vzero-crossing for different functions of Vprotect, where Vmax is the absolute maximum voltage the receiver can tolerate.
- Vprotect is based on any ⁇ 10% supply voltage, such as the VDD 15 supply voltage.
- Vref 1V
- VDD 15 1.35V
- the difference between these two voltages is only 350 mV.
- the difference between Vprotect and Vzero-crossing is only 492 mV when Vprotect is based on a bandgap reference.
- Vprotect is based on Vref.
- the greater the difference between Vprotect and Vzero-crossing the smaller the timing distortion on the protected Vtrue.
- FIG. 8 is a graph illustrating reduced timing distortion when Vprotect is based at least in part on Vref.
- Waveform 80 represents the voltage on the Vtrue input pin
- waveform 82 represents protected Vtrue voltage level after the pass gate, on node 50 .
- Arrows 84 represent the reduced timing distortion between these two voltage levels at the zero-crossing point relative to the timing distortion shown in FIG. 6 .
- the protection circuit can take advantage of the fact that the zero-crossing voltage Vref is known. By basing the protection voltage in whole or in part on Vref rather than on some other voltage in the system, the difference between Vprotect and Vzero-crossing can be maximized while minimizing signal distortion.
- the protection circuit 30 shown in FIG. 5 is simply one example of a protection circuit that can be used in accordance with the present invention.
- Other overvoltage protection circuits can also be used in alternative embodiments.
- an active clamp can be used to clamp the input voltages based at least in part on the zero-crossing voltage.
- Any overvoltage protection circuit can be used that limits the input voltages seen by the receiver to a voltage that is based at least in part on the reference voltage of a pseudo-differential signal.
- bias circuits shown in FIGS. 4 and 7 are examples of bias circuit that can be used in accordance with the present invention. Other bias circuits can be used in alternative embodiments of the present invention.
- a variety of circuits can be used to generate the appropriate voltage level on Vprotect as a function of Vref, in accordance with the present invention.
- a DC voltage summing circuit can be used to sum Vref with some other voltage level in the system, such as a fraction of a power supply voltage.
- FIG. 9 is a schematic diagram illustrating a DC summing circuit 90 , which can be used for generating Vprotect in accordance with one embodiment of the present invention.
- Summing circuit 90 includes voltage inputs V 1 and V 2 , input resistors R 1 and R 2 , feedback resistor Rf, amplifier 92 and output Vprotect.
- the non-inverting input of amplifier 92 is coupled to VSS.
- the inverting input of amplifier 92 is coupled to voltage inputs V 1 and V 2 through input resistors R 1 and R 2 , respectively.
- Feedback resistor Rf is coupled between Vprotect and the inverting inputs of amplifier 92 .
- ⁇ V protect ⁇ (( Rf/R 1)( v 1)+( Rf/R 2)( V 2)) Eq. 1
- V 1 is coupled to Vref and V 2 is coupled to a suitable supply voltage rail
- the values of R 1 , R 2 and Rf can be selected such that summing circuit 90 adds Vref to a desired fraction of the power supply voltage.
- circuit 90 consumes a relatively large amount of power and area. Also, if the input resistors draw an unacceptable level of current off of Vref, an additional buffering operational amplifier may also be required. This further increases the power and area consumed by the circuit.
- FIG. 10 is a schematic diagram illustrating a DC voltage summing circuit 100 according to another embodiment of the present invention, which consumes much less power and area than variations on the circuit shown in FIG. 9 .
- Summing circuit 100 includes N-channel transistors MN 5 and MN 6 and P-channel transistors MP 3 -MP 7 .
- Transistors MN 5 and MN 6 are native MOS devices having very low gate-source thresholds and body effects (gamma).
- transistors MN 5 and MN 6 can have near zero gate-source voltages, such as in the range of 0.1V to 0.3V or lower.
- MN 5 and MN 6 are substantially identical to one another.
- Transistor MN 5 operates as a current source and has a gate coupled to the reference voltage Vref, a source coupled to Vss and a drain coupled to the gate and drain of MP 3 .
- the setup voltage on Vref generates a setup current Is into the drain of transistor MN 5 .
- Transistors MP 3 and MP 4 are coupled together to form a current mirror, which mirrors the setup current Is from the drain of transistor MP 3 to the drain of transistor MP 4 .
- Transistor MP 3 has a gate and drain coupled to the drain of transistor MN 5 and a source coupled to voltage supply terminal VDDIO.
- Transistor MP 4 has a gate coupled to the gate and drain of MP 3 , a drain coupled to the gate and drain of MN 6 and a source coupled to VDDIO.
- the source of transistor MN 6 is coupled to node 102 .
- the gate and drain of MN 6 are also coupled to voltage output Vprotect.
- the voltage on Vprotect is the sum of the gate-source voltage of MN 6 (Vref) and the voltage on node 102 . Node 102 therefore serves as a DC voltage input, which is summed with the first DC voltage input, Vref, to produce Vprotect.
- transistors MP 5 , MP 6 and MP 7 are coupled in series with one another to form a voltage divider between VDDIO and VSS.
- Transistor MP 5 has a source coupled to VDDIO and a gate and drain coupled to the source of MP 6 .
- Transistor MP 6 has a gate and drain coupled to node 102 and to the source of MP 7 .
- Transistor MP 7 has a gate and drain coupled to VSS.
- Transistors MP 5 -MP 7 divide the voltage on VDDIO by substantially a factor of three, such that the voltage on node 102 is substantially VDDIO/3.
- the number and sizes of MP 5 -MP 7 depend upon what fraction of VDDIO we want to add to Vref. In one embodiment, it was found that the most desirable voltage on Vprotect was Vref+VDDIO/3, where VDDIO was an available 1.8V ⁇ 10% voltage supply level. The voltage divider therefore generates the “VDDIO/3” term on node 102 .
- the factor of three was based primarily on the value of Vref, the voltage tolerances of the transistors used in the receiver, and the available voltage supply level to be divided. Any other suitable factor of a supply voltage can also be used in alternative embodiments.
- the voltage on node 102 is generated by some other type of bias voltage generator and based on an available voltage level in the system.
- FIG. 11 is a graph illustrating the output of voltage summing circuit 100 versus temperature for a range of manufacturing tolerances.
- Each cluster of curves in FIG. 11 represents a specific value of Vref and VDDIO.
- Each cluster has only about 30 mV of variation over a wide range of temperature and process conditions. The resulting protection voltage generated by the circuit is therefore very stable over these variables.
- FIG. 12 is a graph illustrating the difference between ideal output voltage Videal (Vref+VDDIO/3) and the actual output of the circuit over a wide range of VDDIO and Vref values.
- Videal ⁇ Vprotect is plotted of a function of temperature for all manufacturing tolerances and nine combinations of Vref (0.8V, 0.9V and 1.0V) and VDDIO (1.62V, 1.80V and 1.98V). As shown in FIG. 12 , the output Vprotect remains within 50 mV of the target voltage, Videal.
- the difference from the ideal voltage can be further reduced at the expense of increased DC power by using larger transistor devices and a greater ratio of current in the voltage divider to the setup current Is. Further accuracy can be obtained if the native N-channel devices can reside in their own Pwells to eliminate the body effect.
- the DC voltage summing circuit shown in FIG. 10 is therefore capable of accurately summing a DC voltage with some fraction of a power supply voltage or other voltage level. Such a DC voltage summing circuit can be used in a variety of applications, such as for generating the most appropriate reference voltage for an input overvoltage protection circuit.
- the DC voltage summing circuit consumes a significantly reduced area and power compared to conventional DC summing circuits.
Abstract
Description
TABLE 1 | ||
OPTION | Vmax | Vprotect − Vzero-cross |
Base Vprotect on any ±10% | 1.65 V | 350 mV (when Vref = 1 & |
supply (say VDD15) | VDD15 = 1.35 V) | |
Base Vprotect on a | 1.65 V | 492 mV (when Vref = 1 & |
multiplied ±5% bandgap | Vbgap is low) | |
reference | ||
Base Vprotect purely on | 1.65 V | 520 mV (when Vref = 0.8 V) |
Vref (say 1.65*Vref) | ||
Base Vprotect on Vref & | 1.65 V | 532 mV (when VDD15 = 1.35 V) |
VDD15 (say Vref + | ||
0.39*VDD15) | ||
−Vprotect=−((Rf/R1)(v1)+(Rf/R2)(V2)) Eq. 1
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8446204B2 (en) | 2011-01-27 | 2013-05-21 | Qualcomm Incorporated | High voltage tolerant receiver |
US8680891B2 (en) | 2011-01-27 | 2014-03-25 | Qualcomm Incorporated | High voltage tolerant differential receiver |
US9018799B2 (en) | 2012-05-24 | 2015-04-28 | Hamilton Sundstrand Corporation | Electrical power supply system having internal fault protection |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104270105B (en) * | 2014-09-16 | 2017-04-26 | 广州杰士莱电子有限公司 | Digital power amplifier circuit |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5159260A (en) * | 1978-03-08 | 1992-10-27 | Hitachi, Ltd. | Reference voltage generator device |
JPH06237124A (en) * | 1993-02-08 | 1994-08-23 | Nippon Telegr & Teleph Corp <Ntt> | Input protection circuit for differential amplifier |
US20050195543A1 (en) * | 2004-03-04 | 2005-09-08 | Via Technologies, Inc. | Overvoltage protection apparatus |
US7233201B2 (en) * | 2004-08-31 | 2007-06-19 | Micron Technology, Inc. | Single-ended pseudo-differential output driver |
-
2004
- 2004-11-12 US US10/988,122 patent/US7457090B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5159260A (en) * | 1978-03-08 | 1992-10-27 | Hitachi, Ltd. | Reference voltage generator device |
JPH06237124A (en) * | 1993-02-08 | 1994-08-23 | Nippon Telegr & Teleph Corp <Ntt> | Input protection circuit for differential amplifier |
US20050195543A1 (en) * | 2004-03-04 | 2005-09-08 | Via Technologies, Inc. | Overvoltage protection apparatus |
US7233201B2 (en) * | 2004-08-31 | 2007-06-19 | Micron Technology, Inc. | Single-ended pseudo-differential output driver |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8446204B2 (en) | 2011-01-27 | 2013-05-21 | Qualcomm Incorporated | High voltage tolerant receiver |
US8680891B2 (en) | 2011-01-27 | 2014-03-25 | Qualcomm Incorporated | High voltage tolerant differential receiver |
US9018799B2 (en) | 2012-05-24 | 2015-04-28 | Hamilton Sundstrand Corporation | Electrical power supply system having internal fault protection |
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