CN112202427A - Turnover point adjustable comparator - Google Patents

Turnover point adjustable comparator Download PDF

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Publication number
CN112202427A
CN112202427A CN202011282933.6A CN202011282933A CN112202427A CN 112202427 A CN112202427 A CN 112202427A CN 202011282933 A CN202011282933 A CN 202011282933A CN 112202427 A CN112202427 A CN 112202427A
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current
comparator
nmos tube
electrode
resistor
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CN112202427B (en
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甄少伟
杨涛
杨芮
吴东铭
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A comparator with an adjustable turning point comprises a comparison module and a transimpedance amplifier, wherein a second NMOS tube, a third NMOS tube and a fourth NMOS tube in the comparison module respectively form a current mirror structure with a first NMOS tube, and the current mirror structure is used for mirroring the current of a first current source to provide bias; bases of the first NPN type triode and the second NPN type triode are used as two input ends of the comparator, emitting electrodes are connected together through a fifth resistor and are respectively connected with the second current source and the third current source, and the turning point of the comparator is adjusted by adjusting the current values of the second current source and the third current source; in addition, by adding a current swing control system consisting of a third PMOS tube, a second PMOS tube and a first PMOS tube, the current swing of the output stage is not limited by the magnitude of tail current, and the static power consumption of the circuit can be reduced. The trans-impedance amplifier is used for converting output current information into voltage information and finishing linear conversion of I-V. The invention can realize voltage comparison and current comparison, and is particularly suitable for being used as a current comparator for DCR sampling.

Description

Turnover point adjustable comparator
Technical Field
The invention belongs to the field of integrated circuits and switching power supplies, and relates to a comparator with an adjustable turning point, which can realize a voltage comparison function and a current comparison function and is suitable for being used as a current comparator for DCR sampling.
Background
The loop control of the switching power supply mainly comprises two forms of voltage mode control and current mode control, wherein the loop control mode of the current mode has more advantages compared with the control mode of the voltage mode, such as: small area, low power consumption, high speed, etc. Therefore, current mode control is widely used in switching power supplies, and in current mode control, a current comparator plays a crucial role, so the design of the current comparator is very important. Under the control mode of the Current mode, the traditional Current sampling technology comprises Resistance sampling, SENSEFET sampling and Direct Current Resistance (DCR) sampling, wherein the DCR sampling mode can effectively improve the efficiency of the switching power supply, so that the Current sampling technology is widely applied.
The conventional current comparator usually consists of a differential structure, which is usually used in a differential amplifier, the bias current and the output stage current of the differential amplifier are provided by a tail current source, but the swing of the output stage current is limited by the size of the tail current source. The two inputs of the current comparator are generally the sampling current and the output of the error amplifier, but the peak current of the DCR sampling cannot be effectively controlled. Aiming at the defects of the traditional current comparator, a new current comparator structure needs to be provided.
Disclosure of Invention
Aiming at the defects that the traditional current comparator has output-stage current swing limitation and the peak current of DCR sampling cannot be effectively controlled, the invention provides the comparator with the adjustable turning point, when an input signal is a current signal, the current signal is converted into a corresponding voltage signal and then input, the current signal is input, the current comparison function is realized, the comparator can be used as the current comparator of DCR sampling, an additional control current source is added on a tail current source, and the current comparator is linearly controlled to output the turning point; a current swing control system is added, so that the current swing of an output stage is not limited by the magnitude of tail current, and the static power consumption of the circuit can be reduced; the output end enables output current information to be converted into voltage information through a Trans-Impedance Amplifier (TIA) structure, and linear conversion of I-V is completed. Meanwhile, the comparator provided by the invention can also realize a voltage comparison function and directly compare the input voltage signals.
The technical scheme of the invention is as follows:
a comparator with an adjustable turning point comprises a comparison module and a transimpedance amplifier, wherein the comparison module comprises a first current source, a second current source, a third current source, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NPN triode, a second NPN triode, a first resistor, a second resistor, a third resistor and a fifth resistor,
the grid drain of the first NMOS tube is in short circuit connection with the first current source, the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube and is grounded; the second NMOS tube, the third NMOS tube and the fourth NMOS tube respectively form a current mirror structure with the first NMOS tube, and the current mirror structure is used for mirroring the current of the first current source to provide bias;
a base electrode of the first NPN type triode is used as a first input end of the comparator, a collector electrode of the first NPN type triode is connected with a grid electrode of the seventh NMOS tube and is connected with power voltage after passing through the first resistor, and an emitter electrode of the first NPN type triode is connected with the second current source, a drain electrode of the second NMOS tube and one end of the fifth resistor; a base electrode of the second NPN type triode is used as a second input end of the comparator, a collector electrode of the second NPN type triode is connected with a grid electrode of the eighth NMOS tube and is connected with power voltage after passing through the second resistor, and an emitter electrode of the second NPN type triode is connected with the third current source, a drain electrode of the third NMOS tube and the other end of the fifth resistor; adjusting the turning point of the comparator by adjusting the current values of the second current source and the third current source;
the grid-drain short circuit of the third PMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube, and the source electrode of the third PMOS tube is connected with the source electrode of the ninth NMOS tube after passing through a third resistor; the drain electrode of the first PMOS tube is connected with the grid electrode and the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the seventh NMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the sixth NMOS tube and serves as the output end of the comparison module, and the source electrode of the second PMOS tube is connected with the source electrode of the eighth NMOS tube; the grid electrode and the drain electrode of the ninth NMOS tube, the drain electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube are connected with a power supply voltage;
the trans-impedance amplifier is used for converting the signal at the output end of the comparison module into a differential voltage signal and then using the differential voltage signal as an output signal of the comparator.
Specifically, the transimpedance amplifier includes a first inverter and a fourth resistor, an input end of the first inverter is connected to one end of the fourth resistor and an output end of the comparison module and serves as a second output end of the comparator, an output end of the first inverter is connected to the other end of the fourth resistor and serves as a first output end of the comparator, and the first output end and the second output end of the comparator output the differential voltage signal as an output signal of the comparator.
Specifically, when the input signal of the comparator is a voltage signal, the input voltage signal is connected to the first input end and the second input end of the comparator, and the comparator completes a voltage comparison function; when the input signal of the comparator is a current signal, the input current signal is converted into a corresponding voltage signal and then is connected to the first input end and the second input end of the comparator, and the comparator completes the function of current comparison.
Specifically, the comparator is used as a current comparator for sampling a direct-current resistance of a switch power supply inductor, an inductor direct-current resistance sampling network of the switch power supply comprises an inductor, a capacitor, a sixth resistor and a seventh resistor, one end of the inductor is connected with one end of the sixth resistor and a connection point of an upper power tube and a lower power tube in the switch power supply, and the other end of the inductor is connected with one end of the seventh resistor; one end of the capacitor is connected with the other end of the sixth resistor and the first input end of the comparator, and the other end of the capacitor is connected with the other end of the seventh resistor, the output end of the switching power supply and the second input end of the comparator; the second current source in the comparator is the current containing the output voltage information of the switching power supply, and the current of the third current source is the current with a constant magnitude minus the current of the second current source.
Specifically, the mirror image ratio of the current mirror structure formed by the first NMOS transistor and the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor is 1: 1.
The invention has the beneficial effects that: the invention provides a comparator with an adjustable turning point, which is characterized in that a second current source and a third current source are added to a tail current source to serve as additional control current sources to realize the output of the turning point of a linear control comparator; the invention can realize voltage comparison and current comparison, and is particularly suitable for being used as a current comparator for DCR sampling; in addition, by adding a current swing control system consisting of a third PMOS tube MP3, a second PMOS tube MP2 and a first PMOS tube MP1, the current swing of an output stage is not limited by the magnitude of tail current, and the static power consumption of the circuit can be reduced; the output end enables output current information to be converted into voltage information through a transconductance amplifier TIA structure, and linear conversion of I-V is completed.
Drawings
Fig. 1 is a circuit structure diagram of a comparator with an adjustable turning point according to the present invention.
Fig. 2 is a schematic circuit diagram illustrating a current comparator in sampling of a switching power supply DCR in an embodiment of the present invention.
Fig. 3 is a schematic diagram of a simulation result when a comparator with an adjustable turning point provided by the present invention is used as a current comparator in sampling of a switching power supply DCR to perform transient simulation in an embodiment.
Fig. 4 is a schematic diagram of inductive dc resistance (DCR) sampling in a switching power supply.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
The comparator with the adjustable turning point comprises a comparison module and a transimpedance amplifier, wherein as shown in fig. 1, the comparison module comprises a first current source, a second current source, a third current source, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN5An NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NPN-type triode QN1, a second NPN-type triode QN2, a first resistor R1, a second resistor R2, a third resistor R3, and a fifth resistor R3OSThe gate drain of the first NMOS transistor MN1 is in short circuit and is connected with a first current source, the gate of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4, and the source electrode of the first NMOS transistor MN1 is connected with the source electrode of the second NMOS transistor MN2, the source electrode of the third NMOS transistor MN3, the source electrode of the fourth NMOS transistor MN4, the source electrode of the fifth NMOS transistor MN5 and the source electrode of the sixth NMOS transistor MN6 and is grounded; the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the first NMOS transistor MN1 respectively form a current mirror structure for converting the current I of the first current sourceREFMirroring to provide a bias; current I of the first current sourceREFThe bias current can be provided by a reference circuit, and the appropriate bias current can be provided for the whole circuit after the mirror image of the current mirror.
A base electrode of the first NPN transistor QN1 is used as a first input terminal of the comparator, a collector electrode thereof is connected to a gate electrode of the seventh NMOS transistor MN7 and is connected to the power supply voltage VDD through the first resistor R1, and an emitter electrode thereof is connected to the second current source, a drain electrode of the second NMOS transistor MN2, and the fifth resistor ROSOne end of (a); a base of the second NPN transistor QN2 is used as a second input terminal of the comparator, a collector thereof is connected to a gate of the eighth NMOS transistor MN8 and to the power supply voltage VDD through the second resistor R2, and an emitter thereof is connected to the third current source, a drain of the third NMOS transistor MN3, and the fifth resistor ROSThe other end of (a); and adjusting the turning point of the comparator by adjusting the current values of the second current source and the third current source.
Suppose a fifth resistance ROSCurrent at is IRFrom kirchhoff's law, the collector current I of the first NPN transistor QN1C1The size is as follows:
IC1＝IR+A1×IREF-I2 (1)
collector current I of second NPN type triode QN2C2The size is as follows:
IC2＝A2×IREF-I3-IR (2)
the mirror ratio of the current mirror formed by the first NMOS transistor MN1 and the second NMOS transistor MN2 is 1: A1, and the mirror ratio of the current mirror formed by the first NMOS transistor MN1 and the third NMOS transistor MN3 is 1: A2, IREFIs the current provided by the first current source, I2Is the current provided by the second current source, I3Is the current provided by the third current source.
The difference between the first input VP and the second input VN of the comparator is:
VP-VN＝VBE1-VBE2+IRROS (3)
Figure BDA0002781395210000041
VBE1、VBE2the base-emitter voltages of the first NPN transistor QN1 and the second NPN transistor QN2, respectively. The output state of the comparator can be considered to be turned over at the point IC1＝IC2Thus, it is possible to obtain:
Figure BDA0002781395210000042
when the mirror ratios of the current mirrors formed by the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 are equal, that is, a1 is equal to a2, the first term on the right side of the equation of formula (5)
Figure BDA0002781395210000043
Can be omitted, IROnly with the current value I of the second current source2A current value I of the third current source3In this regard, the trip point of the comparator may be adjusted by adjusting the current values of the second and third current sources. Even if A1 and A2 are not equal, the circuit is determined
Figure BDA0002781395210000044
Is also constant, and can be adjusted by adjusting I2And I3To adjust the trip point of the comparator.
The gate-drain short circuit of the third PMOS transistor MP3 is connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and the drain of the fourth NMOS transistor MN4, and the source thereof is connected to the source of the ninth NMOS transistor MN9 through the third resistor R3; the drain electrode of the first PMOS transistor MP1 is connected to the gate and drain electrode of the fifth NMOS transistor MN5 and the gate electrode of the sixth NMOS transistor MN6, and the source electrode thereof is connected to the source electrode of the seventh NMOS transistor MN 7; the drain electrode of the second PMOS transistor MP2 is connected to the drain electrode of the sixth NMOS transistor MN6 and serves as the output terminal of the comparison module, and the source electrode thereof is connected to the source electrode of the eighth NMOS transistor MN 8; the grid electrode and the drain electrode of the ninth NMOS transistor MN9, the drain electrode of the seventh NMOS transistor MN7 and the drain electrode of the eighth NMOS transistor MN8 are connected with a power supply voltage VDD.
The third PMOS transistor MP3 is used to provide a bias for the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 by respectively configuring a current mirror with the first PMOS transistor MP1 and the second PMOS transistor MP2, so as to prevent the drain of the fifth NMOS transistor MN5 from being directly connected to the source of the seventh NMOS transistor MN7, and also prevent the drain of the sixth NMOS transistor MN6 from being directly connected to the source of the eighth NMOS transistor MN8, which may not achieve the stability of the static operating point.
For convenience of analysis, the mirror ratios of the current mirror structures respectively formed by the first NMOS transistor MN1 and the second, third, and fourth NMOS transistors MN2, MN3, MN4 are all 1: 1. The gate voltage of the third PMOS transistor MP3 is: vG3＝VDD-IREFR3-VGS9+VDS3，VGS9Is the gate-source voltage, V, of the ninth NMOS transistor MN9DS3Is the drain-source voltage of the third PMOS transistor MP3, the gate voltage V of the third PMOS transistor MP3G3The first PMOS transistor MP1 and the second PMOS transistor MP2 can be biased in the saturation region. The current swing of the two branches of the seventh NMOS transistor MN7, the fifth NMOS transistor MN5, the eighth NMOS transistor MN8 and the sixth NMOS transistor MN6 is controlled by the first PMOS transistor MP1 and the second PMOS transistor MP2, so that the current swing of the output end of the comparator is not limited by the current magnitude of the tail current source. The mirror image ratio of the current mirror formed by the third PMOS transistor MP3, the first PMOS transistor MP1 and the second PMOS transistor MP2 cannot be too large, so that the mirror image current is close to the current swing without the MP1, MP2 and MP3 structures, and the effect of controlling the current swing is lost.
The transimpedance amplifier is configured to convert a signal at an output terminal of the comparing module into a differential voltage signal and then use the differential voltage signal as an output signal of the comparator, as shown in fig. 2, an implementation structure of the transimpedance amplifier TIA is provided, and includes a first inverter INV1 and a fourth resistor R4, an input terminal of the first inverter INV1 is connected to one end of the fourth resistor R4 and the output terminal of the comparing module and serves as a second output terminal VOUT2 of the comparator, an output terminal of the first inverter INV1 is connected to the other end of the fourth resistor R4 and serves as a first output terminal VOU1 of the comparator, and the differential voltage signal output by the first output terminal VOUT1 and the second output terminal VOUT2 of the comparator serves as an output signal of the comparator.
The TIA structure is configured by the first inverter INV1 and the fourth resistor R4 in this embodiment, current information output by the comparison module is converted into differential voltage information, and conversion from single-ended input to double-ended output is realized. Of course, other transimpedance amplifier configurations that are capable of performing this function are also suitable for use with the present invention.
The comparator provided by the invention can realize the functions of voltage comparison and current comparison, when the input signal of the comparator is a voltage signal, the input voltage signal is connected to the first input end VP and the second input end VN of the comparator, and the comparator completes the function of voltage comparison; when the input signal of the comparator is a current signal, the input current signal is converted into a corresponding voltage signal and then connected to the first input terminal VP and the second input terminal VN of the comparator, and the comparator performs a current comparison function.
Taking the comparator proposed by the present invention as a current comparator for sampling the inductor dc resistance (DCR sampling) in the switching power supply as an example, as shown in fig. 4, which is a DCR sampling schematic diagram of the switching power supply, the upper and lower power tubes S1 and S2 of the switching power supply are connected between the input voltage of the switching power supply and the ground, an inductor dc resistance sampling network is arranged between the connection point of S1 and S2 and the output end of the switching power supply, and the inductor dc resistance sampling network includes an inductor L and a capacitor CCA sixth resistor RCAnd a seventh resistor RDCROne end L of the inductor is connected with a sixth resistor RCOne end of the power supply is connected with the connection point of the upper power tube and the lower power tube in the switching power supply, and the other end of the power supply is connected with a seventh power tubeResistance RDCROne end of (a); capacitor CCIs connected with a sixth resistor RCAnd the other end of the comparator is connected with a first input end VP of the comparator, and the other end of the comparator is connected with a seventh resistor RDCRThe other end of the comparator, the output end of the switching power supply and a second input end VN of the comparator; as shown in fig. 2, the second current source of the comparator is configured to include the output voltage V of the switching power supply in this embodimentOUTCurrent I of informationTHCFor example, the output of the pre-stage error amplifier of the switching power supply is converted into a current containing output voltage information through the transconductance amplifier as the second current source, and the current of the third current source is set to be a constant current ICTMinus the current I of the second current sourceTHC。
The working process and principle of the current comparator for implementing DCR sampling of the switching power supply by the comparator in this embodiment are analyzed below.
The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 form a group of current mirror units for mirroring the current I of the first current sourceREFThe mirror current ratios are all 1:1, so that the analysis is convenient and the whole static power consumption of the circuit is convenient to control, IREFA bias current is provided to the current comparator. The first NPN tube QN1 and the second NPN tube QN2 are input pair tubes of the current comparator, the base electrode of the first NPN tube QN1 is the positive phase input end VP of the current comparator, and the base electrode is connected with the inductance sampling voltage V in the DCR sampling networkSENSEThe base of the second NPN tube QN2 is the inverting input terminal VN of the current comparator and is connected to the inductor sampling voltage V in the DCR sampling networkSENSEThe emitters of the two NPN transistors pass through a fifth resistor ROSConnecting; suppose a fifth resistance ROSCurrent at is IRFrom kirchhoff's law, the collector current I of the first NPN transistor QN1C1The size is as follows:
IC1＝IR+IREF-ITHC (6)
collector current I of second NPN type triode QN2C2The size is as follows:
IC2＝IREF-ICT+ITHC-IR (7)
the difference between the non-inverting input terminal VP and the inverting input terminal VN of the current comparator is:
VP-VN＝VBE1-VBE2+IRROS (8)
Figure BDA0002781395210000061
the output state of the current comparator can be considered to be in the turning point IC1＝IC2Thus, it is possible to obtain:
Figure BDA0002781395210000062
Figure BDA0002781395210000063
from the equation (11), the current comparator has a flip point represented by ITHCAnd ICTAnd current control presents a linear relation, so that the peak current of the inductor is linearly controlled by an error amplification value of feedback voltage in the switching power supply. The peak current magnitude of the DCR sampling is:
Figure BDA0002781395210000071
the simulation analysis of the current comparator circuit of this embodiment is performed, and a schematic diagram of a simulation result in the transient simulation is shown in fig. 3, where the simulation conditions are: VDD is a power supply voltage of 2.4V, VP is a direct current voltage of 2.6V, VN is a voltage source which rises linearly and falls linearly from 2V to 3V, the period is 5us, the rising time and the falling time are both 2.5us, IREFA fixed 10uA current source; i isCTIs a fixed 20uA current source; i isTHCThe current source is a linear rising and linear falling current source from 5uA to 15uA, the period is 6us, the rising time and the falling time are both 3us, and the resistor ROS＝3kΩ。
As can be seen from FIG. 3, from top to bottom, the voltage VOUT1 at the first output terminal of the current comparator, the voltages VN and VP at the two input terminals of the current comparator, and the collector current I at the two input terminals of the differential input stage of the current comparator are respectivelyC1And IC2Two additional currents I superposed on the tail current source of the differential input terminal of the current comparatorTHCAnd
Figure BDA0002781395210000072
at 21.5us, when the current comparator output VOUT1 toggles from low to high, the voltage difference between the VN and VP voltages is 9.75mV, and when I isC1＝IC2As can be seen from the formula (11),
Figure BDA0002781395210000073
as can be seen, at this time ITHC-ICTAnd/2 is 3.25 uA. 3.25uA × 3K Ω ═ 9.75 mV. The simulation result is consistent with the analysis result in the past, when ITHCAnd ICTThe current linearly controls the trip point of the comparator.
According to the above analysis, in the present embodiment, the comparator is used as a current comparator for DCR sampling, and an additional control current source, i.e. the second current source I, is added to the tail current source (i.e. the current mirror formed by the second NMOS transistor MN2 and the third NMOS transistor MN 3)THCAnd a third current source ICT-ITHCLinearly controlling the current comparator to output a turning point; a current swing control system consisting of a third PMOS tube MP3, a second PMOS tube MP2 and a first PMOS tube MP1 is additionally arranged, so that the current swing of an output stage is not limited by the magnitude of tail current, and the static power consumption of the circuit can be reduced; the output end enables output current information to be converted into voltage information through a TIA structure, and linear conversion of I-V is completed.
In the present embodiment, the comparator of the present invention is taken as a current comparator for DCR sampling as an example for explanation, but the present invention is also applicable to other situations that require extra current to control the output flip point of the comparator, and I needs to be matchedTHCAnd the control current is changed into the control current of other control comparator turning points. The above embodimentsThe present invention is illustrative only of the principles and utilities of the present invention and is not to be taken in a limiting sense. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (5)

1. A comparator with an adjustable turning point is characterized by comprising a comparison module and a transimpedance amplifier, wherein the comparison module comprises a first current source, a second current source, a third current source, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NPN triode, a second NPN triode, a first resistor, a second resistor, a third resistor and a fifth resistor,
the grid drain of the first NMOS tube is in short circuit connection with the first current source, the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube and is grounded; the second NMOS tube, the third NMOS tube and the fourth NMOS tube respectively form a current mirror structure with the first NMOS tube, and the current mirror structure is used for mirroring the current of the first current source to provide bias;
a base electrode of the first NPN type triode is used as a first input end of the comparator, a collector electrode of the first NPN type triode is connected with a grid electrode of the seventh NMOS tube and is connected with power voltage after passing through the first resistor, and an emitter electrode of the first NPN type triode is connected with the second current source, a drain electrode of the second NMOS tube and one end of the fifth resistor; a base electrode of the second NPN type triode is used as a second input end of the comparator, a collector electrode of the second NPN type triode is connected with a grid electrode of the eighth NMOS tube and is connected with power voltage after passing through the second resistor, and an emitter electrode of the second NPN type triode is connected with the third current source, a drain electrode of the third NMOS tube and the other end of the fifth resistor; adjusting the turning point of the comparator by adjusting the current values of the second current source and the third current source;
the grid-drain short circuit of the third PMOS tube is connected with the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the drain electrode of the fourth NMOS tube, and the source electrode of the third PMOS tube is connected with the source electrode of the ninth NMOS tube after passing through a third resistor; the drain electrode of the first PMOS tube is connected with the grid electrode and the drain electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the seventh NMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the sixth NMOS tube and serves as the output end of the comparison module, and the source electrode of the second PMOS tube is connected with the source electrode of the eighth NMOS tube; the grid electrode and the drain electrode of the ninth NMOS tube, the drain electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube are connected with a power supply voltage;
the trans-impedance amplifier is used for converting the signal at the output end of the comparison module into a differential voltage signal and then using the differential voltage signal as an output signal of the comparator.
2. The comparator with adjustable turning point according to claim 1, wherein the transimpedance amplifier includes a first inverter and a fourth resistor, an input terminal of the first inverter is connected to one end of the fourth resistor and an output terminal of the comparison module and serves as a second output terminal of the comparator, an output terminal of the first inverter is connected to the other end of the fourth resistor and serves as a first output terminal of the comparator, and the first output terminal and the second output terminal of the comparator output the differential voltage signal as the output signal of the comparator.
3. The comparator with adjustable turning point according to claim 1 or 2, characterized in that when the input signal of the comparator is a voltage signal, the input voltage signal is connected to the first input terminal and the second input terminal of the comparator, and the comparator performs a voltage comparison function; when the input signal of the comparator is a current signal, the input current signal is converted into a corresponding voltage signal and then is connected to the first input end and the second input end of the comparator, and the comparator completes the function of current comparison.
4. The comparator with the adjustable turning point according to claim 3, wherein the comparator is used as a current comparator for sampling the inductance direct-current resistance of the switching power supply, the inductance direct-current resistance sampling network of the switching power supply comprises an inductance, a capacitor, a sixth resistor and a seventh resistor, one end of the inductance is connected with one end of the sixth resistor and the connection point of the upper power tube and the lower power tube in the switching power supply, and the other end of the inductance is connected with one end of the seventh resistor; one end of the capacitor is connected with the other end of the sixth resistor and the first input end of the comparator, and the other end of the capacitor is connected with the other end of the seventh resistor, the output end of the switching power supply and the second input end of the comparator; the second current source in the comparator is the current containing the output voltage information of the switching power supply, and the current of the third current source is the current with a constant magnitude minus the current of the second current source.
5. The comparator with the adjustable turning point according to any one of claims 1, 2 or 4, wherein the mirror ratio of the current mirror structure formed by the first NMOS transistor and the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor is 1: 1.
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