CN109728799B - A kind of High Speed Analog latch - Google Patents
A kind of High Speed Analog latch Download PDFInfo
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- CN109728799B CN109728799B CN201910254789.6A CN201910254789A CN109728799B CN 109728799 B CN109728799 B CN 109728799B CN 201910254789 A CN201910254789 A CN 201910254789A CN 109728799 B CN109728799 B CN 109728799B
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Abstract
The present invention provides a kind of High Speed Analog latch, comprising: the first driving stage, the second driving stage, third driving stage and several load resistances；First load resistance and third load resistance are serially connected between the positive input and first port of the first driving stage, concatenate the 6th load resistance between the tie point between the first load resistance and third load resistance and the positive output end of the first driving stage；Second load resistance and the 4th load resistance are serially connected between the reverse input end and first port of the first driving stage, concatenate the 5th load resistance between the tie point between the second load resistance and the 4th load resistance and the inverse output terminal of the first driving stage；The output end of second driving stage and the output end of the first driving stage are connected by identical polarity；The output end of third driving stage and the input terminal of the first driving stage are connected by opposite polarity.The state latch of differential analog signal by a small margin may be implemented in the present invention, improves the speed of latch.
Description
Technical field
The present invention relates to integrated circuit fields, espespecially a kind of High Speed Analog latch realizes high speed difference analogue by a small margin
The state latch of signal.
Background technique
Latch can convert digital signal for the high-low voltage of input and store as a kind of memory device.Lock
Storage is a kind of bistable circuit, comprising two stable operating points, two stable states of corresponding latch, while also including
The operating point of one balance, is unstable state, and the voltage of two stable operating points and the voltage difference of matching point are lock
The steady state voltage of storage is poor, and the small-signal gain of matching point latch is defined as equilibrium state gain.When input voltage change,
Latch is transitioned into another stable operating point from a stable operating point, i.e. latch mode is overturn, to realize incoming level
It latches.In addition, latch will realize two stable operating points, need to meet locking condition, is usually that latch is required to have
Sufficiently large equilibrium state gain.
Latch is widely used in number and Analogous Integrated Electronic Circuits, and simplest latch is by two head and the tail in digital circuit
Connected phase inverter composition, expands the S-R latch having with clearing or set end on its basis.It applies in digital circuit
Latch, two stable operating point are power supply and ground voltage respectively, and voltage difference is very big between two stable operating points, are easy
Meet locking condition, the disadvantage is that very big input voltage is needed to change the overturning that could complete latch mode, for this reason,
The latch applied in digital circuit is difficult to be applied directly in analog circuit.
Simulation latch is to increase current source or resistance progress current limliting on the basis of digital latch, makes the steady of latch
State voltage difference reduces, and then so that latch state overturning required voltage is become smaller, while also improving the speed of latch, still
Bring risk is reduction of the equilibrium state gain of latch, there is the risk for being unsatisfactory for locking condition.For latch design
For, equilibrium state gain and steady state voltage difference are usually positively related.
Simulation latch is commonly used in current mode logic circuit.One basic simulation latch, as shown in figure 8, latching
The steady state voltage difference of device is by two NMOS tube equilibrium state mutual conductance gm, load resistance R(R1=R2=R) and bias current determine, i.e., it is full
The following relationship of foot:；In addition, latch also needs to meet the locking condition that equilibrium state gain is greater than 1:；Relation above illustrates small steady state voltage difference and big equilibrium state gain is conflicting.
Summary of the invention
The object of the present invention is to provide a kind of High Speed Analog latch, solve the steady state voltage difference and balance of simulation latch
Contradiction between state gain can according to need reduction and latch under the premise of offer meets the equilibrium state gain of locking condition
Input signal amplitude required for device is overturn realizes the state latch of differential analog signal by a small margin, to improve latch
Speed.
Technical solution provided by the invention is as follows:
A kind of High Speed Analog latch, comprising: the first driving stage is the driving circuit of a Differential Input, difference output；The
Two driving stages are the driving circuits of another Differential Input, difference output, the positive input of second driving stage and described
The positive output end of one driving stage is connected, the negative sense output of the negative input of second driving stage and first driving stage
End is connected, and the positive output end of second driving stage is connected with the positive output end of first driving stage, and described second drives
The negative sense output end of dynamic grade is connected with the negative sense output end of first driving stage；Third driving stage is another Differential Input, difference
Divide the driving circuit of output；The positive input of the third driving stage is connected with the positive output end of second driving stage,
The negative input of the third driving stage is connected with the negative sense output end of second driving stage, and the third driving stage is just
It is connected to output end with the negative input of first driving stage, the negative sense output end of the third driving stage and described first
The positive input of driving stage is connected；First load resistance, third load resistance and the 6th load resistance, the first load electricity
Resistance and the third load resistance are serially connected between the positive input and first port of first driving stage, and described first is negative
It carries described in being concatenated between tie point and the positive output end of first driving stage between resistance and the third load resistance
6th load resistance；Second load resistance, the 4th load resistance, the 5th load resistance, second load resistance and described
Four load resistances are serially connected between the reverse input end and the first port of first driving stage, second load resistance
It is negative that the described 5th is concatenated between tie point and the inverse output terminal of first driving stage between the 4th load resistance
Carry resistance.
It is further preferred that first driving stage includes the first field effect transistor and the second field effect transistor；Institute
Positive input of the grid of the first field effect transistor as first driving stage is stated, first field effect transistor
The negative sense output end to drain as first driving stage；The grid of second field effect transistor is as first driving
The negative input of grade, positive output end of the drain electrode of second field effect transistor as first driving stage；It is described
First field effect transistor and second field effect transistor are NMOS tube, or, first field effect transistor and described
Second field effect transistor is PMOS tube.
It is further preferred that the source electrode of the source electrode of first field effect transistor and second field effect transistor is total
With a port for being connected to the first current source；When first field effect transistor and second field effect transistor are
When NMOS tube, another port of first current source is connected to ground；Alternatively, when first field effect transistor and described
When second field effect transistor is PMOS tube, another port of first current source is connected to power supply.
It is further preferred that second driving stage includes third field effect transistor and the 4th field effect transistor；Institute
Negative input of the grid of third field effect transistor as second driving stage is stated, the third field effect transistor
The positive output end to drain as second driving stage；The grid of 4th field effect transistor is as second driving
The positive input of grade, negative sense output end of the drain electrode of the 4th field effect transistor as second driving stage；It is described
Third field effect transistor and the 4th field effect transistor are NMOS tube, or, the third field effect transistor and described
4th field effect transistor is PMOS tube.
It is further preferred that the source electrode of the source electrode of the third field effect transistor and the 4th field effect transistor is total
With a port for being connected to the second current source；When the third field effect transistor and the 4th field effect transistor are
When NMOS tube, another port of second current source is connected to ground；Alternatively, when the third field effect transistor and described
When 4th field effect transistor is PMOS tube, another port of second current source is connected to power supply.
It is further preferred that the third driving stage includes the 5th field effect transistor and the 6th field effect transistor；Institute
Negative input of the grid of the 5th field effect transistor as the third driving stage is stated, the 5th field effect transistor
The positive output end to drain as the third driving stage；The grid of 6th field effect transistor drives as the third
The positive input of grade, negative sense output end of the drain electrode of the 6th field effect transistor as the third driving stage；It is described
5th field effect transistor and the 6th field effect transistor are NMOS tube, or, the 5th field effect transistor and described
6th field effect transistor is PMOS tube.
It is further preferred that the source electrode of the 5th field effect transistor and the source electrode of the 6th field effect transistor are total
With a port for being connected to third current source；When the 5th field effect transistor and the 6th field effect transistor are
When NMOS tube, another port of the third current source is connected to ground；Alternatively, when the 5th field effect transistor and described
When 6th field effect transistor is PMOS tube, another port of the third current source is connected to power supply.
It is further preferred that the source electrode of the source electrode of the 5th field effect transistor and the 6th field effect transistor it
Between concatenate the first feedback resistance and the second feedback resistance；Tie point between first feedback resistance and the second feedback resistance with
The a port of 4th current source is connected；When the 5th field effect transistor and the 6th field effect transistor are NMOS tube
When, another port of the 4th current source is connected to ground；Alternatively, when the 5th field effect transistor and 6th described
When effect transistor is PMOS tube, another port of the 4th current source is connected to power supply.
It is further preferred that first driving stage includes the first bipolar transistor and the second bipolar transistor；Institute
Positive input of the base stage of the first bipolar transistor as first driving stage is stated, first bipolar transistor
Negative sense output end of the collector as first driving stage；The base stage of second bipolar transistor is driven as described first
The negative input of dynamic grade, positive output end of the collector of second bipolar transistor as first driving stage；
First bipolar transistor and second bipolar transistor are PNP transistor, or, first bipolar transistor
Pipe and second bipolar transistor are NPN transistor.
It is further preferred that the transmitting of the emitter of first bipolar transistor and second bipolar transistor
Pole is commonly connected to a port of the 5th current source；When first bipolar transistor and second bipolar transistor
When for NPN transistor, another port of the 5th current source is connected to ground；Alternatively, working as first bipolar transistor
When pipe and second bipolar transistor are PNP transistor, another port of the 5th current source is connected to power supply.
It is further preferred that second driving stage includes third bipolar transistor and the 4th bipolar transistor；Institute
Negative input of the base stage of third bipolar transistor as second driving stage is stated, the third bipolar transistor
Positive output end of the collector as second driving stage；The base stage of 4th bipolar transistor is driven as described second
The positive input of dynamic grade, negative sense output end of the collector of the 4th bipolar transistor as second driving stage；
The third bipolar transistor and the 4th bipolar transistor are PNP transistor, or, the third bipolar transistor
Pipe and the 4th bipolar transistor are NPN transistor.
It is further preferred that the transmitting of the emitter of the third bipolar transistor and the 4th bipolar transistor
Pole is commonly connected to a port of the 6th current source；When the third bipolar transistor and the 4th bipolar transistor
When for NPN transistor, another port of the 6th current source is connected to ground；Alternatively, working as the third bipolar transistor
When pipe and the 4th bipolar transistor are PNP transistor, another port of the 6th current source is connected to power supply.
It is further preferred that the third driving stage includes the 5th bipolar transistor and the 6th bipolar transistor；Institute
Negative input of the base stage of the 5th bipolar transistor as the third driving stage is stated, the 5th bipolar transistor
Positive output end of the collector as the third driving stage；The base stage of 6th bipolar transistor is driven as the third
The positive input of dynamic grade, negative sense output end of the collector of the 6th bipolar transistor as the third driving stage；
5th bipolar transistor and the 6th bipolar transistor are PNP transistor, or, the 5th bipolar transistor
Pipe and the 6th bipolar transistor are NPN transistor.
It is further preferred that the transmitting of the emitter and the 6th bipolar transistor of the 5th bipolar transistor
Pole is commonly connected to a port of the 7th current source；When the 5th bipolar transistor and the 6th bipolar transistor
When for NPN transistor, another port of the 7th current source is connected to ground；Alternatively, working as the 5th bipolar transistor
When pipe and the 6th bipolar transistor are PNP transistor, another port of the 7th current source is connected to power supply.
It is further preferred that the transmitting of the emitter of the 5th bipolar transistor and the 6th bipolar transistor
Third feedback resistance and the 4th feedback resistance are concatenated between pole；Connection between the third feedback resistance and the 4th feedback resistance
Point is connected with a port of the 8th current source；When the 5th bipolar transistor and the 6th bipolar transistor are
When NPN transistor, another port of the 8th current source is connected to ground；Alternatively, working as the 5th bipolar transistor
With the 6th bipolar transistor be PNP transistor when, another port of the 8th current source is connected to power supply.
It is further preferred that first load resistance is identical with the resistance value of second load resistance；And/or it is described
Third load resistance is identical with the resistance value of the 4th load resistance；And/or the 5th load resistance and the described 6th loads
The resistance value of resistance is identical；And/or the resistance value of the third load resistance is 0；And/or the resistance value of the 4th load resistance is
0。
A kind of High Speed Analog latch provided through the invention, can bring it is following the utility model has the advantages that
By the way that the output end of the second driving stage and the output end of the first driving stage are connected by identical polarity, make the first drive
Dynamic grade output electric current and the second driving stage export current in phase, increase latch equilibrium state gain；It crosses third driving stage
Output end and the output end of the first driving stage are connected to the same point by opposite polarity, make the first driving stage output electric current and the
Two driving stages export anti-phase, in the case where not changing latch equilibrium state gain, can reduce the stable state electricity of latch
Pressure difference reduces the input voltage size that latch overturning needs, to eliminate latch overturning desired signal amplitude size and lock
Contradiction between the equilibrium state gain of storage；To reduce input as needed in the case where not reducing the equilibrium state gain of latch
The amplitude requirement of signal makes the time of node charge and discharge shorten, and power consumption is lower, and the reaction speed of latch is faster.
Detailed description of the invention
Below by clearly understandable mode, preferred embodiment is described with reference to the drawings, to a kind of High Speed Analog latch
Above-mentioned characteristic, technical characteristic, advantage and its implementation be further described.
Fig. 1 is a kind of circuit diagram of one embodiment of High Speed Analog latch of the invention；
Fig. 2 is a kind of circuit diagram of another embodiment of High Speed Analog latch of the invention；
Fig. 3 is a kind of circuit diagram of another embodiment of High Speed Analog latch of the invention；
Fig. 4 is a kind of circuit diagram of another embodiment of High Speed Analog latch of the invention；
Fig. 5 is a kind of circuit diagram of another embodiment of High Speed Analog latch of the invention；
Fig. 6 is a kind of circuit diagram of another embodiment of High Speed Analog latch of the invention；
Fig. 7 is a kind of circuit diagram of another embodiment of High Speed Analog latch of the invention；
Fig. 8 is a kind of circuit diagram of basic simulation latch.
Specific embodiment
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, Detailed description of the invention will be compareed below
A specific embodiment of the invention.It should be evident that drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, and obtain other embodiments.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, there is identical structure or function in some figures so that simplified form is easy to understand
Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated
" only this ", can also indicate the situation of " more than one ".
Embodiment 1
As shown in Figure 1, a kind of circuit diagram of High Speed Analog latch, including load resistance R1 ~ R6, the first driving
Grade, the second driving stage and third driving stage, wherein the forward direction that load resistance R1 and load resistance R3 is serially connected in the first driving stage is defeated
Enter between end and first port, the positive output end of tie point and the first driving stage between load resistance R1 and load resistance R3
Between concatenate load resistance R6；Load resistance R2 and load resistance R4 is serially connected in the reverse input end and first end of the first driving stage
Between mouthful, load is concatenated between the tie point and the inverse output terminal of the first driving stage between load resistance R2 and load resistance R4
Resistance R5；The input terminal of second driving stage and the output end of the first driving stage are connected by identical polarity, the second driving stage it is defeated
Outlet is connected with the output end of the first driving stage by identical polarity；The output of the input terminal of third driving stage and the second driving stage
End is connected by identical polarity, and the input terminal of the output end of third driving stage and the first driving stage is connected by opposite polarity；Section
Point A and B constitutes a pair of of differential input signal, and node E and F constitute a pair of of differential output signal.The simulation latch is by the difference
Input signal carries out positive feedback and latches to obtain the differential output signal.
Specifically, the first driving stage, the second driving stage and third driving stage can be Differential Input, difference output it is any
Driving circuit, such as the NMOS conventional differential input pair that perhaps PMOS is constituted or by NPN type or positive-negative-positive bipolar transistor structure
At conventional differential input pair or common source input two NMOS or two PMOS constitute Differential Input pair, Huo Zheyuan
NMOS the PMOS Differential Input equity of pole series resistor feedback.Each stage drive circuit can choose different types of circuit knot
Structure, such as the conventional differential input that is constituted using two NMOS of the first driving stage use two bipolar npns to, the second driving stage
Property the conventional differential input that constitutes of transistor Differential Input that, third driving stage is constituted using two NMOS of common source input
It is right, with specific reference to being selected.The field-effect tube using same type is needed in same driving stage, for example is all
NMOS, or be all the bipolar transistor of PMOS or same type.
The type and resistance value of load resistance R1, R2, R3, R4, R5, R6 between any two can be same or different, and first
The electrical parameter of the electrical parameter of driving stage, the electrical parameter of the second driving stage and third driving stage between any two can be identical
Or it is different.
Resistance sizes of the steady state voltage difference of latch by load resistance R1 ~ R6, the first driving stage, the second driving stage and
The electrical parameter (bias current, mutual conductance) of three driving stages determines.
Because the output end of the second driving stage and the output end of the first driving stage are connected by identical polarity, i.e. the second driving stage
Positive output end be connected with the positive output end of the first driving stage, the negative sense output end of the second driving stage and the first driving stage
Negative sense output end is connected, so the output current in phase of the output electric current and the second driving stage of the first driving stage, after electric current is added
Separately flow into the resistance string of load resistance R2 and load resistance R5 composition and the electricity of load resistance R1 and load resistance R6 composition
Resistance string.
As shown in Figure 1, the negative sense output end of third driving stage is connected to C point through load resistance R3, the first driving stage is just
It is connected to C point through load resistance R6 to output end, the two is that the same point C is connected to by opposed polarity；Third driving stage is just
D point is connected to through load resistance R4 to output end, the negative sense output end of the first driving stage is connected to D point through load resistance R5, and two
Person is that the same point D is connected to by opposed polarity；So the output electric current of the output electric current and the first driving stage of third driving stage
It is that reverse phase is flowed into the same point, load resistance R1 and R2 is separately flowed into after current subtraction.
The equilibrium state gain of latch is related to the voltage difference of node D to latch mode lower node C, and the voltage difference is bigger,
Equilibrium state gain is bigger.The steady state voltage difference of latch is related to the voltage difference of node B to latch mode lower node A, the voltage
Difference is smaller, and steady state voltage difference is smaller, and the input signal amplitude that latch overturning needs is smaller.Since the first driving stage exports electric current
(i1) and the second driving stage output electric current (i2) same phase and third driving stage export electric current (i3) reverse phase, guarantee the by design
One driving stage exports the sum of electric current and the second driving stage output electric current and is greater than third driving stage output electric current (since i2 and i1 are same
Phase, (i1+i2) > i3 easy to accomplish), the size of current on load resistance R1 and load resistance R2 is i1+i2-i3, thus C and D
Voltage difference are as follows: (i1+i2-i3) * (R1+R2)；Size of current on load resistance R3 and R4 is i3, thus the voltage difference of A and B is real
It is pressure drop of the C and D voltage difference superimposed current i3 on R3 and R4 on border, i.e., A and B voltage difference is (i1+i2-i3) * (R1+R2)-
I3*(R3+R4).It is derived from front it is found that making the voltage difference of A and B be less than the voltage of C and D under the action of third driving stage
Difference, so that latch be made to be easier to overturn.It, can be with by adjusting the electrical parameter and load resistance R3, R4 of third driving stage
In the case where not concept transfer C and node D voltage difference the equilibrium state gain of latch (be equivalent to do not reduce), further decrease
Voltage difference between node A and node B reduces the input voltage size that latch overturning needs, to improve the speed of latch
Degree.
The equilibrium state gain of traditional analog latch shown in Fig. 8, steady state voltage difference all with the voltage difference phase of A, B two o'clock
It closes, when equilibrium state gain is big, steady state voltage difference is also big；And the steady state voltage difference and A, B two of simulation latch provided by the invention
The voltage difference of point is related, and equilibrium state gain is related to the voltage difference of C, D two o'clock, and the two can be adjusted respectively, so lock can be eliminated
Storage overturns the contradiction between desired signal amplitude size and equilibrium state gain.
The polarity of the input terminal of each driving stage, is reversely exchanged that (former positive input becomes by the deformation 1 of the present embodiment
Negative input, former negative input become positive input) and the polarity of corresponding output end also makees reversed exchange (former negative sense is defeated
Outlet becomes positive output end, and former forward direction output end becomes negative sense output end), obtained circuit can also complete the present embodiment
Function.
The resistance value of load resistance R3 and/or load resistance R4 are set as 0 by the deformation 2 of the present embodiment, this is requiring not to be very
High scene, for example guarantee the equilibrium state gain of latch, but the input voltage amplitude requirement that latch overturning needs is less low
In the case where, it can still apply.
The latch cicuit that the present embodiment proposes eliminates the balance of latch overturning desired signal amplitude size and latch
Contradiction between state gain reduces the amplitude requirement of input signal, and the time of node charge and discharge shortens, and makes low in energy consumption, latch
The speed of device is faster.
Embodiment 2
As shown in Fig. 2, a kind of High Speed Analog latch, wherein the first driving stage, the second driving stage and third driving stage by
Basic NMOS differential is to realization, on the basis of embodiment 1, the differential pair of NMOS tube MN1, MN2 and bias current IB1 composition
As the first driving stage, the differential pair of NMOS tube MN3, MN4 and bias current IB2 composition is as the second driving stage, NMOS tube
The differential pair of MN5, MN6 and bias current IB3 composition is as third driving stage；First port is power supply；The MN1 of first driving stage
It is connected with the source electrode of MN2, is connected to the first port of current source IB1, the second port ground connection of current source IB1；Second driving stage
MN3 be connected with the source electrode of MN4, be connected to the first port of current source IB2, the second port ground connection of IB2；Third driving stage
MN5 is connected with the source electrode of MN6, is connected to the first port of current source IB3, the second port ground connection of IB3.
Specifically, the type and resistance value of load resistance R1, R2, R3, R4, R5, R6 between any two can be identical or not
Together, if load resistance R1 and R2 is unequal or load resistance R3 and R4 is unequal or load resistance R5 and R6 is unequal, two
A stable operating point can be different relative to the voltage difference of matching point.The electrical parameter of first driving stage, the second driving
The electrical parameter and the electrical parameter of third driving stage of grade may be the same or different between any two, such as bias current IB1,
IB2 and IB3 size of current can be same or different, and the design parameter (breadth length ratio etc.) of the NMOS tube of each driving stage can be identical
Or it is different.If two NMOS tube MN1 and MN2 design parameters of the first driving stage are different or two of the second driving stage
NMOS tube MN3 and MN4 design parameter is different or two NMOS tube MN5 and MN6 design parameters of third driving stage are different
Sample, then two stable operating points can be different relative to the voltage difference of matching point.If load resistance R1 and R2 is equal,
And/or load resistance R3 and R4 is equal and/or load resistance R5 and R6 is equal, can simplify circuit design.
The output current in phase of the output electric current and the second driving stage of first driving stage, electric current separately flow into load after being added
The resistance string of resistance R2 and load resistance R5 composition and the resistance string of load resistance R1 and load resistance R6 composition.Third is driven
The output anti-phase of the output electric current and the first driving stage of grade is moved, separately flows into load resistance R1 and R2 after current subtraction.By
In the output electric current of the first driving stage and the output current polarity of third driving stage on the contrary, under latch mode, node C and node D
Between voltage difference be greater than voltage difference between node A and node B, and the electricity ginseng for adjusting third driving stage can be passed through
Number, the voltage difference between node A and B is adjusted such as the mutual conductance of MN5 and MN6, bias current IB3 and resistance R3 and R4；Section
The equilibrium state gain of the voltage difference and latch of point C and node D is positively correlated, the input voltage width that latch state overturning needs
Degree and voltage difference between node A, B are related.By adjusting the electrical parameter and load resistance R3 and R4 of third driving stage,
Make the voltage difference of node A and node B be less than node C and node D voltage difference, get rid of latch overturning required input voltage and
Restriction relation between equilibrium state gain.
Embodiment 3
As shown in figure 3, a kind of High Speed Analog latch, the difference with embodiment 3 are, the first driving stage, the second driving
Bias current sources are not included in grade, third driving stage, the common end of driving stage is directly grounded, i.e. the source of the MN1 of the first driving stage
Pole is connected and is grounded with the source electrode of MN2, and the source electrode of the MN3 of the second driving stage is connected and is grounded with the source electrode of MN4, third driving stage
The source electrode of MN5 be connected and be grounded with the source electrode of MN6.Latch shown in Fig. 3 is as the working principle of latch shown in Fig. 2.
Embodiment 4
As shown in figure 4, a kind of High Speed Analog latch, wherein the first driving stage and the second driving stage are by basic NMOS differential
To realization, third driving stage is characterized in particular in realization, the circuit and the difference of embodiment 3 by the NMOS differential that strip resistance is fed back:
Third driving stage is by two NMOS tubes MN5 and MN6, the first feedback resistance R7, the second feedback resistance R8 and biasing
The grid of electric current IB4 composition, MN5 and MN6 are two input terminals of third driving stage, are drained as two outputs of third driving stage
End, MN5 are connected with the first end of the first feedback resistance R7 with the first end of the second feedback resistance R8 respectively with the source electrode of MN6.The
The first end of the second end and current source IB4 of the second end of one feedback resistance R7 and the second feedback resistance R8 is connected, current source
The second end of IB4 is connected to ground.Latch shown in Fig. 4 is similar with latch working principle shown in Fig. 2, latch shown in Fig. 4
Third driving stage mutual conductance is smaller, and the linearity is more preferable, facilitates the steady state voltage for adjusting latch poor.
The deformation 1 of the present embodiment, by the source electrode of two NMOS tubes MN5 and MN6 respectively with the first feedback resistance R7 first
End is connected with the first end of the second feedback resistance R8, the second end of the second end of the first feedback resistance R7 and the second feedback resistance R8
It is commonly connected to ground.
The deformation 2 of the present embodiment, as shown in figure 5, by the source electrode of two NMOS tubes MN5 and MN6 respectively with two current sources
First end connection, the second end of the two current sources is commonly connected to ground, and the first end of the two current sources is also respectively with one
The first end and second end of a resistance are connected.
Embodiment 5
As shown in fig. 6, a kind of High Speed Analog latch, wherein the first driving stage, the second driving stage and third driving stage by
Basic PMOS differential pair realizes that on the basis of embodiment 1, the differential pair of PMOS tube MP1, MP2 and bias current IB1 composition is made
For the first driving stage, the differential pair of PMOS tube MP3, MP4 and bias current IB2 composition as the second driving stage, PMOS tube MP5,
The differential pair of MP6 and bias current IB3 composition is as third driving stage；First port is ground；The MP1 and MP2 of first driving stage
Source electrode be connected, be connected to the first port of current source IB1, the second port of current source IB1 connects power supply；Second driving stage
MP3 is connected with the source electrode of MP4, is connected to the first port of current source IB2, and the second port of current source IB2 connects power supply；Third is driven
The source electrode of the MP5 and MP6 of dynamic grade are connected, and are connected to the first port of current source IB3, the second port of current source IB3 connects power supply.
Wherein, the type and resistance value of load resistance R1, R2, R3, R4, R5, R6 between any two can be same or different,
If load resistance R1 and R2 is unequal or load resistance R3 and R4 is unequal or load resistance R5 and R6 is unequal, two steady
Determining operating point can be different relative to the voltage difference of matching point.The electrical parameter of first driving stage, second driving stage
Electrical parameter and the electrical parameter of third driving stage between any two can be same or different, such as bias current IB1, IB2 and
IB3 size of current is same or different, and the design parameter (breadth length ratio etc.) of the PMOS tube of each driving stage can be same or different.
If two PMOS tube MP1 and MP2 design parameters of the first driving stage are different or two PMOS tube MP3 of the second driving stage
With MP4 design parameter is different or two PMOS tube MP5 and MP6 design parameters of third driving stage are different, then two it is steady
Determining operating point can be different relative to the voltage difference of matching point.If load resistance R1 and R2 be equal and/or load resistance
R3 and R4 is equal and/or load resistance R5 and R6 is equal, can simplify circuit design.
Latch shown in fig. 6 is identical as the working principle of latch shown in Fig. 2.
The source electrode of the MP1 of first driving stage and MP2 is commonly connected to power vd D by the deformation 1 of the present embodiment, and second drives
The source electrode of the MP3 and MP4 of dynamic grade are commonly connected to power vd D, and the source electrode of the MP5 and MP6 of third driving stage are commonly connected to electricity
Source VDD, other are identical as the present embodiment.Herein on the basis of deformation 1, by the source electrode of the MP5 of third driving stage and MP6 respectively with two
The first port of a feedback resistance is connected, and the second port of the two feedback resistances is commonly connected to power vd D, obtains another
Deformation.
The deformation 2 of the present embodiment, by the source electrode of the MP5 of third driving stage and MP6 respectively with two feedback resistances first
Port is connected, and the second port of the two feedback resistances is commonly connected to a port of current source IB3, and current source IB3's is another
A port is connected to power vd D.
The deformation 3 of the present embodiment, by the source electrode of the MP5 of the third driving stage and MP6 first end with two current sources respectively
Connection, the second end of the two current sources is commonly connected to power supply, the first end of the two current sources respectively with resistance
First end, second end are connected.
Embodiment 6
As shown in fig. 7, the difference of a kind of High Speed Analog latch and embodiment 3 is, the first driving stage, the second driving
Grade and third driving stage are that two bipolar transistors are realized, are realized by basic NPN differential pair, other working principles are the same.NPN
The differential pair of pipe NP1, NP2 and bias current IB5 composition is as the first driving stage, NPN pipe NP3, NP4 and bias current IB6 group
At differential pair as the second driving stage, the differential pair of NPN pipe NP5, NP6 and bias current IB7 composition is as third driving stage；
First port is power supply；The emitter of the NP1 and NP2 of first driving stage are connected, and are connected to the first port of current source IB5, electricity
The second port of stream source IB5 is grounded；The emitter of the NP3 and NP4 of second driving stage are connected, and are connected to the first of current source IB6
Port, the second port ground connection of IB6；The emitter of the NP5 and NP6 of third driving stage are connected, and are connected to the first of current source IB7
Port, the second port ground connection of IB7.
The emitter of each driving stage is commonly connected to ground by the deformation 1 of the present embodiment.It, will herein on the basis of deformation 1
The emitter of the NP5 and NP6 of third driving stage are connected with the first port of two feedback resistances respectively, the two feedback resistances
Second port is commonly connected to ground, obtains another deformation.
The deformation 2 of the present embodiment, by the emitter of the NP5 of third driving stage and NP6 respectively with two feedback resistance (thirds
Feedback resistance and the 4th feedback resistance) first port be connected, the second port of the two feedback resistances is commonly connected to the 8th
Another port of a port of current source, the current source is connected to ground.
The deformation 3 of the present embodiment, the first driving stage, the second driving stage and third driving stage can be by basic PN P differential pairs
It realizes, the emitter of each driving stage can be commonly connected to power supply or the emitter of each driving stage is commonly connected to electric current
Another port of a port in source, the current source is connected to power supply.
It should be noted that above-described embodiment can be freely combined as needed, every kind of load electricity in above-described embodiment
The number of resistance and feedback resistance is only example, for example, the first load resistance is indicated with R1, it is practical to realize first with multiple resistance
The function of load resistance is also possible.The above is only a preferred embodiment of the present invention, it is noted that for this technology
For the those of ordinary skill in field, various improvements and modifications may be made without departing from the principle of the present invention, this
A little improvements and modifications also should be regarded as protection scope of the present invention.
Claims (16)
1. a kind of High Speed Analog latch characterized by comprising
First driving stage is the driving circuit of a Differential Input, difference output；
Second driving stage is the driving circuit of another Differential Input, difference output；The positive input of second driving stage and
The positive output end of first driving stage is connected, the negative input of second driving stage and first driving stage it is negative
It is connected to output end, the positive output end of second driving stage is connected with the positive output end of first driving stage, described
The negative sense output end of second driving stage is connected with the negative sense output end of first driving stage；
Third driving stage is the driving circuit of another Differential Input, difference output；The positive input of the third driving stage and
The positive output end of second driving stage is connected, the negative input of the third driving stage and second driving stage it is negative
It is connected to output end, the positive output end of the third driving stage is connected with the negative input of first driving stage, described
The negative sense output end of third driving stage is connected with the positive input of first driving stage；
First load resistance, third load resistance and the 6th load resistance, first load resistance and third load electricity
Resistance is serially connected between the positive input and first port of first driving stage, and first load resistance and the third are negative
It carries and concatenates the 6th load resistance between tie point and the positive output end of first driving stage between resistance；
Second load resistance, the 4th load resistance, the 5th load resistance, second load resistance and the 4th load resistance
It is serially connected between the reverse input end and the first port of first driving stage, second load resistance and the described 4th
The 5th load resistance is concatenated between tie point and the inverse output terminal of first driving stage between load resistance.
2. High Speed Analog latch according to claim 1, it is characterised in that:
First driving stage includes the first field effect transistor and the second field effect transistor；
Positive input of the grid of first field effect transistor as first driving stage, first field-effect are brilliant
Negative sense output end of the drain electrode of body pipe as first driving stage；
Negative input of the grid of second field effect transistor as first driving stage, second field-effect are brilliant
Positive output end of the drain electrode of body pipe as first driving stage；
First field effect transistor and second field effect transistor are NMOS tube, or, first field effect transistor
Pipe and second field effect transistor are PMOS tube.
3. High Speed Analog latch according to claim 2, it is characterised in that:
The source electrode of the source electrode of first field effect transistor and second field effect transistor is commonly connected to the first electric current
The a port in source；
When first field effect transistor and second field effect transistor are NMOS tube, first current source it is another
A port is connected to ground；
Alternatively,
When first field effect transistor and second field effect transistor are PMOS tube, first current source it is another
A port is connected to power supply.
4. High Speed Analog latch according to claim 1, it is characterised in that:
Second driving stage includes third field effect transistor and the 4th field effect transistor；
Negative input of the grid of the third field effect transistor as second driving stage, the third field-effect are brilliant
Positive output end of the drain electrode of body pipe as second driving stage；
Positive input of the grid of 4th field effect transistor as second driving stage, the 4th field-effect are brilliant
Negative sense output end of the drain electrode of body pipe as second driving stage；
The third field effect transistor and the 4th field effect transistor are NMOS tube, or, the third field effect transistor
Pipe and the 4th field effect transistor are PMOS tube.
5. High Speed Analog latch according to claim 4, it is characterised in that:
The source electrode of the source electrode of the third field effect transistor and the 4th field effect transistor is commonly connected to the second electric current
The a port in source；
When the third field effect transistor and the 4th field effect transistor are NMOS tube, second current source it is another
A port is connected to ground；
Alternatively,
When the third field effect transistor and the 4th field effect transistor are PMOS tube, second current source it is another
A port is connected to power supply.
6. High Speed Analog latch according to claim 1, it is characterised in that:
The third driving stage includes the 5th field effect transistor and the 6th field effect transistor；
Negative input of the grid of 5th field effect transistor as the third driving stage, the 5th field-effect are brilliant
Positive output end of the drain electrode of body pipe as the third driving stage；
Positive input of the grid of 6th field effect transistor as the third driving stage, the 6th field-effect are brilliant
Negative sense output end of the drain electrode of body pipe as the third driving stage；
5th field effect transistor and the 6th field effect transistor are NMOS tube, or, the 5th field effect transistor
Pipe and the 6th field effect transistor are PMOS tube.
7. High Speed Analog latch according to claim 6, it is characterised in that:
The source electrode of 5th field effect transistor and the source electrode of the 6th field effect transistor are commonly connected to third electric current
The a port in source；
When the 5th field effect transistor and the 6th field effect transistor are NMOS tube, the third current source it is another
A port is connected to ground；
Alternatively,
When the 5th field effect transistor and the 6th field effect transistor are PMOS tube, the third current source it is another
A port is connected to power supply.
8. High Speed Analog latch according to claim 6, it is characterised in that:
The first feedback electricity is concatenated between the source electrode of 5th field effect transistor and the source electrode of the 6th field effect transistor
Resistance and the second feedback resistance；
Tie point between first feedback resistance and the second feedback resistance is connected with a port of the 4th current source；
When the 5th field effect transistor and the 6th field effect transistor are NMOS tube, the 4th current source it is another
A port is connected to ground；
Alternatively,
When the 5th field effect transistor and the 6th field effect transistor are PMOS tube, the 4th current source it is another
A port is connected to power supply.
9. High Speed Analog latch according to claim 1, it is characterised in that:
First driving stage includes the first bipolar transistor and the second bipolar transistor；
Positive input of the base stage of first bipolar transistor as first driving stage, first bipolarity are brilliant
Negative sense output end of the collector of body pipe as first driving stage；
Negative input of the base stage of second bipolar transistor as first driving stage, second bipolarity are brilliant
Positive output end of the collector of body pipe as first driving stage；
First bipolar transistor and second bipolar transistor are PNP transistor, or, first bipolarity
Transistor and second bipolar transistor are NPN transistor.
10. High Speed Analog latch according to claim 9, it is characterised in that:
The emitter of the emitter of first bipolar transistor and second bipolar transistor is commonly connected to the 5th
The a port of current source；
When first bipolar transistor and second bipolar transistor are NPN transistor, the 5th electric current
Another port in source is connected to ground；
Alternatively,
When first bipolar transistor and second bipolar transistor are PNP transistor, the 5th electric current
Another port in source is connected to power supply.
11. High Speed Analog latch according to claim 1, it is characterised in that:
Second driving stage includes third bipolar transistor and the 4th bipolar transistor；
Negative input of the base stage of the third bipolar transistor as second driving stage, the third bipolarity are brilliant
Positive output end of the collector of body pipe as second driving stage；
Positive input of the base stage of 4th bipolar transistor as second driving stage, the 4th bipolarity are brilliant
Negative sense output end of the collector of body pipe as second driving stage；
The third bipolar transistor and the 4th bipolar transistor are PNP transistor, or, the third bipolarity
Transistor and the 4th bipolar transistor are NPN transistor.
12. High Speed Analog latch according to claim 11, it is characterised in that:
The emitter of the emitter of the third bipolar transistor and the 4th bipolar transistor is commonly connected to the 6th
The a port of current source；
When the third bipolar transistor and the 4th bipolar transistor are NPN transistor, the 6th electric current
Another port in source is connected to ground；
Alternatively,
When the third bipolar transistor and the 4th bipolar transistor are PNP transistor, the 6th electric current
Another port in source is connected to power supply.
13. High Speed Analog latch according to claim 1, it is characterised in that:
The third driving stage includes the 5th bipolar transistor and the 6th bipolar transistor；
Negative input of the base stage of 5th bipolar transistor as the third driving stage, the 5th bipolarity are brilliant
Positive output end of the collector of body pipe as the third driving stage；
Positive input of the base stage of 6th bipolar transistor as the third driving stage, the 6th bipolarity are brilliant
Negative sense output end of the collector of body pipe as the third driving stage；
5th bipolar transistor and the 6th bipolar transistor are PNP transistor, or, the 5th bipolarity
Transistor and the 6th bipolar transistor are NPN transistor.
14. High Speed Analog latch according to claim 13, it is characterised in that:
The emitter of 5th bipolar transistor and the emitter of the 6th bipolar transistor are commonly connected to the 7th
The a port of current source；
When the 5th bipolar transistor and the 6th bipolar transistor are NPN transistor, the 7th electric current
Another port in source is connected to ground；
Alternatively,
When the 5th bipolar transistor and the 6th bipolar transistor are PNP transistor, the 7th electric current
Another port in source is connected to power supply.
15. High Speed Analog latch according to claim 13, it is characterised in that:
It is anti-that third is concatenated between the emitter of 5th bipolar transistor and the emitter of the 6th bipolar transistor
Feed resistance and the 4th feedback resistance；
Tie point between the third feedback resistance and the 4th feedback resistance is connected with a port of the 8th current source；
When the 5th bipolar transistor and the 6th bipolar transistor are NPN transistor, the 8th electric current
Another port in source is connected to ground；
Alternatively,
When the 5th bipolar transistor and the 6th bipolar transistor are PNP transistor, the 8th electric current
Another port in source is connected to power supply.
16. High Speed Analog latch described in any one according to claim 1, it is characterised in that:
First load resistance is identical with the resistance value of second load resistance；
And/or
The third load resistance is identical with the resistance value of the 4th load resistance；
And/or
5th load resistance is identical with the resistance value of the 6th load resistance；
And/or
The resistance value of the third load resistance is 0；
And/or
The resistance value of 4th load resistance is 0.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101753117A (en) * | 2008-12-16 | 2010-06-23 | 晨星软件研发(深圳)有限公司 | Delay unit in ring oscillator and correlation method thereof |
| CN202750074U (en) * | 2012-04-20 | 2013-02-20 | 西安华迅微电子有限公司 | High-speed comparator |
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| JP3998553B2 (en) * | 2002-09-30 | 2007-10-31 | Ｎｅｃエレクトロニクス株式会社 | Differential output circuit and circuit using the same |
| CN102789255B (en) * | 2012-07-18 | 2014-06-25 | 天津大学 | Turn-threshold-adjustable under voltage lockout (UVLO) and reference voltage circuit |
| WO2016197153A1 (en) * | 2015-06-05 | 2016-12-08 | Hassan Ihs | Fast pre-amp latch comparator |
| CN109102834B (en) * | 2018-06-21 | 2020-12-01 | 普冉半导体(上海)股份有限公司 | Data latch circuit, page data latch and method for flash memory page programming |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101753117A (en) * | 2008-12-16 | 2010-06-23 | 晨星软件研发(深圳)有限公司 | Delay unit in ring oscillator and correlation method thereof |
| CN202750074U (en) * | 2012-04-20 | 2013-02-20 | 西安华迅微电子有限公司 | High-speed comparator |
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