CN110069857B - Memristor based on negative resistance control - Google Patents
Memristor based on negative resistance control Download PDFInfo
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- CN110069857B CN110069857B CN201910325845.0A CN201910325845A CN110069857B CN 110069857 B CN110069857 B CN 110069857B CN 201910325845 A CN201910325845 A CN 201910325845A CN 110069857 B CN110069857 B CN 110069857B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a memristor based on negative resistance control, which comprises a first negative resistance unit U1, a second negative resistance unit U2 and a push-pull structure U3. One end of the push-pull structure U3 is connected with an input sine voltage, and the other two ends are respectively connected with the first negative resistance unit U1 and the second negative resistance unit U2. The other ends of the first negative resistance unit U1 and the second negative resistance unit U2 are both grounded. The invention provides a memristor based on negative resistance control, which can be realized by hardware and has a simple structure to simulate TiO 2 I-V characteristic of memristor to replace actual TiO 2 The memristor is researched and applied, and a plurality of new ideas are provided for model design and hardware circuit application of the memristor.
Description
Technical Field
The invention relates to a memristor model design, in particular to a memristor based on negative resistance control.
Background
The memristor is used as a passive memory device and is named as the dependence of resistance on the passing electric quantity. The memristor has a nano-sized structure and a nonvolatile characteristic, is high in erasing speed and long in erasing life, and has excellent performances such as multi-resistance-state switching characteristic and good CMOS compatibility. Therefore, the memristor has a wide application prospect in analog circuits, artificial intelligence computers, biological memory behavior simulation and the like, and is also considered as an important candidate for future storage and brain-like computing technologies.
Realizing nano TiO by Hewlett packard laboratory in 2008 2 Since the past, the memristors are more and more concerned and researched domestically and abroad. But because the memristor is difficult to realize and the manufacturing cost is high, an ordinary laboratory does not have the condition of carrying out experiments or researches on the actual memristor components. Design a memristor equivalent model to replace actual TiO 2 Memristors are of great significance. Although many scholars at home and abroad are always dedicated to research on memristor models, most of the study is based on simulation of mathematical formulas or MATLAB models, and few hardware-realizable memristor model circuits are complex. Therefore, design aHardware-implemented, simple-structured TiO 2 The memristor equivalent model is more important.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides the memristor which can be realized by hardware and has a simple structure and is based on negative resistance control to simulate TiO 2 The I-V characteristic of the memristor replaces an actual TiO2 memristor to conduct research and application.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a memristor based on negative resistance control at least comprises a first negative resistance unit U1, a second negative resistance unit U2 and a push-pull structure U3, wherein the first negative resistance unit U1 and the second negative resistance unit U2 are used for generating a hysteresis curve symmetric about an origin, the push-pull structure U3 is used for realizing that the memristor output characteristic is memristive at the origin, the memristor and TiO are not 0 in a memristive value 2 The output characteristic curve of the memristor basically conforms to that of TiO 2 The current-voltage characteristics of memristors are as follows:
wherein i (t), v (t) represent the current and voltage of the memristor, and alpha and beta are constants;
the first negative resistance unit U1 comprises a second resistor R 2 And an NPN R-HBT-NDR network, a second resistor R 2 One end of the first transistor Q is connected 1 The other end of the emitter is connected with the NPN-type R-HBT-NDR network, and the other end of the NPN-type R-HBT-NDR network is grounded; wherein the NPN type R-HBT-NDR network is composed of a third resistor R 3 A fourth resistor R 4 A fifth resistor R 5 First slide rheostat R p1 And a third transistor Q 3 A fourth transistor Q 4 Composition is carried out; third resistor R 3 One end and a second resistor R 2 Connected to a third resistor R 3 The other end is connected with a fifth resistor R 5 And a third transistor Q 3 A base electrode of (1); first slide rheostat R p1 One terminal and a second resistor R 2 Connected, first sliding varistorsDevice R p1 The other end is connected with a third transistor Q 3 Collector of and fourth transistor Q 4 A base electrode of (1); a fourth resistor R 4 One end and a second resistor R 2 Connected to a fourth resistor R 4 The other end is connected with a fourth transistor Q 4 A collector electrode of (a); fifth resistor R 5 The other end of (1), a third transistor Q 3 And a fourth transistor Q 4 The emitter of (2) is grounded;
the second negative resistance unit U2 comprises a seventh resistor R 7 And a PNP type R-HBT-NDR network; a seventh resistor R 7 One end of the first transistor is connected with the second transistor Q 2 The other end of the emitter is connected with the PNP type R-HBT-NDR network, and the other end of the PNP type R-HBT-NDR network is grounded; wherein the PNP type R-HBT-NDR network is composed of an eighth resistor R 8 A ninth resistor R 9 A tenth resistor R 10 A second slide rheostat R p2 And a fifth transistor Q 5 And a sixth transistor Q 6 Composition is carried out; eighth resistor R 8 One end and a seventh resistor R 7 Connected, eighth resistor R 8 The other end is connected with a tenth resistor R 10 And a fifth transistor Q 5 A base electrode of (1); second slide rheostat R p2 One end and a seventh resistor R 7 Connected, second slide rheostat R p2 The other end is connected with a fifth transistor Q 5 Collector of and a sixth transistor Q 6 A base electrode of (1); ninth resistor R 9 One end and a seventh resistor R 7 Connected by a ninth resistor R 9 The other end is connected with a sixth transistor Q 6 A collector electrode of (a); a tenth resistor R 10 Another terminal of the fifth transistor Q 5 And the sixth transistor Q 6 The emitter of (2) is grounded;
the push-pull structure U3 comprises a first diode D with the model number D1N40007 1 A second diode D 2 First resistance R 1 A sixth resistor R 6 And a first DC voltage source V 1 A second DC voltage source V 2 (ii) a First diode D 1 The negative terminal is connected with an input signal V S First diode D 1 The positive end is connected with a first resistor R 1 And a first transistor Q 1 The base electrode of (1); first electricityResistance R 1 The other end is connected with a first direct current voltage source V 1 Positive terminal and first transistor Q 1 The collector of (2), a first direct voltage source V 1 The negative end is grounded; second diode D 2 The positive terminal is connected with an input signal V S Second diode D 2 The negative end is connected with a sixth resistor R 6 And a second transistor Q 2 Base electrode of (2), sixth resistor R 6 The other end is connected with a second direct current voltage source V 2 Positive terminal, second DC voltage source V 2 The negative terminal is grounded.
Compared with the prior art, the invention has the following beneficial effects:
1. the practical TiO with higher cost and complex manufacturing process is replaced by the memristor based on negative resistance control 2 The memristor has important significance for hardware circuit research and application of the memristor;
2. the negative resistance unit is adopted to simulate and control the memristor, so that the difficulty of hardware implementation is greatly reduced, and meanwhile, the circuit structure is very simple and the debugging is convenient;
3. the memristor output characteristic memory device comprises a first negative resistance unit U1, a second negative resistance unit U2 and a push-pull structure U3, wherein the two negative resistance units U1 and U2 are used for generating a hysteresis curve with a switching characteristic, and the push-pull structure U3 is used for realizing that the memory conductance value of the output characteristic of the memristor at an original point is not 0. By adjusting R 4 、R 10 The resistance value of the voltage-current curve of the negative resistance unit can be changed, so that the memristor with different resistance values and threshold voltages can be flexibly simulated.
Drawings
FIG. 1 is a block diagram of the circuit configuration of the present invention.
FIG. 2 is a schematic diagram of a negative resistance control-based memristor circuit of the present invention.
FIG. 3 is an I-V curve of an NPN R-HBT-NDR network of the present invention.
The following specific embodiments will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.
Hair brushOn the basis of a memristor theoretical model, a negative resistance unit and a push-pull structure are utilized to realize the memristor based on negative resistance control based on the output characteristic of the memristor, and the memristor has more ideal high-low resistance state switching characteristic, the voltage-current characteristic curve and TiO 2 The memristor output curve substantially conforms.
Referring to fig. 1, a structural block diagram of a memristor based on negative resistance control is shown, and the memristor is composed of at least a first negative resistance unit U1, a second negative resistance unit U2 and a push-pull structure U3. The first negative resistance unit U1 and the second negative resistance unit U2 are used for generating a hysteresis curve which is symmetrical about an origin, and the push-pull structure U3 is used for eliminating the influence caused by the conduction voltage of the transistor and realizing that the memory conductance value near the origin is not zero. Devices of the three units in the diagram are common laboratory components and parts, and are simple to realize on hardware. In the technical scheme, the negative resistance units U1 and U2 are utilized to generate symmetrical hysteresis curves, and the influence of the conduction voltage of the triode is eliminated through the push-pull structure U3, so that the volt-ampere characteristic curve and TiO are obtained 2 Memristor curves are more consistent with memristors.
In the above technical scheme, tiO 2 General expression of memristor current-voltage characteristics:
where i (t), v (t) represent the current and voltage of the memristor, and α, β are constants. Under the excitation of sinusoidal voltage, a well-symmetrical hysteresis curve can be obtained. According to the invention, two negative resistance units are used for generating a hysteresis curve, and a push-pull structure is used for providing bias voltage, so that a compact and symmetrical hysteresis curve is obtained. Under the excitation of a periodic sinusoidal voltage signal, a current-voltage relation curve of the memristor based on negative resistance control conforms to TiO 2 Volt-ampere curve of memristor.
Referring to fig. 2, a schematic diagram of a Negative Resistance control-based memristor according to the present invention is shown, in which a Negative Resistance unit mainly includes four resistors and two Heterojunction Bipolar Transistors (HBTs) to form an R-HBT-NDR network, and an I-V characteristic curve with Negative Resistance characteristic (NDR) can be obtained by adjusting parameters.
Specifically, the first negative resistance unit U1 includes a second resistor R 2 And an NPN R-HBT-NDR network. A second resistor R 2 One end of the first transistor Q is connected 1 And the other end of the emitter is connected with the NPN-type R-HBT-NDR network, and the other end of the NPN-type R-HBT-NDR network is grounded. Wherein the NPN type R-HBT-NDR network is composed of a third resistor R 3 A fourth resistor R 4 A fifth resistor R 5 The first slide rheostat R p1 And a third transistor Q 3 And a fourth transistor Q 4 And (4) forming. Third resistor R 3 One terminal and a second resistor R 2 Connected to a third resistor R 3 The other end is connected with a fifth resistor R 5 And a third transistor Q 3 A base electrode of (1); first slide rheostat R p1 One terminal and a second resistor R 2 Connected, first slide rheostat R p1 The other end is connected with a third transistor Q 3 Collector of and fourth transistor Q 4 A base electrode of (1); a fourth resistor R 4 One terminal and a second resistor R 2 Connected, a fourth resistor R 4 The other end is connected with a fourth transistor Q 4 A collector electrode of (a); fifth resistor R 5 The other end of (1), a third transistor Q 3 And a fourth transistor Q 4 Is grounded.
The second negative resistance unit U2 comprises a seventh resistor R 7 And a PNP type R-HBT-NDR network. A seventh resistor R 7 One end of the first transistor is connected with the second transistor Q 2 And the other end of the emitter is connected with the PNP type R-HBT-NDR network, and the other end of the PNP type R-HBT-NDR network is grounded. Wherein the PNP type R-HBT-NDR network is composed of an eighth resistor R 8 A ninth resistor R 9 A tenth resistor R 10 A second slide rheostat R p2 And a fifth transistor Q 5 And a sixth transistor Q 6 And (4) forming. Eighth resistor R 8 One end and a seventh resistor R 7 Connected, eighth resistor R 8 The other end is connected with a tenth resistor R 10 And a fifth transistor Q 5 A base electrode of (1); second slide rheostat R p2 One end and a seventh resistor R 7 Connected, second slide rheostat R p2 The other end is connected with a fifth transistor Q 5 Collector of and a sixth transistor Q 6 The base electrode of (1); ninth resistor R 9 One end and a seventh resistor R 7 Connected to a ninth resistor R 9 The other end is connected with a sixth transistor Q 6 A collector electrode of (a); a tenth resistor R 10 Another terminal of (b), a fifth transistor Q 5 And the sixth transistor Q 6 The emitter of (2) is grounded.
The push-pull structure U3 comprises a first diode D with the model number D1N40007 1 A second diode D 2 First resistance R 1 A sixth resistor R 6 And a first DC voltage source V 1 A second DC voltage source V 2 . First diode D 1 The negative terminal is connected with an input signal V S The positive terminal is connected with a first resistor R 1 And a first transistor Q 1 The base electrode of (1); a first resistor R 1 The other end is connected with a first direct current voltage source V 1 Positive terminal and first transistor Q 1 The collector of (2), a first direct voltage source V 1 The negative terminal is grounded. Second diode D 2 Input signal V is connected to the positive terminal S The negative end is connected with a sixth resistor R 6 And a second transistor Q 2 Base electrode of (2), sixth resistor R 6 The other end is connected with a second direct current voltage source V 2 Positive terminal, second DC voltage source V 2 The negative terminal is grounded.
FIG. 3 is an I-V curve of a negative resistance cell, wherein I P Is the peak current, V P Is the peak voltage; i is V Is valley current, V V The valley voltage, region iii is the negative resistance region. Third transistor Q in NPN type R-HBT-NDR network 3 A fourth transistor Q 4 There are three regions of operation, and the voltage conditions that need to be satisfied for a cascode circuit are as follows:
(1) A cut-off region: u. of BE ≤U on And u is CE ＞u BE ；
(2) An amplification area: u. u BE ＞U on And u is CE ≥u BE ；
(3) A saturation area: u. of BE ＞U on And u is CE ＜u BE 。
In the characteristic curve shown in fig. 3, when the input signal is small, the third transistor Q 3 A fourth transistor Q 4 The emitter junction voltage of the NPN type R-HBT-NDR network is smaller than the starting voltage, and the collector junction is reversely biased, so that the emitter junction voltage and the collector junction are both in a cut-off state, and the working area of the whole NPN type R-HBT-NDR network is located in the area I; with the increase of the input signal, the third transistor Q 3 Is still in the off state and the fourth transistor Q 4 Is greater than the turn-on voltage and the collector junction is reverse biased, so that the fourth transistor Q 4 In the amplifying state, the total current flowing through the R-HBT-NDR network increases with the increase of the input signal, and the operating region of the NPN-type R-HBT-NDR network is located in a region ii, which is also referred to as a first positive resistance region of the NPN-type R-HBT-NDR network. As the input signal continues to increase, due to the fourth transistor Q 4 Is greater than its base voltage, and a fourth transistor Q 4 The base voltage of the transistor is connected with the third transistor Q 3 Are equal in collector voltage, and the third transistor Q 3 Is greater than its base voltage, a third transistor Q 3 Is again greater than its emitter voltage, a third transistor Q 3 And the emitter voltage of the fourth transistor Q 4 Are equal. In summary, the fourth transistor Q 4 The voltage between the collector and the emitter is greater than that of the third transistor Q 3 The voltage between the collector and the emitter, and thus, the third transistor Q 3 Will be larger than the fourth transistor Q 4 The saturation state is entered first. And a third transistor Q 3 After entering the saturation state, due to Q 3 The voltage between the collector and the emitter is small, typically only 0.1V to 0.3V, which results in a voltage applied to the fourth transistor Q 4 The voltage of the base is also small and does not reach the value of the turn-on voltage, so that the fourth transistor Q is enabled 4 In the off state. Therefore, at this time, the current of the entire R-HBT-NDR network is rather decreased, and the NPN-type R-HBT-NDR network operation region is located in region iii, which is also referred to as the negative resistance region of the NPN-type R-HBT-NDR network. After the input signal continues to increase, the fourth transistor Q 4 Is still in a cut-off state while the third transistor Q 3 And the current tail part has a slight rising trend under the influence of characteristics such as a base width modulation effect and the like, and at the moment, the operating region of the NPN-type R-HBT-NDR network is located in a region IV which is also called as a second positive resistance region of the NPN-type R-HBT-NDR network. Similarly, the current-voltage curve of the PNP type R-HBT-NDR network is similar to that of the NPN type R-HBT-NDR network, and has four operation regions, and the two are symmetric about the origin.
The first negative resistance unit U1 consists of a second resistor R 2 And an NPN R-HBT-NDR network, and a second resistor R 2 Then, when the first negative resistance unit U1 is excited by a sinusoidal voltage signal, the I-V curve of the first negative resistance unit U1 presents a hysteresis curve with high-low resistance state switching characteristics in the first quadrant. The NPN type R-HBT-NDR network adopts a first slide rheostat R p1 Therefore, the control of the peak current of the I-V characteristic curve and the circuit design are more flexible. Similarly, the second negative resistance unit U2 is composed of an eighth resistor R 8 And a PNP type R-HBT-NDR network, plus an eighth resistor R 8 Then, when the second negative resistance unit U2 is excited by a sinusoidal voltage signal, the I-V curve of the second negative resistance unit U2 presents a hysteresis curve with high-low resistance state switching characteristics in the third quadrant. If the first negative resistance unit U1 and the second negative resistance unit U2 are directly connected in parallel, a symmetric hysteresis loop based on a three-quadrant can be obtained. However, the curve near the origin is close to the horizontal axis in terms of output characteristics due to the influence of the transistor on-voltage and the like, that is, the memristive value near the origin is not zero.
In order to realize that the resistance value of the memristor based on negative resistance control is controllable at the origin, a push-pull structure U3 is considered to be introduced. In the push-pull structure U3 unit, a first diode D 1 Negative terminal and second diode D 2 The positive end is connected, and one end of the positive end is led out from the connection position and is connected with the sine voltage input. In the unit U3 with push-pull structure, a first transistor Q 1 Is connected with the first negative resistance unit and the second transistor Q 2 Is connected with the second negative resistance unit. A first resistor R 1 And a sixth resistor R 6 Are equal in resistance, the first diode D 1 A second onePolar tube D 2 The characteristics and the characteristics of the triode can be closely matched, and bias voltage is provided through the push-pull structure U1, so that the slope of the output characteristic curve of the whole memristor based on negative resistance control under the excitation of periodic sinusoidal voltage signals at the zero crossing point is not zero, and the output characteristic curve is closer to the output characteristic curve of an ideal memristor. The memristor based on negative resistance control has ideal high-low resistance state switching characteristics, and can be applied to digital circuits, such as binary logic, multi-valued logic and the like.
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not meant to be limiting, and that the changes and modifications of the above embodiments are within the scope of the present invention.
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it is possible to make various improvements and modifications to the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (1)
1. The memristor based on negative resistance control is characterized by at least comprising a first negative resistance unit U1, a second negative resistance unit U2 and a push-pull structure U3, wherein the first negative resistance unit U1 and the second negative resistance unit U2 are used for generating a hysteresis curve which is symmetrical about an origin, and the push-pull structure U3 is used for realizing the output characteristic curve of the memristor and enabling the memristor to have a memristive value which is not 0 at the origin;
the first negative resistance unit U1 comprises a second resistor R 2 And an NPN R-HBT-NDR network, a second resistor R 2 One end of the first transistor Q is connected 1 The other end of the emitter is connected with the NPN-type R-HBT-NDR network, and the other end of the NPN-type R-HBT-NDR network is grounded; wherein the NPN type R-HBT-NDR network is composed of a third resistor R 3 A fourth resistor R 4 A fifth resistor R 5 The first slide rheostat R p1 And a third transistor Q 3 A fourth transistor Q 4 Composition is carried out; third resistor R 3 One terminal and a second resistor R 2 Connected, third resistor R 3 The other end is connected with a fifth resistor R 5 And a third transistor Q 3 A base electrode of (1); first slide rheostat R p1 One terminal and a second resistor R 2 Connected, first slide rheostat R p1 The other end is connected with a third transistor Q 3 Collector of and fourth transistor Q 4 A base electrode of (1); a fourth resistor R 4 One end and a second resistor R 2 Connected to a fourth resistor R 4 The other end is connected with a fourth transistor Q 4 A collector electrode of (a); fifth resistor R 5 The other end of (1), a third transistor Q 3 And a fourth transistor Q 4 The emitter of (2) is grounded;
the second negative resistance unit U2 comprises a seventh resistor R 7 And a PNP type R-HBT-NDR network; a seventh resistor R 7 One end of the first transistor is connected with the second transistor Q 2 The other end of the emitter is connected with the PNP type R-HBT-NDR network, and the other end of the PNP type R-HBT-NDR network is grounded; wherein the PNP type R-HBT-NDR network is composed of an eighth resistor R 8 A ninth resistor R 9 A tenth resistor R 10 The second slide rheostat R p2 And a fifth transistor Q 5 And a sixth transistor Q 6 Composition is carried out; eighth resistor R 8 One end and a seventh resistor R 7 Connected, eighth resistor R 8 The other end is connected with a tenth resistor R 10 And a fifth transistor Q 5 A base electrode of (1); second slide rheostat R p2 One end and a seventh resistor R 7 Connecting, second slide rheostat R p2 The other end is connected with a fifth transistor Q 5 Collector of and a sixth transistor Q 6 Of (2) aA pole; ninth resistor R 9 One end and a seventh resistor R 7 Connected by a ninth resistor R 9 The other end is connected with a sixth transistor Q 6 A collector electrode of (a); a tenth resistor R 10 Another terminal of the fifth transistor Q 5 And the sixth transistor Q 6 The emitter of (2) is grounded;
the push-pull structure U3 comprises a first diode D with the model number of D1N40007 1 A second diode D 2 First resistance R 1 A sixth resistor R 6 And a first DC voltage source V 1 A second DC voltage source V 2 (ii) a First diode D 1 The negative terminal is connected with an input signal V S First diode D 1 The positive terminal is connected with a first resistor R 1 And a first transistor Q 1 The base electrode of (1); a first resistor R 1 The other end is connected with a first direct current voltage source V 1 Positive terminal and first transistor Q 1 The collector of (2), a first direct voltage source V 1 The negative end is grounded; second diode D 2 Input signal V is connected to the positive terminal S A second diode D 2 The negative end is connected with a sixth resistor R 6 And a second transistor Q 2 Base electrode of (2), sixth resistor R 6 The other end is connected with a second direct current voltage source V 2 Positive terminal, second DC voltage source V 2 The negative terminal is grounded.
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| JPS5854733A (en) * | 1981-09-28 | 1983-03-31 | Fujitsu Ltd | Push-pull type logical circuit |
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| CN102594193A (en) * | 2012-03-06 | 2012-07-18 | 广州金升阳科技有限公司 | Self-excitation push-pull converter |
| WO2018055900A1 (en) * | 2016-09-23 | 2018-03-29 | アイシン・エィ・ダブリュ株式会社 | Switching element driving circuit |
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