JP2023022273A5

JP2023022273A5 -

Info

Publication number: JP2023022273A5
Application number: JP2022194627A
Authority: JP
Filing date: 2022-12-06
Publication date: 2023-08-07
Anticipated expiration: 2040-06-05

Description

上記の目的を達成するため、本発明は、画像演出に必要な画像信号を生成するＶＤＰ（Video Display Processor ）、及び、前記ＶＤＰの動作を規定する設定値が設定されるＶＤＰレジスタを有するＶＤＰ回路と、前記画像信号の基礎データを不揮発的に記憶するＣＧＲＯＭと、プログラム処理を実行するＣＰＵ、前記ＣＰＵに制御されて動作する内部回路、及び、前記内部回路の動作を規定する設定値が設定される動作制御レジスタを有するＣＰＵ回路とを有し、前記ＣＰＵ回路が前記ＶＤＰ回路に発行するディスプレイリストと、前記ＣＰＵ回路による前記ＶＤＰレジスタへの設定動作に基づいて所定の画像演出動作が実行される遊技機であって、前記ＶＤＰがアクセス可能なＶＤＰメモリ空間には、所定ビット位置以下の下位ビットが０となる基点アドレスに基づいて、前記基礎データを展開する展開空間として使用可能な複数の領域が確保可能に構成される一方、前記ＣＰＵがアクセス可能なＣＰＵメモリ空間には、前記ＣＰＵ回路の外部に位置して、データバス幅を各々規定可能な複数のアドレス空間が含まれ、前記ＣＰＵのプログラム処理が開始されるまでに、前記ＶＤＰレジスタの初期値を設定する自動設定手段と、前記ＣＰＵのリセット後、不揮発メモリ領域に記憶されているプログラムを前記ＣＰＵが処理することで、前記アドレス空間へのアクセス動作について、必要な設定値を前記動作制御レジスタに設定するプログラム第１手段（ＳＰ１～ＳＰ２，ＳＰ６）と、その後、不揮発メモリ領域から揮発メモリ領域に転送されたプログラムを前記ＣＰＵが処理することで、前記ＶＤＰによる前記ＣＧＲＯＭへのアクセス動作について、必要な設定値を前記ＶＤＰレジスタに設定するプログラム第２手段（ＳＰ２０）と、を設け、前記プログラム第２手段による前記ＶＤＰレジスタへの設定値には、前記ＣＧＲＯＭを構成するメモリデバイスの種別や特性に対応する動作パラメータが含まれている。 In order to achieve the above object, the present invention provides a VDP (Video Display Processor) for generating an image signal necessary for image production, and a VDP circuit having a VDP register in which a setting value defining the operation of the VDP is set. , a CGROM for nonvolatilely storing the basic data of the image signal, a CPU for executing program processing, an internal circuit that operates under the control of the CPU, and set values that define the operation of the internal circuit are set. and a CPU circuit having an operation control register, wherein a predetermined image rendering operation is executed based on a display list issued by the CPU circuit to the VDP circuit and a setting operation to the VDP register by the CPU circuit. In the game machine, the VDP memory space accessible by the VDP has a plurality of areas that can be used as a development space for developing the basic data based on a base address in which the lower bits below a predetermined bit position are 0. can be secured, the CPU memory space accessible by the CPU includes a plurality of address spaces located outside the CPU circuit and each capable of defining a data bus width. By the automatic setting means for setting the initial value of the VDP register before the start of program processing, and by the CPU processing the program stored in the non-volatile memory area after resetting the CPU, the address space program first means (SP1 to SP2, SP6) for setting necessary set values in the operation control register, and then the CPU processes the program transferred from the nonvolatile memory area to the volatile memory area. By doing so, a program second means (SP20) for setting a necessary setting value to the VDP register for the access operation to the CGROM by the VDP is provided, and the setting to the VDP register by the program second means is provided. The value includes operating parameters corresponding to the type and characteristics of the memory device that constitutes the CGROM .

Claims

a VDP circuit having a VDP (Video Display Processor) that generates an image signal necessary for image rendering, and a VDP register in which setting values that define the operation of the VDP are set;
a CGROM for nonvolatilely storing basic data of the image signal;
A CPU that executes program processing, an internal circuit that operates under the control of the CPU, and a CPU circuit that has an operation control register in which a set value that defines the operation of the internal circuit is set,
A game machine in which a predetermined image rendering operation is executed based on a display list issued by the CPU circuit to the VDP circuit and a setting operation to the VDP register by the CPU circuit,
The VDP memory space accessible by the VDP is configured to be able to secure a plurality of areas that can be used as expansion spaces for expanding the basic data, based on a base address in which the lower bits below a predetermined bit position are 0. while
the CPU memory space accessible by the CPU includes a plurality of address spaces located outside the CPU circuit and each capable of defining a data bus width;
automatic setting means for setting an initial value of the VDP register before program processing of the CPU is started;
A program first means ( SP1 to SP2, SP6) and
Thereafter, the program transferred from the nonvolatile memory area to the volatile memory area is processed by the CPU to set necessary setting values in the VDP register for the access operation to the CGROM by the VDP. SP20) and,
A gaming machine, wherein the setting value to the VDP register by the program second means includes operation parameters corresponding to the type and characteristics of a memory device constituting the CGROM.