JP2022516865A - ディープトレンチ絶縁及びトレンチコンデンサを備える半導体デバイス - Google Patents
ディープトレンチ絶縁及びトレンチコンデンサを備える半導体デバイス Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 239000003990 capacitor Substances 0.000 title claims abstract description 69
- 238000009413 insulation Methods 0.000 title description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 229920005591 polysilicon Polymers 0.000 claims abstract description 56
- 238000001465 metallisation Methods 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims description 203
- 238000000034 method Methods 0.000 claims description 100
- 239000002344 surface layer Substances 0.000 claims description 66
- 230000008569 process Effects 0.000 claims description 45
- 239000002019 doping agent Substances 0.000 claims description 43
- 238000002347 injection Methods 0.000 claims description 38
- 239000007924 injection Substances 0.000 claims description 38
- 150000004767 nitrides Chemical class 0.000 claims description 37
- 238000004519 manufacturing process Methods 0.000 claims description 30
- 238000005137 deposition process Methods 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 8
- 238000001802 infusion Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- -1 including Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 229910052710 silicon Inorganic materials 0.000 description 23
- 239000010703 silicon Substances 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000000758 substrate Substances 0.000 description 12
- 230000008021 deposition Effects 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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Abstract
Description
Claims (20)
- 半導体デバイスであって、
半導体構造であって、
第1の導電型の多数キャリアドーパントを含む半導体表面層と、
第2の導電型の多数キャリアドーパントを含む埋込み層とを含む、前記半導体構造、
前記半導体表面層の上に延在するメタライゼーション構造、及び
絶縁構造、
を含み、
前記絶縁構造が、
前記半導体構造を介して前記埋込み層まで延在する第1のトレンチと、
前記半導体表面層から前記埋込み層まで前記第1のトレンチの側壁に沿って延在する第1の誘電体ライナと、
前記第1の導電型の多数キャリアドーパントを含む第1のポリシリコンであって、前記第1の誘電体ライナの内部を延在し、前記第1のトレンチを前記半導体表面層の頂部側まで充填する前記第1のポリシリコンと、
前記第2の導電型の多数キャリアドーパントを含む第1の深ドープ領域であって、前記第1のトレンチを囲み、前記半導体表面層から前記埋込み層まで延在する前記第1の深ドープ領域と、
前記第1のポリシリコンを前記第1の深ドープ領域に接続する前記メタライゼーション構造の第1の導電性特徴と、
を含む、
半導体デバイス。 - 請求項1に記載の半導体デバイスであって、
コンデンサをさらに含み、
前記コンデンサが、
前記半導体構造を介して前記埋込み層まで延在する第2のトレンチと、
前記半導体表面層から前記埋込み層まで前記第2のトレンチの側壁に沿って延在する第2の誘電体ライナと、
前記第1の導電型の多数キャリアドーパントを含む第2のポリシリコンであって、前記第2の誘電体ライナの内部を延在し、前記第2のトレンチを前記半導体表面層の頂部側まで充填する前記第2のポリシリコンと、
前記第2の導電型の多数キャリアドーパントを含む第2の深ドープ領域であって、前記第2のトレンチを囲み、前記半導体表面層から前記埋込み層まで延在する第2の深ドープ領域と、
第1のコンデンサプレートを形成するために前記第2のポリシリコンに接続されるメタライゼーション構造の第2の導電性特徴と、
第2のコンデンサプレートを形成するために前記第2の深ドープ領域に接続される前記メタライゼーション構造のさらなる導電性特徴と、
を含む、
半導体デバイス。 - 請求項2に記載の半導体デバイスであって、前記第1のトレンチが第1の深さを有し、前記第2のトレンチが第2の深さを有し、前記第1の深さが前記第2の深さよりも大きい、半導体デバイス。
- 請求項3に記載の半導体デバイスであって、前記第1のトレンチが第1の幅を有し、前記第2のトレンチが第2の幅を有し、前記第1の幅が前記第2の幅よりも大きい、半導体デバイス。
- 請求項2に記載の半導体デバイスであって、前記第1のトレンチが第1の幅を有し、前記第2のトレンチが第2の幅を有し、前記第1の幅が前記第2の幅よりも大きい、半導体デバイス。
- 請求項2に記載の半導体デバイスであって、
前記第1の誘電体ライナが、
前記半導体表面層から前記埋込み層まで前記第1のトレンチの前記側壁に沿って延在する第1の酸化物層、
前記半導体表面層から前記埋込み層まで前記第1の酸化物層に沿って延在する窒化物層、及び
前記半導体表面層から前記埋込み層まで前記窒化物層に沿って延びる第2の酸化物層、
を含み、
前記第2の誘電体ライナが、
前記半導体表面層から前記埋込み層まで前記第2のトレンチの前記側壁に沿って延在する第3の酸化物層、
前記半導体表面層から前記埋込み層まで前記第3の酸化物層に沿って延在する第2の窒化物層、及び
前記半導体表面層から前記埋込み層まで前記第2の窒化物層に沿って延在する第4の酸化物層、
を含む、
半導体デバイス。 - 請求項2に記載の半導体デバイスであって、前記コンデンサが、
前記半導体構造を介して前記埋込み層まで延在する複数の第2のトレンチであって、前記複数の第2のトレンチの各々が、前記第2の深ドープ領域によって囲まれ、前記半導体表面層から前記埋込み層までの前記第2のトレンチの側壁に沿って延在する対応する第2の誘電体ライナを含む、前記複数の第2のトレンチ、及び
前記第1の導電型の多数キャリアドーパントを含む対応する第2のポリシリコンであって、前記第2の誘電体ライナの内部に延在し、前記第2のトレンチを前記半導体表面層の前記頂部側まで充填する、前記第2のポリシリコン、
を含む、半導体デバイス。 - 請求項7に記載の半導体デバイスであって、前記コンデンサが、前記第2の導電型の多数キャリアドーパントを有する浅い注入領域であって、前記第2の深ドープ領域内の前記複数の第2のトレンチ間の前記半導体表面層において延在する、前記浅い注入領域をさらに含む、半導体デバイス。
- 請求項1に記載の半導体デバイスであって、前記第1の誘電体ライナが、
前記半導体表面層から前記埋込み層まで前記第1のトレンチの前記側壁に沿って延在する第1の酸化物層、
前記半導体表面層から前記埋込み層まで前記第1の酸化物層に沿って延在する窒化物層、及び
前記半導体表面層から前記埋込み層まで前記窒化物層に沿って延在する第2の酸化物層、
を含む、半導体デバイス。 - 請求項1に記載の半導体デバイスであって、前記第2の導電型の多数キャリアドーパントを有する浅い注入領域であって、前記第1の深ドープ領域内の前記第1のトレンチの側部に沿って前記半導体表面層において延在する、前記浅い注入領域をさらに含む、半導体デバイス。
- 半導体デバイスにおいて絶縁構造を作製する方法であって、
半導体構造内にトレンチを形成することであって、前記トレンチが、第1の導電型の多数キャリアドーパントを含む半導体表面層を介して、第2の導電型の多数キャリアドーパントを含む埋込み層まで延在する、前記トレンチを形成すること、
前記第2の導電型の多数キャリアドーパントを前記トレンチに注入して、前記トレンチを囲み前記半導体表面層から前記埋込み層まで延在する深ドープ領域を形成する、注入プロセスを実施すること、
前記トレンチの側壁上に誘電体ライナを堆積させる堆積プロセスを実施すること、
ポリシリコンを堆積させて前記トレンチを充填する堆積プロセスを実施すること、及び
前記半導体表面層の上を延在するメタライゼーション構造の導電性特徴を形成することであって、前記導電性特徴が前記ポリシリコンを前記深ドープ領域に接続して絶縁構造を形成する、前記導電性特徴を形成すること、
を含む、方法。 - 請求項11に記載の方法であって、前記誘電体ライナを堆積させる前記堆積プロセスを実施することが、
前記トレンチの前記側壁上に第1の酸化物層を堆積させる第1の堆積プロセスを実施すること、
前記第1の酸化物層上に窒化物層を堆積させる第2の堆積プロセスを実施すること、及び
前記窒化物層上に第2の酸化物層を堆積させる第3の堆積プロセスを実施すること、
を含む、方法。 - 請求項12に記載の方法であって、前記第2の導電型の多数キャリアドーパントを前記半導体表面層に注入して、前記深ドープ領域内の前記トレンチの側部に沿って延在する浅い注入領域を形成する注入プロセスを実施すること、をさらに含む方法。
- 請求項11に記載の方法であって、前記第2の導電型の多数キャリアドーパントを前記半導体表面層に注入して、前記深ドープ領域内の前記トレンチの側部に沿って延在する浅い注入領域を形成する注入プロセスを実施すること、をさらに含む方法。
- 半導体デバイスを作製する方法であって、
半導体構造の頂部表面にレジスト層を形成することであって、前記半導体構造が第1の導電型の多数キャリアドーパントを有する半導体表面層と、第2の導電型の多数キャリアドーパントを有する埋込み層とを含み、前記レジスト層が第1の開口及び第2の開口を含む、前記レジスト層を形成すること、
前記第1の開口を介してエッチングして前記半導体表面層を介して前記埋込み層まで延在する第1のトレンチを形成し、前記第2の開口を介してエッチングして前記半導体表面層を介して前記埋込み層まで延在する第2のトレンチを形成する、エッチングプロセスを実施すること、
前記第2の導電型の多数キャリアドーパントを前記第1の開口を介して注入して、前記第1のトレンチを囲み前記半導体表面層から前記埋込み層まで延在する第1の深ドープ領域を形成し、前記第2の導電型の多数キャリアドーパントを前記第2の開口を介して注入して、前記第2のトレンチを囲み前記半導体表面層から前記埋込み層まで延在する第2の深ドープ領域を形成する、注入プロセスを実施すること、
前記第1のトレンチの側壁上に前記第1の開口を介して第1の誘電体ライナを堆積させ、前記第2のトレンチの側壁上に前記第2の開口を介して第2の誘電体ライナを堆積させる、堆積プロセスを実施すること、
前記第1の開口を介して第1のポリシリコンを堆積させて前記第1のトレンチを充填し、前記第2の開口を介して第2のポリシリコンを堆積させて前記第2のトレンチを充填する、別の堆積プロセスを実施すること、及び
前記半導体表面層の上を延在するメタライゼーション構造の第1の導電性特徴を形成することであって、前記第1の導電性特徴が前記第1のポリシリコンを前記第1の深ドープ領域に接続して絶縁構造を形成する、前記第1の導電性特徴を形成すること、
前記メタライゼーション構造の第2の導電性特徴を形成することであって、前記第2の導電性特徴が前記第2のポリシリコンに接続して第1のコンデンサプレートを形成する、前記第2の導電性特徴を形成すること、及び
前記メタライゼーション構造のさらなる導電性特徴を形成することであって、前記さらなる導電性特徴が前記第2の深ドープ領域に接続して第2のコンデンサプレートを形成する、前記さらなる導電性特徴を形成すること、
を含む、方法。 - 請求項15に記載の方法であって、前記第1及び第2の誘電体ライナを堆積させる前記堆積プロセスを実施することが、
前記第1及び第2のトレンチの前記側壁上に前記第1及び第2の開口を介して第1の酸化物層を堆積させる第1の堆積プロセスを実施すること、
前記第1の酸化物層上に前記第1及び第2の開口を介して窒化物層を堆積させる第2の堆積プロセスを実施すること、及び
前記窒化物層上に前記第1及び第2の開口を介して第2の酸化物層を堆積させる第3の堆積プロセスを実施すること、
を含む、方法。 - 請求項15に記載の方法であって、前記レジスト層を形成することが、前記第1の開口を第1の幅でパターニングすること、及び前記第2の開口を第2の幅でパターン化することを含み、前記第1の幅が前記第2の幅よりも大きい、方法。
- 請求項17に記載の方法であって、前記第1のトレンチが第1の深さを有し、前記第2のトレンチが第2の深さを有し、前記第1の深さが前記第2の深さよりも大きい、方法。
- 請求項15に記載の方法であって、前記第1のトレンチが第1の深さを有し、前記第2のトレンチが第2の深さを有し、前記第1の深さが前記第2の深さよりも大きい、方法。
- 請求項15に記載の方法であって、前記第2の導電型の多数キャリアドーパントを前記半導体表面層に注入して、前記深ドープ領域内の前記第1のトレンチの側部に沿って延在する浅い注入領域を形成する注入プロセスを実施することをさらに含む方法。
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