JP2022051302A - Nitride semiconductor element - Google Patents

Abstract

To provide a nitride semiconductor element that is excellent in both electrical characteristics of an electrode on a second nitride semiconductor layer and reliability as an element.SOLUTION: A nitride semiconductor element comprises: a substrate 10; a first nitride semiconductor layer 20 of a first conductivity type formed on the substrate; a nitride semiconductor active layer 40 formed on a part of the first nitride semiconductor layer; a second nitride semiconductor layer 50 of a second conductivity type formed on the nitride semiconductor active layer; an electrode 60 formed on a part of the second nitride semiconductor layer; and an insulative oxide film 70 continuously formed so as to cover a part of an upper surface of the second nitride semiconductor layer, a lateral face of the electrode, and a part of an upper surface of the electrode. The electrode 60 has an alloy part 61 containing Au and an oxide part 62 containing Ni. The alloy part 61 is in contact with the second nitride semiconductor layer. The oxide part 62 covers at least a part of an upper surface of the alloy part 61 and at least a part of a lateral face of the alloy part 61.SELECTED DRAWING: Figure 2

Description

The present invention relates to a nitride semiconductor device.

The nitride semiconductor light emitting element, which is a kind of nitride semiconductor element, is, for example, a substrate, an n-type nitride semiconductor layer formed on the substrate, and a nitride formed on a part of the n-type nitride semiconductor layer. A semiconductor active layer, a p-type nitride semiconductor layer formed on a nitride semiconductor active layer, an n electrode formed on an n-type nitride semiconductor layer, and a p-type nitride semiconductor layer of a nitride semiconductor laminate. It is composed of a p-electrode formed above and a p-electrode formed above.
Patent Document 1 describes a nitride semiconductor device using a gallium nitride based semiconductor layer as the nitride semiconductor layer. In this nitride semiconductor device, a negative electrode whose main component is Au is formed on the n-type nitride semiconductor layer, and a positive electrode (p electrode) whose main component is Au is formed on the p-type nitride semiconductor layer. An insulating protective layer is formed on each electrode except for the connection portion with the external circuit.

The invention described in Patent Document 1 provides a highly reliable nitride semiconductor device having high insulation between positive and negative electrodes and effectively protecting the surface of an electrode having Au as a main component and a semiconductor layer. The purpose is to do. As a means for that, silicon oxide or silicon nitride is used as the insulating protective layer, and a metal (W, Ti, Cr, Ni, Cu and Al) is selected between the negative electrode and the positive electrode and the insulating protective layer. It is described to form an adhesion strengthening layer consisting of at least one metal oxide) or a metal oxide (an oxide of at least one metal selected from the above group).

Japanese Unexamined Patent Publication No. 11-150301

However, the nitride semiconductor device described in Patent Document 1 has insufficient electrical characteristics of the electrode (p electrode) on the p-type nitride semiconductor layer, and when, for example, annealing is performed in order to obtain good electrical characteristics, for example, The adhesion between the p electrode and the p-type nitride semiconductor layer may deteriorate, and the reliability of the nitride semiconductor element may decrease.
An object of the present invention is a nitride semiconductor device having excellent both electrical characteristics of an electrode on a second nitride semiconductor layer (nitride semiconductor layer formed on a nitride semiconductor active layer) and reliability as an element. Is to provide.

In order to achieve the above problems, the nitride semiconductor device according to one aspect of the present invention has the following configurations (1) to (3).
(1) The substrate, the first conductive type first nitride semiconductor layer formed on the substrate, the nitride semiconductor active layer formed on a part of the first nitride semiconductor layer, and the nitride semiconductor activity. A second conductive type second nitride semiconductor layer formed on the layer, an electrode formed on a part of the second nitride semiconductor layer, and a part of the upper surface of the second nitride semiconductor layer (the above electrode). A portion), the side surface of the electrode, and an insulating oxide film continuously formed so as to cover a part of the upper surface of the electrode.
(2) The electrode formed on the second nitride semiconductor layer has an alloy portion containing Au and an oxide portion containing Ni.
(3) The alloy portion is in contact with the second nitride semiconductor layer, and the oxide portion covers at least a part of the upper surface and at least a part of the side surface of the alloy part.

The nitride semiconductor device of the present invention is nitrided with excellent electrical characteristics of an electrode on a second nitride semiconductor layer (nitride semiconductor layer formed on a nitride semiconductor active layer) and reliability as an element. It can be expected to be a physical semiconductor device.

It is sectional drawing which shows the nitride semiconductor element of an embodiment. It is a partially enlarged view of FIG.

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited to the embodiments shown below. In the embodiments shown below, technically preferable limitations are made for carrying out the present invention, but this limitation is not an essential requirement of the present invention.
In this embodiment, an example in which the nitride semiconductor device of one aspect of the present invention is applied to an ultraviolet light emitting device is described. Further, the conductive type of the first nitride semiconductor layer is n-type, and the conductive type of the second nitride semiconductor layer is p-type.
The nitride semiconductor device according to one aspect of the present invention may be applied to a light emitting device other than the ultraviolet light emitting device, or may be applied to an element other than the light emitting device. Further, the conductive type of the first nitride semiconductor layer may be p-type, and the conductive type of the second nitride semiconductor layer may be n-type.

[overall structure]
First, the entire configuration of the ultraviolet light emitting device 100 of this embodiment will be described with reference to FIGS. 1 and 2. 1 and 2 show a cross section perpendicular to the substrate surface of the ultraviolet light emitting element 100.
As shown in FIG. 1, the ultraviolet light emitting element 100 is a thin substrate 10, an n-type nitride semiconductor layer (first nitride semiconductor layer) 20 formed on the substrate 10, and an n-type nitride semiconductor layer 20. The n electrode 30 formed in the portion 21, the light emitting layer (nitride semiconductor active layer) 40 formed in the thick portion 22 of the n-type nitride semiconductor layer 20, and the p-type nitride formed on the light emitting layer 40. It includes a semiconductor layer (second nitride semiconductor layer) 50, a p electrode 60 formed on a part of the p-type nitride semiconductor layer 50, an insulating oxide film 70, and a pad electrode 80.

The thin portion 21 of the n-type nitride semiconductor layer 20 is formed by laminating the n-type nitride semiconductor layer 20, the light emitting layer 40, and the p-type nitride semiconductor layer 50 in this order on the substrate 10, and then the light emitting layer 40. It is formed by removing a part of the laminated portion including the p-type nitride semiconductor layer 50 by etching or the like to expose a part of the n-type nitride semiconductor layer 20. That is, the ultraviolet light emitting element 100 has a so-called mesa structure.

The insulating oxide film 70 is a silicon oxide film, which is a part of the upper surface of the p-type nitride semiconductor layer 50 (the portion where the p electrode 60 is not formed) and the upper surface of the thin portion 21 of the n-type nitride semiconductor layer 20. (Part where n electrode 30 is not formed), part of the side surface and upper surface of n electrode 30 and p electrode 60 (part where Pad electrode 80 is not formed), and part of the side surface of Pad electrode 80. It is continuously formed so as to cover.

As shown in FIG. 2, the p-electrode 60 has an alloy portion 61 containing Au and an oxide portion 62 containing Ni. The alloy portion 61 is in contact with the p-type nitride semiconductor layer 50, and the oxide portion 62 covers all of the upper surface 61a and the side surface 61b of the alloy portion 61. The alloy containing Au in the alloy portion 61 is TiAu. Since the oxide portion 62 containing Ni has semiconductor-like conductivity, the alloy portion 61 containing Au and the Pad electrode 80 can be electrically connected to each other.
The film thickness of the alloy portion 61 is 30 nm or more and 200 nm or less, and the variation in film thickness is 20 nm or less. The film thickness of the oxide portion 62 is 25 nm or more and 200 nm or less, and the variation in film thickness is 20 nm or more and 200 nm or less.

In the cross section shown in FIG. 2 (cross section perpendicular to the substrate surface), the angle α formed by the side surface 62a of the oxide portion 62 in contact with the insulating oxide film 70 and the upper surface 50a of the p-type nitride semiconductor layer 50 is the alloy portion. The angle β is smaller than the angle β formed by the inner surface 62b of the oxide portion 62 in contact with the side surface 61b of the 61 and the upper surface 50a of the p-type nitride semiconductor layer 50, and the angle β is a sharp angle. That is, α <β <90 ° is satisfied. Since the side surface 62a and the inner surface 62b of the oxide portion 62 are not strictly flat but are uneven, the angles α and β are the angles formed by the lines L1 and L2 whose unevenness is close to a flat surface and the upper surface 50a. Measured as.

[Method for forming p-electrode 60]
The p-electrode 60 having an alloy portion 61 containing Au and an oxide portion 62 containing Ni is, for example, a deposition step of first depositing Ni on the p-type nitride semiconductor layer 50 and then depositing the Au alloy on the p-type nitride semiconductor layer 50. It can be formed by a method including a step of heat-treating in an oxygen atmosphere after the deposition step. In this method, Ni and Au are exchanged by using the reaction of Ni oxidation as a driving force, an alloy portion 61 containing Au is formed on the p-type nitride semiconductor layer 50, and an oxide portion 62 containing Ni is formed on the alloy portion 61 containing Au. It is formed.
Further, it is also possible to form the p-type nitride semiconductor layer 50 by first depositing an Au alloy and then depositing an oxide containing Ni on the p-type nitride semiconductor layer 50 without heat treatment.

[Actions and effects of embodiments]
In the ultraviolet light emitting element 100 of the embodiment, since the p electrode 60 has an alloy portion 61 containing Au and an oxide portion 62 containing Ni, the p electrode 60 has an alloy portion 61 containing Au and an oxide portion 62 containing Ni. The electrical characteristics of the p-electrode 60, the adhesion between the p-electrode 60 and the p-type nitride semiconductor layer 50, the adhesion between the p-electrode 60 and the insulating oxide film 70, and the adhesion between the p-electrode 60 and the insulating oxide film 70, as compared with those without the electrode 60. The reliability (light output is maintained for a long period of time) is good.
Further, in the ultraviolet light emitting element 100, since the p electrode 60 satisfies α <β <90 °, the insulating oxide film 70 is in a well-coated state, heat generation is prevented, and current concentration. It is also in a particularly favorable state in terms of suppressing the above.

Specifically, the oxide portion 62 is covered with the insulating oxide film 70 because the side surface 62a of the oxide portion 62 is a tapered surface extending toward the p-type nitride semiconductor layer 50 (α <90 °). The sex becomes good. Further, since the thickness of the side portion of the oxide portion 62 becomes thicker toward the p-type nitride semiconductor layer 50 (α <β), the heat generation of the alloy portion 61 containing Au having high conductivity can be suppressed. , Current concentration at the end of the p-electrode 60 (the portion close to the p-type nitride semiconductor layer 50) can be suppressed. By suppressing the heat generation of the alloy portion 61, a highly reliable ultraviolet light emitting element can be realized, and by suppressing the current concentration at the end of the p electrode 60, a high output ultraviolet light emitting element can be realized. ..

Further, in the ultraviolet light emitting device 100, the thickness of the alloy portion 61 is 30 nm or more and 200 nm or less, and the variation in the film thickness is 20 nm or less, so that good contact characteristics with the p-type nitride semiconductor layer 50 can be obtained. can. Further, as compared with the case where the ultraviolet light emitting element 100 has an electrode containing Au as a main component instead of the alloy portion 61 containing Au, it is possible to prevent the generation of voids due to the aggregation of Au during the heat treatment, and the semiconductor and the semiconductor. Since the contact area of the above can be maintained, good contact characteristics can be obtained.
Further, in the ultraviolet light emitting element 100, since the oxide portion 62 covers all of the upper surface 61a and the side surface 61b of the alloy portion 61, the adhesion between the alloy portion 61 and the oxide portion 62 is also excellent.
Therefore, the ultraviolet light emitting element 100 of the embodiment is excellent in both the electrical characteristics of the p electrode 60 and the reliability as an element.

[Details about each layer]
<Board>
The substrate 10 is not particularly limited as long as the n-type nitride semiconductor layer 20 can be formed on the substrate 10. Specifically, sapphire, silicon (Si), silicon carbide (SiC), magnesium oxide (MgO), digallium trioxide (Ga ₂ O ₃ ), zinc oxide (ZnO), gallium nitride (GaN), indium nitride (InN). ), Aluminum nitride (AlN), or a mixed crystal substrate thereof and the like.

From the viewpoint that the difference in lattice constant from the n-type nitride semiconductor layer 20 formed on the substrate 10 is small, through-transition can be reduced by growing in a lattice matching system, and the lattice strain due to whole gas generation can be increased. , A single crystal substrate made of a nitride semiconductor such as gallium nitride (GaN), aluminum nitride (AlN), or aluminum nitride gallium (AlGaN) as a bulk, or a nitride semiconductor such as GaN, AlN, or AlGaN grown on a certain material. It is preferable to use the layer (also referred to as a template) as the substrate 10.
Further, impurities may be mixed in the substrate 10. As a method for producing the substrate 10, a general substrate growth method such as a vapor layer growth method such as a sublimation method or an HVPE method or a liquid phase growth method can be applied.

<N-type nitride semiconductor layer>
The n-type nitride semiconductor layer 20 is a layer made of Al _X Ga _1-X N (0 <X ≦ 1), and may be directly formed on the substrate 10 as shown in FIG. 1, or the substrate. A layer other than the n-type nitride semiconductor layer 20 may be formed on the 10 and the n-type nitride semiconductor layer 20 may be formed on the layer. For example, a buffer layer may be formed on the substrate 10, an n-type AlGaN layer as the n-type nitride semiconductor layer 20 may be formed on the buffer layer, and a light emitting layer 40 may be formed on the n-type AlGaN layer.

Further, in the ultraviolet light emitting device according to another embodiment of the present invention, the n-type nitride semiconductor layer 20 may be directly or indirectly formed on the light emitting layer 40. That is, even if the p-type nitride semiconductor layer 50 and the light emitting layer 40 are laminated in this order on the substrate 10 and the n-type nitride semiconductor layer 20 is directly or indirectly formed on the light emitting layer 40. good.

Further, the n-type nitride semiconductor layer 20 is a layer made of Al _X Ga _1-X N (0 <X ≦ 1), but in this case, it is the same as the ultraviolet light emitting element 100 according to the embodiment of the present invention. To the extent that the effect can be obtained, add other elements such as group III elements such as indium (In) and group V elements such as phosphorus (P), arsenic (As), and antimony (Sb) by a few percent. It goes without saying that the case where a small amount is added to make a slight change in the composition of the n-type nitride semiconductor layer 20 is also included in the technical scope of the present invention. The same applies to the composition of the other layers.

The n-type nitride semiconductor layer 20 is preferably Al _X Ga _1-X N (0.4 ≦ X ≦ 1.0) from the viewpoint of the transparency of ultraviolet rays.
In addition to the n-type dopant, the n-type nitride semiconductor layer 20 includes other Group V elements such as phosphorus (P), arsenic (As), and antimony (Sb), carbon (C), hydrogen (H), and fluorine (F). ), Oxygen (O), magnesium (Mg), silicon (Si) and other impurities may be mixed. Here, the definition of impurities means that elements other than Al, Ga, and N are contained at a concentration of 1.0 × 10 ²⁰ cm ^-3 or less. That is, Al _X ^Ga _1-X N ⁽ 0 < It is interpreted as a layer consisting of X ≦ 1).

<Light emitting layer>
The light emitting layer 40 may be directly formed on the n-type nitride semiconductor layer 20 as shown in FIG. 1, or a layer other than the light emitting layer 40 is formed on the n-type nitride semiconductor layer 20 and the upper layer thereof. The light emitting layer 40 may be formed on the surface, and is not particularly limited. Specifically, the light emitting layer 40 may be formed on the undoped AlGaN layer formed on the n-type nitride semiconductor layer 20.
Further, as the ultraviolet light emitting device according to another embodiment of the present invention, the light emitting layer 40 may be formed on the p-type nitride semiconductor layer 50. That is, the p-type nitride semiconductor layer 50 may be formed on the substrate 10, the light emitting layer 40 may be laminated on the p-type nitride semiconductor layer 50, and the n-type nitride semiconductor layer 20 may be formed on the light emitting layer 40.

The material of the light emitting layer 40 is not particularly limited as long as it is a nitride semiconductor, but it may be a mixed crystal of aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) from the viewpoint of achieving high luminous efficiency. desirable. In addition to nitrogen (N), the light emitting layer 40 contains other Group V elements such as phosphorus (P), arsenic (As), and antimony (Sb), carbon (C), hydrogen (H), and fluorine (F). Impurities such as oxygen (O), magnesium (Mg), and silicon (Si) may be mixed. Further, a quantum well structure or a single-layer structure may be used, but it is desirable to have at least one well structure from the viewpoint of achieving high luminous efficiency.

<P-type nitride semiconductor layer>
The p-type nitride semiconductor layer 50 may be a single layer or a multilayer as long as it exhibits a p-type conductive type. As shown in FIG. 1, it may be directly formed on the light emitting layer 40, or a layer other than the p-type nitride semiconductor layer 50 is formed on the light emitting layer 40, and the p-type nitride semiconductor layer 50 is formed on the layer other than the p-type nitride semiconductor layer 50. It may be formed. For example, a gradient composition layer in which the ratio of constituent elements changes continuously or discretely is formed on the light emitting layer 40, and a p-type nitride semiconductor layer 50 may be formed on the inclined composition layer, and the present invention is not particularly limited. Further, a barrier layer having a relatively large band gap may be further provided between the light emitting layer 40 and the inclined composition layer.

Further, as the ultraviolet light emitting device according to another embodiment of the present invention, the p-type nitride semiconductor layer 50 may be directly or indirectly formed on the substrate 10. That is, the p-type nitride semiconductor layer 50 may be directly or indirectly laminated on the substrate 10, and the light emitting layer 40 and the n-type nitride semiconductor layer 20 may be formed in this order on the p-type nitride semiconductor layer 50.
The electrode of the p-type nitride semiconductor layer 50 may be in direct contact with the upper layer, or the electrode may be in contact with the uppermost surface of the multilayer. That is, when another p-type layer is formed on the p-type nitride semiconductor layer, the two layers can be collectively regarded as the p-type nitride semiconductor layer 50.

The p-type nitride semiconductor layer 50 may contain a p-type dopant from the viewpoint of generating holes inside the thin film, and conversely, it contains a dopant for injecting holes directly from the electrode into the two-dimensional hole gas at the interface. It does not have to be. Magnesium Mg is generally used as the P-type dopant, but beryllium Be, zinc Zn, and the like can also be used as long as they are impurities that generate holes.

<P electrode (electrode formed on the second nitride semiconductor layer)>
The ultraviolet light emitting device 100 includes a p electrode 60 from the viewpoint of increasing the hole injection efficiency into the p-type nitride semiconductor layer 50. The p-electrode is formed on the p-type nitride semiconductor layer 50 so as to be conductive to the p-type nitride semiconductor layer 50.

<Insulating oxide film>
From the viewpoint of semiconductor reliability, the ultraviolet light emitting device 100 covers a part of the upper surface of the p-type nitride semiconductor layer 50, the side surface of the p electrode 60, and a part of the upper surface of the p electrode. The film 70 is in a state of being continuously formed. The insulating oxide film 70 may directly or indirectly cover the upper surface of the p electrode 60, but it is preferable that the insulating oxide film 70 directly covers the upper surface of the p electrode 60 from the viewpoint of adhesion to the p electrode 60. Further, the insulating oxide film 70 is preferably a metal oxide film from the viewpoint of adhesion to the oxide portion 62 containing Ni. Of these, silicon oxide is more preferable from the viewpoint of adhesion.
Further, in the ultraviolet light emitting element 100, from the viewpoint of ease of probe measurement and wire bonding, the p electrode 60 is in a state where a contact hole is formed on an insulating film and a pad electrode 80 is formed on the contact hole.

<Method of forming each layer>
As a method for growing each layer of the ultraviolet light emitting device 100 according to one embodiment of the present embodiment, a film can be formed by using an epitaxial growth technique such as the MOVPE method, but the method is not limited thereto. For example, a film may be formed by using a hydride vapor phase growth method (HVPE method), a molecular beam epitaxy method (MBE method), or the like.

[About how to check the composition and how to measure the film thickness]
The composition of the alloy portion containing Au can be confirmed by processing the cross section of the sample, observing it with a transmission electron microscope (TEM), and then performing energy dispersive X-ray analysis (EDX).
The method for forming the alloy portion containing Au is not particularly limited. For example, it can be obtained by a physical vapor deposition method such as EB vapor deposition or sputtering.

The composition of the oxide portion containing Ni can be confirmed by processing the cross section of the sample, observing it with a transmission electron microscope (TEM), and then performing energy dispersive X-ray analysis (EDX).
The method for forming the oxide portion containing Ni is not particularly limited. For example, it can be obtained by using a method such as heat treatment of a Ni film formed by a physical vapor deposition method in an oxygen atmosphere, sputtering using an oxide as a target, and reactive sputtering in which an active gas such as oxygen gas is introduced into a sputtering space. be able to.

The film thickness of the oxide portion containing Ni is 25 nm or more and 200 nm or less, and the variation in film thickness is 20 nm or more and 200 nm or less from the viewpoint of adhesion to the insulating film and contact characteristics with the second nitride semiconductor. preferable. At 20 nm, the contact area is insufficient and the adhesion is poor, and at 200 nm or more, the film thickness of Ni and the metal contained before the heat treatment is too thick, and the contact characteristics deteriorate.

For the variation in film thickness, the cross-section of the sample is processed, and the difference between the thickest part and the thinnest part of the oxide containing Ni from the surface in contact with the p electrode 60 is obtained from the observation image by a transmission electron microscope (TEM). means.
The method for controlling the film thickness variation is not particularly limited, but it can be controlled to 20 nm or more and 200 nm by adjusting the heat treatment temperature when the metal containing Ni and the alloy containing Au are heat-treated in an oxygen atmosphere.

The angles α and β can be realized by adjusting the angle of incidence of the metal on the sample during electrode deposition and the annealing conditions of the electrodes. As an example, an alloy portion containing Au is formed by an EB vapor deposition method having a small incident angle on a sample in which a pattern is formed with a resist, and then an oxide portion containing Ni is formed by a sputtering method having a large incident angle. By turning it off, a sample in which α> β can be prepared.
The angles α and β can be calculated from images obtained by processing the cross section of the sample and observing with a transmission electron microscope (TEM).

[Applicable devices]
The ultraviolet light emitting element 100 according to the embodiment of the present invention can be applied to various devices.
The ultraviolet light emitting element 100 according to the embodiment of the present invention can be applied to all existing devices in which an ultraviolet lamp is used, and can be replaced. In particular, it is applicable to an apparatus using deep ultraviolet rays having a wavelength of 280 nm or less.
The ultraviolet light emitting element 100 according to an embodiment of the present invention can be applied to devices in, for example, medical or life science fields, environmental fields, industries or industrial fields, living or home appliances fields, agriculture fields, and other fields.

The ultraviolet light emitting device 100 according to an embodiment of the present invention includes a device for synthesizing or decomposing chemicals and chemical substances, a device for sterilizing liquids, gases, and solids (containers, foods, medical devices, etc.), a device for cleaning semiconductors, and a film. , Glass and metal surface modifiers, semiconductors, flat panel displays (FPDs), printed substrates (PCBs) and other exposure equipment for the manufacture of electronic products, printing or coating equipment, bonding or sealing equipment, films, patterns and mock It can be applied to transfer or molding equipment such as ups, and measurement or inspection equipment for banknotes, scratches, blood and chemical substances.

Examples of liquid sterilizers include automatic ice maker and ice trays in refrigerators, water tanks for ice storage containers and ice makers, freezers, ice makers, humidifiers, dehumidifiers, cold water tanks or hot water tanks for water servers, and the like. Channel piping, stationary water purifier, portable water purifier, water dispenser, water heater, wastewater treatment device, disposer, toilet drain trap, washing machine, dialysis water sterilization module, peritoneal dialysis connector sterilizer, disaster water storage system Etc., but this is not the case.

Examples of gas sterilizers include air purifiers, air conditioners, ceiling fans, floor and bedding vacuum cleaners, futon dryers, shoe dryers, washing machines, clothes dryers, indoor sterilizers, and storage ventilation. Systems, shoe boxes, tons, etc. can be mentioned, but this is not the case.
Examples of solid sterilizers (including surface sterilizers) include vacuum packers, conveyor belts, medical, dental, barber and beauty salon hand tool sterilizers, toothbrushes, toothbrush holders, chopstick boxes, cosmetic pouches, etc. Examples include, but are not limited to, drainage ditch lids, toilet bowl local cleaners, toilet bowl lids, and the like.

Hereinafter, the present invention will be described in more detail with reference to Examples and Comparative Examples. The present invention is not limited to the examples shown below.
[Manufacturing of element]
<Example 1>
This sample is an ultraviolet light emitting device 100 having the structure described in the embodiment, and has the following configuration.
The substrate 10 is an AlN substrate. The n-type nitride semiconductor layer 20 is an n-Al _0.7 Ga _0.3 N layer containing 2.0 × 10 ²⁰ cm ^-3 as impurities, and is thick with a thin portion (a portion where the n electrode 30 is formed) 21. It has a portion (a portion where the light emitting layer 40 is formed) 22. Further, an AlN buffer layer is provided between the substrate 10 and the n-type nitride semiconductor layer 20.

The light emitting layer 40 is a multiple quantum well having five layers of Al _0.51 Ga _0.49 N (well layer) having a thickness of 2.0 nm and Si-doped Al _0.78 Ga _0.22 N (barrier layer) having a thickness of 8.0 nm alternately. It is a structure. The p-type nitride semiconductor layer 50 is a p-type GaN layer containing 2.0 × 10 ²⁰ cm ^-3 as an impurity.
The n electrode 30 is a Ti / Al / Ni / Au layer. The p-electrode (first electrode) 60 has an AuTi alloy portion 61 in contact with the p-type nitride semiconductor layer 50 and an oxide portion 62 containing Ni that covers the upper surface and side surfaces of the AuTi alloy portion 61. The insulating oxide film 70 is a silicon oxide film and has a film thickness of 300 nm. The pad electrode 80 has a laminated structure of Ti and Au.

The ultraviolet light emitting element 100 was manufactured by the following method.
First, on an AlN substrate obtained from an AlN single crystal, an AlN buffer layer, an n-Al _0.7 Ga _0.3 N layer containing 2.0 × 10 ²⁰ cm ^-3 of Si as an impurity, the above-mentioned multiple quantum well structure of AlGaN, and A p-type GaN layer containing 2.0 × 10 ²⁰ cm ^-3 of Mg as an impurity was formed in this order by the organic metal vapor phase growth method (MOCVD method). As a result, a laminate was formed on the AlN substrate.

Next, the laminate on the AlN substrate is dry-etched to remove a part of the in-plane to a predetermined depth, and the n-Al _0.7 Ga _0.3 N layer is partially exposed to expose the n-type nitride. A thin portion 21 was formed on the semiconductor layer 20. This dry etching was performed using a chlorine-based gas after forming a resist pattern on the laminate by a photolithography method.
Next, using the resist pattern formed by the photolithography method, Ti is 20 nm thick, Au is 150 nm thick, and Ni is thickened in a predetermined region on the thin portion 21 of the n-type nitride semiconductor layer 20. Au was deposited at 30 nm and at a thickness of 50 nm in this order. Next, after removing the resist pattern, heat treatment was performed at 800 ° C. for 180 seconds. As a result, the n electrode 30 was formed.

Next, using a resist pattern formed by a photolithography method, Ni is deposited in a predetermined region on the p-type nitride semiconductor layer 50 by an EB vapor deposition machine at a thickness of 20 nm and TiAu at a thickness of 35 nm in this order. did. Next, after removing the resist pattern, heat treatment was performed at 600 ° C. for 180 seconds in an oxygen atmosphere. As a result, the p-electrode 60 was formed in which the upper surface and the side surface of the AuTi alloy portion 61 were covered with the oxide portion 62 containing Ni.
Next, a silicon oxide film of 300 nm was formed on the entire AlN substrate in this state by the plasma CVD method. Next, using the resist pattern formed by the photolithography method, contact holes were formed at predetermined positions of the silicon oxide film (the upper part of the n electrode 30 and the upper part of the p electrode 60) by etching with CF ₄ .

Next, Ti was deposited at a thickness of 20 nm and Au at a thickness of 1000 nm in each of the formed contact holes in this order. As a result, the pad electrode 80 was formed on the upper part of the n electrode 30 and the upper part of the p electrode 60.
The obtained ultraviolet light emitting element 100 was cut perpendicularly to the surface of the substrate 10 at the portion of the p electrode 60, and the cut surface was observed by TEM to confirm the cross-sectional structure of the p electrode 60, which is shown in FIG. It was confirmed that it was in a state. Moreover, when the values of the angle α and the angle β were measured from the TEM image of the cut surface, the angle α was 40 ° and the angle β was 55 °.

Further, from the TEM image of the cut surface, the film thickness and the variation in the film thickness were measured for the layer on the p-type semiconductor layer 50 side and the layer on the Pad electrode 80 side of the p electrode 60. As a result, the film thickness of the layer (alloy portion 61) on the p-type semiconductor layer 50 side was 25 nm to 45 nm, and the film thickness variation was 20 nm (45 nm-25 nm). The film thickness of the layer (oxide portion 62) on the Pad electrode 80 side was 10 nm to 210 nm, and the film thickness variation was 200 nm (210 nm-10 nm).

Further, the cut surface was subjected to surface analysis of the main elements (Si, Al, Ga, N, Ti, O, Ni, Au) by TEM-EDX (energy dispersive X-ray spectroscopy). The composition of the layer on the p-type semiconductor layer 50 side (alloy portion 61) was AuTi, and the composition of the layer on the Pad electrode 80 side (oxide portion 62) was NiO.

<Comparative Example 1>
In Example 1, in the step of forming the p-electrode 60, Ni was deposited in a predetermined region on the p-type nitride semiconductor layer 50 with a thickness of 20 nm and TiAu with a thickness of 35 nm in this order. Ni was deposited at a thickness of 20 nm and Au at a thickness of 35 nm in this order. Further, in Example 1, the subsequent heat treatment after removing the resist pattern was performed in an oxygen atmosphere at 600 ° C. for 180 seconds, but in this example, the heat treatment was performed in an oxygen atmosphere at 650 ° C. for 180 seconds. rice field. The ultraviolet light emitting device was obtained by the same method as in Example 1 except for these points. That is, the ultraviolet light emitting device of Comparative Example 1 has the same configuration as that of Example 1 except for the p electrode.

When the surface analysis of the cut surface obtained in the same manner as in Example 1 was performed on the obtained ultraviolet light emitting device by the same method as in Example 1, the composition of the layer on the p-type semiconductor layer 50 side of the p electrode was found. It was Au, and the composition of the layer on the Pad electrode 80 side was NiO. In addition, voids were present in the Au layer, which is the layer on the p-type semiconductor layer 50 side. That is, it was confirmed that the p-electrode of the ultraviolet light emitting device of Comparative Example 1 had an Au layer containing voids instead of the alloy layer 61 in FIG. 2. Moreover, when the values of the angle α and the angle β were measured from the TEM image of the cut surface, the angle α was 65 ° and the angle β was 55 °.

Further, from the TEM image of the cut surface, the film thickness and the variation in the film thickness were measured for the layer on the p-type semiconductor layer 50 side and the layer on the Pad electrode 80 side of the p electrode. As a result, in the layer on the p-type semiconductor layer 50 side, the film thickness was 0 nm to 75 nm, and the variation in film thickness was 75 nm (75 nm-0 nm) (0 nm is the void region). In the layer on the Pad electrode 80 side, the film thickness was 5 nm to 205 nm, and the film thickness variation was 200 nm (205 nm-5 nm).

<Comparative Example 2>
In Comparative Example 1, the heat treatment after the deposition of Ni and Au and the removal of the resist pattern was performed in an oxygen atmosphere at 650 ° C. for 180 seconds, but in this example, the heat treatment was performed in an oxygen atmosphere at 400 ° C. for 180 seconds. rice field. Except for this point, an ultraviolet light emitting device was obtained by the same method as in Comparative Example 1. That is, the ultraviolet light emitting element of Comparative Example 2 has the same configuration as that of Example 1 except for the p electrode.

When the surface analysis of the cut surface obtained in the same manner as in Example 1 was performed on the obtained ultraviolet light emitting device by the same method as in Example 1, the composition of the layer on the p-type semiconductor layer 50 side of the p electrode was Au. The composition of the layer on the Pad electrode 80 side was NiO. Further, no void was present in the Au layer, which is the layer on the p-type semiconductor layer 50 side. That is, it was confirmed in FIG. 2 that the p electrode of the ultraviolet light emitting device of Comparative Example 2 had a uniform Au layer instead of the alloy layer 61. Moreover, when the values of the angle α and the angle β were measured from the TEM image of the cut surface, the angle α was 80 ° and the angle β was 80 °.

Further, from the TEM image of the cut surface, the film thickness and the variation in the film thickness were measured for the layer on the p-type semiconductor layer 50 side and the layer on the Pad electrode 80 side of the p electrode. As a result, the film thickness of the p-type semiconductor layer 50 side was 30 nm to 40 nm, and the film thickness variation was 10 nm (40 nm to 30 nm). In the layer on the Pad electrode 80 side, the film thickness was 15 nm to 25 nm, and the film thickness variation was 10 nm (25 nm-10 nm).
In the ultraviolet light emitting device of Comparative Example 1, the reason why the layer on the p-type nitride semiconductor layer side of the p electrode became an Au layer containing voids was that the heat treatment temperature in an oxygen atmosphere was too high at 650 ° C. In Comparative Example 2 at 400 ° C., the Au layer had no voids.

<Comparative Example 3>
In Comparative Example 1, the heat treatment after the deposition of Ni and Au and the removal of the resist pattern was performed in an oxygen atmosphere at 650 ° C. for 180 seconds, but in this example, the heat treatment was performed in a nitrogen atmosphere at 600 ° C. for 180 seconds. rice field. Except for this point, an ultraviolet light emitting device was obtained by the same method as in Comparative Example 1.
When the surface analysis of the cut surface obtained in the same manner as in Example 1 was performed on the obtained ultraviolet light emitting device by the same method as in Example 1, the p electrode had an AuNi layer as a whole. That is, it was confirmed that the p electrode of the ultraviolet light emitting device of Comparative Example 3 did not have the oxide portion 62 in FIG. 2 and was entirely an AuNi layer (alloy layer containing Au).
Further, as a result of measuring the variation in the film thickness and the film thickness of the p electrode from the TEM image of the cut surface, the film thickness was 50 nm to 60 nm, and the variation in the film thickness was 10 nm (60 nm-50 nm).

<Comparative Example 4>
In Example 1, Ni was deposited in a predetermined region on the p-type nitride semiconductor layer 50 with a thickness of 20 nm and TiAu with a thickness of 35 nm in this order, and then the resist pattern was removed and heat treatment was performed. On the other hand, in this example, only Au is deposited at a thickness of 35 nm without depositing Ni, and after removing the resist pattern, NiO is formed into a mesh by a sputtering device using a resist pattern formed by a photolithography method. It was deposited on the Au layer at 200 nm.
Then, after that, a silicon oxide film having a thickness of 300 nm was formed by a plasma CVD method without performing heat treatment. The ultraviolet light emitting device was obtained by the same method as in Example 1 except for these points. That is, the ultraviolet light emitting element of Comparative Example 4 has the same configuration as that of Example 1 except for the p electrode.

When the surface analysis of the cut surface obtained in the same manner as in Example 1 was performed on the obtained ultraviolet light emitting device by the same method as in Example 1, the composition of the layer on the p-type semiconductor layer 50 side of the p electrode was Au. The layer on the Pad electrode 80 side was a mesh-like NiO layer. Further, no void was present in the Au layer, which is the layer on the p-type semiconductor layer 50 side. That is, it was confirmed that the p electrode of the ultraviolet light emitting element of Comparative Example 4 had an Au layer instead of the alloy layer 61 in FIG. 2, and the oxide portion 62 had a mesh shape. Moreover, when the values of the angle α and the angle β were measured from the TEM image of the cut surface, the angle α was 40 ° and the angle β was 80 °.

Further, from the TEM image of the cut surface, the film thickness and the variation in the film thickness were measured for the layer on the p-type semiconductor layer 50 side and the layer on the Pad electrode 80 side of the p electrode. As a result, the film thickness of the p-type semiconductor layer 50 side was 30 nm to 40 nm, and the film thickness variation was 10 nm (40 nm-30 nm). In the layer on the Pad electrode 80 side, the film thickness was 0 nm to 200 nm, and the film thickness variation was 200 nm (200 nm-0 nm).

[evaluation]
For each of the ultraviolet light emitting devices of Examples 1 and Comparative Examples 1 to 4, the electrical characteristics of the p-electrode, the adhesion between the p-electrode and the p-type nitride semiconductor layer 50, and the adhesion between the p-electrode and the insulating oxide film 70. , And reliability were measured by the following methods.

<Electrical characteristics of p electrode>
After forming the same p-GaN layer as above on the substrate, a resist pattern was formed on the upper surface of the p-GaN layer, and the p electrodes of Examples 1 and Comparative Examples 1 to 4 were formed in the openings thereof, respectively. The contact resistivity of each test p electrode of Example 1 and Comparative Examples 1 to 4 thus obtained was measured to examine the performance of ohmic contact.
The contact resistivity was measured by a CTLM (Circular Transmission Line Model) measuring method. Specifically, the gap of the ring pattern for measuring contact resistance was set to 20 μm, and the current value when a voltage of 20 V was applied was measured. When this current value was 10 mA or less, it was determined that the electrical characteristics of the p electrode were defective.

<Adhesion between p-electrode and p-type nitride semiconductor layer and insulating oxide film>
In the state where the ultraviolet light emitting elements of Examples 1 and Comparative Examples 1 to 4 are formed on the wafer, each wafer is put into an organic solvent for ultrasonic cleaning, and then put in ultrapure water for ultrasonic cleaning. Was done. After that, each wafer was observed with a microscope to check whether or not peeling occurred between the p-electrode and the p-type nitride semiconductor layer and between the p-electrode and the insulating oxide film.
Further, each of the ultraviolet light emitting elements of Examples 1 and Comparative Examples 1 to 4 (cut out from a wafer and made into a device) was placed in an environment of 55 ° C., energized with a constant current of 350 mA, and then observed with a microscope. Then, it was investigated whether or not peeling occurred between the p-electrode and the p-type nitride semiconductor layer and between the p-electrode and the insulating oxide film.
The adhesion evaluation was judged to be good when peeling did not occur in both of the above two tests, and was judged to be poor when peeling occurred in either or both tests.

<Reliability>
Each of the ultraviolet light emitting elements of Examples 1 and Comparative Examples 1 to 4 (cut out from a wafer and made into a device) was subjected to a continuous energization test at 500 mA in an environment of 25 ° C., and the light output was measured after 500 hours had passed. did. When this measured value drops to less than half of the initial value of the optical output, it is judged that the reliability is poor.
These results are shown in Table 1 together with the configuration of each element.

The following can be seen from the results in Table 1.
The ultraviolet light emitting device 100 of the first embodiment has a p-electrode 60 having the structure shown in FIG. 2, that is, the p-electrode has an alloy (TiAu alloy) portion 61 containing Au and an oxide portion 62 containing Ni. , Α <β is satisfied, and the variation in the film thickness of each part also satisfies the preferable range, so that the electrical characteristics are good, the adhesion to the p-type nitride semiconductor layer and the insulating oxide film is also good, and the reliability of the device is also good. It became a good one.

In the ultraviolet light emitting device of Comparative Example 1, the layer on the p-type nitride semiconductor layer side of the p electrode was a non-uniform Au layer containing voids, so that the electrical characteristics of the p electrode were poor. In addition, the adhesion to the p-type nitride semiconductor layer was poor, and the reliability of the device was also poor.
In the ultraviolet light emitting device of Comparative Example 2, the layer on the p-type nitride semiconductor layer side of the p electrode was a uniform Au layer without voids, but the heat treatment temperature in an oxygen atmosphere was as low as 400 ° C., so p. The electrical characteristics of the electrodes were poor. Further, since the film thickness variation of the Ni oxide portion is 10 nm (less than 25 nm), the adhesion to the insulating oxide film is poor, and the reliability of the device is also poor.

In the ultraviolet light emitting element of Comparative Example 3, since the entire p electrode was an AuNi layer, the electrical characteristics of the p electrode were poor. Further, since the p electrode does not have a Ni oxide portion, the adhesion to the insulating oxide film is poor, and the reliability of the device is also poor.
In the ultraviolet light emitting device of Comparative Example 4, the layer on the p-type nitride semiconductor layer side of the p electrode was a uniform Au layer without voids, but the electrical characteristics of the p electrode were poor because it was not heat-treated. Yes, the reliability of the element was also poor. Since the p-electrode has a mesh-like Ni oxide portion, the adhesion to the p-type nitride semiconductor layer and the insulating oxide film was good.

10 Substrate 20 n-type nitride semiconductor layer (first nitride semiconductor layer)
30 n electrode 40 light emitting layer (nitride semiconductor active layer)
50 p-type nitride semiconductor layer (second nitride semiconductor layer)
Top surface of 50a p-type nitride semiconductor layer 60p electrode (electrode formed on a part of the second nitride semiconductor layer)
61a Alloy part containing Au 61a Top surface of alloy part containing Au 61b Side surface of alloy part containing Au 62 Oxide part containing Ni 62a Side surface of oxide part containing Ni 62b Inner surface of oxide part containing Ni 70 Insulation Oxide film 80 Pad electrode 100 Ultraviolet light emitting element (nitride semiconductor element)

Claims (7)

With the board
The first conductive type first nitride semiconductor layer formed on the substrate and
The nitride semiconductor active layer formed on a part of the first nitride semiconductor layer and
The second conductive type second nitride semiconductor layer formed on the nitride semiconductor active layer and
An electrode formed on a part of the second nitride semiconductor layer and
A part of the upper surface of the second nitride semiconductor layer, a side surface of the electrode, and an insulating oxide film continuously formed so as to cover a part of the upper surface of the electrode.
The electrode has an alloy portion containing Au and an oxide portion containing Ni.
The alloy portion is in contact with the second nitride semiconductor layer, and the oxide portion is a nitride semiconductor element that covers at least a part of the upper surface and at least a part of the side surface of the alloy part. The nitride semiconductor device according to claim 1, wherein the alloy portion has a film thickness of 30 nm or more and 200 nm or less, and the variation in the film thickness is 20 nm or less. The nitride semiconductor device according to claim 1 or 2, wherein the oxide portion has a film thickness of 25 nm or more and 200 nm or less, and the variation in the film thickness is 20 nm or more and 200 nm or less. The nitride semiconductor device according to any one of claims 1 to 3, wherein the alloy portion is a TiAu alloy portion. The nitride semiconductor device according to any one of claims 1 to 4, wherein all the side surfaces of the alloy portion are covered with the oxide portion. The nitride semiconductor device according to any one of claims 1 to 5, wherein the insulating oxide film is a silicon oxide film. In the cross section perpendicular to the substrate surface, the angle α formed by the side surface of the oxide portion in contact with the insulating oxide film and the upper surface of the second nitride semiconductor layer is the oxide in contact with the side surface of the alloy portion. The nitride semiconductor device according to any one of claims 1 to 6, wherein the angle β is smaller than the angle β formed by the inner surface of the portion and the upper surface of the second nitride semiconductor layer, and the angle β is a sharp angle.

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