JP2021509514A5 - - Google Patents

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JP2021509514A5
JP2021509514A5 JP2020537005A JP2020537005A JP2021509514A5 JP 2021509514 A5 JP2021509514 A5 JP 2021509514A5 JP 2020537005 A JP2020537005 A JP 2020537005A JP 2020537005 A JP2020537005 A JP 2020537005A JP 2021509514 A5 JP2021509514 A5 JP 2021509514A5
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neural network
artificial neural
circuit
network according
transistor
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JP7244525B2 (ja
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JP2020537005A 2018-01-03 2018-11-29 深層学習人工ニューラルネットワークにおけるアナログ不揮発性メモリ用のプログラム可能なニューロン Active JP7244525B2 (ja)

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Application Number Priority Date Filing Date Title
US201862613373P 2018-01-03 2018-01-03
US62/613,373 2018-01-03
US15/936,983 US11354562B2 (en) 2018-01-03 2018-03-27 Programmable neuron for analog non-volatile memory in deep learning artificial neural network
US15/936,983 2018-03-27
PCT/US2018/063147 WO2019135839A1 (en) 2018-01-03 2018-11-29 Programmable neuron for analog non-volatile memory in deep learning artificial neural network

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JP2021509514A JP2021509514A (ja) 2021-03-25
JP2021509514A5 true JP2021509514A5 (https=) 2022-01-06
JP7244525B2 JP7244525B2 (ja) 2023-03-22

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US (1) US11354562B2 (https=)
EP (1) EP3735656B1 (https=)
JP (1) JP7244525B2 (https=)
KR (1) KR102616978B1 (https=)
CN (1) CN111542840B (https=)
TW (1) TWI785174B (https=)
WO (1) WO2019135839A1 (https=)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102182583B1 (ko) 2016-05-17 2020-11-24 실리콘 스토리지 테크놀로지 인크 비휘발성 메모리 어레이를 사용하는 딥러닝 신경망 분류기
US11087207B2 (en) * 2018-03-14 2021-08-10 Silicon Storage Technology, Inc. Decoders for analog neural memory in deep learning artificial neural network
US11687766B2 (en) * 2018-06-19 2023-06-27 Qualcomm Incorporated Artificial neural networks with precision weight for artificial intelligence
US10528643B1 (en) * 2018-08-01 2020-01-07 Sandisk Technologies Llc Vector-matrix multiplication using non-volatile memory cells
US10956814B2 (en) * 2018-08-27 2021-03-23 Silicon Storage Technology, Inc. Configurable analog neural memory system for deep learning neural network
US10489483B1 (en) * 2018-09-21 2019-11-26 National Technology & Engineering Solutions Of Sandia, Llc Circuit arrangement and technique for setting matrix values in three-terminal memory cells
US10877752B2 (en) * 2018-09-28 2020-12-29 Intel Corporation Techniques for current-sensing circuit design for compute-in-memory
US11500442B2 (en) 2019-01-18 2022-11-15 Silicon Storage Technology, Inc. System for converting neuron current into neuron current-based time pulses in an analog neural memory in a deep learning artificial neural network
US11270763B2 (en) 2019-01-18 2022-03-08 Silicon Storage Technology, Inc. Neural network classifier using array of three-gate non-volatile memory cells
US11023559B2 (en) 2019-01-25 2021-06-01 Microsemi Soc Corp. Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
US11270771B2 (en) 2019-01-29 2022-03-08 Silicon Storage Technology, Inc. Neural network classifier using array of stacked gate non-volatile memory cells
JP6977908B2 (ja) * 2019-03-01 2021-12-08 Tdk株式会社 積和演算器、ニューロモーフィックデバイスおよび積和演算方法
US11423979B2 (en) * 2019-04-29 2022-08-23 Silicon Storage Technology, Inc. Decoding system and physical layout for analog neural memory in deep learning artificial neural network
US11393546B2 (en) 2019-07-19 2022-07-19 Silicon Storage Technology, Inc. Testing circuitry and methods for analog neural memory in artificial neural network
US11449741B2 (en) * 2019-07-19 2022-09-20 Silicon Storage Technology, Inc. Testing circuitry and methods for analog neural memory in artificial neural network
CN110533160A (zh) * 2019-07-22 2019-12-03 北京大学 基于nor flash模拟量计算阵列的深度神经网络
US11562212B2 (en) 2019-09-09 2023-01-24 Qualcomm Incorporated Performing XNOR equivalent operations by adjusting column thresholds of a compute-in-memory array
KR102225558B1 (ko) * 2019-10-14 2021-03-08 연세대학교 산학협력단 온칩 활성화 함수가 구현된 아날로그 신호 전달 기반의 멀티 레이어 연산 회로
CN110991623B (zh) * 2019-12-20 2024-05-28 中国科学院自动化研究所 基于数模混合神经元的神经网络运算系统
US11636322B2 (en) * 2020-01-03 2023-04-25 Silicon Storage Technology, Inc. Precise data tuning method and apparatus for analog neural memory in an artificial neural network
JP7595057B2 (ja) * 2020-02-21 2024-12-05 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
US11568021B2 (en) 2020-02-21 2023-01-31 Alibaba Group Holding Limited Vector-vector multiplication techniques for processing systems
US11355184B2 (en) * 2020-03-05 2022-06-07 Silicon Storage Technology, Inc. Analog neural memory array in artificial neural network with substantially constant array source impedance with adaptive weight mapping and distributed power
US11038520B1 (en) * 2020-04-15 2021-06-15 International Business Machines Corporation Analog-to-digital conversion with reconfigurable function mapping for neural networks activation function acceleration
KR102873065B1 (ko) 2020-04-23 2025-10-16 삼성전자주식회사 뉴로모픽 컴퓨팅 장치 및 그것의 동작 방법
US12299562B2 (en) * 2020-05-10 2025-05-13 Silicon Storage Technology, Inc. Analog neural memory array in artificial neural network with source line pulldown mechanism
KR102903267B1 (ko) * 2020-05-20 2025-12-22 삼성전자주식회사 뉴럴 네트워크를 구현하는 뉴로모픽 장치 및 그 동작 방법
US11875852B2 (en) * 2020-07-06 2024-01-16 Silicon Storage Technology, Inc. Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network
US11289171B1 (en) * 2020-10-02 2022-03-29 Sandisk Technologies Llc Multi-level ultra-low power inference engine accelerator
WO2022181999A1 (ko) * 2021-02-23 2022-09-01 한국과학기술원 우수한 선형성 특성을 갖는 뉴로모픽 시냅스 소자 및 그 동작 방법
JP7628623B2 (ja) * 2021-02-25 2025-02-10 シリコン ストーリッジ テクノロージー インコーポレイテッド 人工ニューラルネットワークにおけるアナログニューラルメモリのための精密なデータチューニング方法及び装置
US11605426B2 (en) * 2021-04-23 2023-03-14 Applied Materials, Inc. Retention drift correction in non-volatile memory arrays
CN115310030A (zh) * 2021-05-07 2022-11-08 脸萌有限公司 一种矩阵乘法电路模块及方法
EP4557173A3 (en) * 2021-07-05 2025-08-20 Silicon Storage Technology Inc. Programmable output blocks for analog neural memory in a deep learning artificial neural network
US20230049032A1 (en) * 2021-08-02 2023-02-16 Silicon Storage Technology, Inc. Output circuitry for analog neural memory in a deep learning artificial neural network
US11989440B2 (en) * 2021-08-11 2024-05-21 Silicon Storage Technology, Inc. Hybrid memory system configurable to store neural memory weight data in analog form or digital form
US11489534B1 (en) * 2021-10-11 2022-11-01 Cirrus Logic, Inc. Digital-to-analog conversion architecture and method
US11687252B2 (en) 2021-10-18 2023-06-27 Western Digital Technologies, Inc. Non-volatile memory with pre-trained model and inference circuit
CN114139692B (zh) * 2021-11-30 2024-03-08 河南科技大学 一种基于模拟态架构的cmos人工神经元功能电路
US12099743B2 (en) 2022-03-31 2024-09-24 SanDisk Technologies, Inc. Non-volatile memory integrated with artificial intelligence system for preemptive block management

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2677656B2 (ja) * 1989-02-28 1997-11-17 富士通株式会社 ニューロコンピュータの集中制御方式
JP2679738B2 (ja) 1989-03-01 1997-11-19 富士通株式会社 ニューロコンピュータにおける学習処理方式
US5305250A (en) 1989-05-05 1994-04-19 Board Of Trustees Operating Michigan State University Analog continuous-time MOS vector multiplier circuit and a programmable MOS realization for feedback neural networks
US5148514A (en) * 1989-05-15 1992-09-15 Mitsubishi Denki Kabushiki Kaisha Neural network integrated circuit device having self-organizing function
JP2517410B2 (ja) * 1989-05-15 1996-07-24 三菱電機株式会社 学習機能付集積回路装置
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
JPH0451382A (ja) * 1990-06-20 1992-02-19 Hitachi Ltd 情報処理装置
US5353382A (en) * 1990-10-15 1994-10-04 California Institute Of Technology Programmable synapse for neural network applications
US5237210A (en) * 1992-03-12 1993-08-17 Intel Corporation Neural network accomodating parallel synaptic weight adjustments for correlation learning algorithms
US5264734A (en) 1992-05-19 1993-11-23 Intel Corporation Difference calculating neural network utilizing switched capacitors
US5256911A (en) 1992-06-10 1993-10-26 Intel Corporation Neural network with multiplexed snyaptic processing
US6041322A (en) * 1997-04-18 2000-03-21 Industrial Technology Research Institute Method and apparatus for processing data in a neural network
US6829598B2 (en) 2000-10-02 2004-12-07 Texas Instruments Incorporated Method and apparatus for modeling a neural synapse function by utilizing a single conventional MOSFET
US6747310B2 (en) 2002-10-07 2004-06-08 Actrans System Inc. Flash memory cells with separated self-aligned select and erase gates, and process of fabrication
US6781186B1 (en) * 2003-01-30 2004-08-24 Silicon-Based Technology Corp. Stack-gate flash cell structure having a high coupling ratio and its contactless flash memory arrays
US8464123B2 (en) * 2009-05-07 2013-06-11 Ramot At Tel Aviv University Ltd. Matrix structure for block encoding
US8532602B2 (en) 2009-06-30 2013-09-10 Skyworks Solutions, Inc. Switching system with linearizing circuit
JP5300773B2 (ja) * 2010-03-29 2013-09-25 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
CN102456157B (zh) 2010-10-20 2015-08-26 北京大学 神经元器件和神经网络
US9418333B2 (en) * 2013-06-10 2016-08-16 Samsung Electronics Co., Ltd. Synapse array, pulse shaper circuit and neuromorphic system
US9715655B2 (en) * 2013-12-18 2017-07-25 The United States Of America As Represented By The Secretary Of The Air Force Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems
JP6501146B2 (ja) * 2014-03-18 2019-04-17 パナソニックＩｐマネジメント株式会社 ニューラルネットワーク回路およびその学習方法
US9922715B2 (en) * 2014-10-03 2018-03-20 Silicon Storage Technology, Inc. Non-volatile split gate memory device and a method of operating same
EP3035249B1 (en) 2014-12-19 2019-11-27 Intel Corporation Method and apparatus for distributed and cooperative computation in artificial neural networks
US9716852B2 (en) 2015-04-03 2017-07-25 Semiconductor Energy Laboratory Co., Ltd. Broadcast system
US10014318B2 (en) * 2015-10-24 2018-07-03 Monocithic 3D Inc Semiconductor memory device, structure and methods
US10169701B2 (en) * 2015-05-26 2019-01-01 International Business Machines Corporation Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models
US10325006B2 (en) * 2015-09-29 2019-06-18 International Business Machines Corporation Scalable architecture for analog matrix operations with resistive devices
EP3208750A1 (en) 2016-02-22 2017-08-23 Universität Zürich An analogue electronic deep neural network
KR102182583B1 (ko) 2016-05-17 2020-11-24 실리콘 스토리지 테크놀로지 인크 비휘발성 메모리 어레이를 사용하는 딥러닝 신경망 분류기
US10664745B2 (en) * 2016-06-29 2020-05-26 International Business Machines Corporation Resistive processing units and neural network training methods
US10776684B1 (en) * 2016-11-02 2020-09-15 National Technology & Engineering Solutions Of Sandia, Llc Mixed core processor unit
JP6183980B1 (ja) * 2016-12-02 2017-08-23 国立大学法人東京工業大学 ニューラルネットワーク回路装置、ニューラルネットワーク、ニューラルネットワーク処理方法およびニューラルネットワークの実行プログラム
CN106815636B (zh) * 2016-12-30 2019-03-05 华中科技大学 一种基于忆阻器的神经元电路
US10909449B2 (en) * 2017-04-14 2021-02-02 Samsung Electronics Co., Ltd. Monolithic multi-bit weight cell for neuromorphic computing
US12106211B2 (en) * 2017-04-27 2024-10-01 The Regents Of The University Of California Mixed signal neuromorphic computing with nonvolatile memory devices
US11875852B2 (en) * 2020-07-06 2024-01-16 Silicon Storage Technology, Inc. Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network
US11545214B2 (en) * 2020-07-08 2023-01-03 Samsung Electronics Co., Ltd. Resistive memory device

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