JP2021504941A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2021504941A5 JP2021504941A5 JP2020527813A JP2020527813A JP2021504941A5 JP 2021504941 A5 JP2021504941 A5 JP 2021504941A5 JP 2020527813 A JP2020527813 A JP 2020527813A JP 2020527813 A JP2020527813 A JP 2020527813A JP 2021504941 A5 JP2021504941 A5 JP 2021504941A5
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- power
- cell
- post
- routed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims 44
- 238000000034 method Methods 0.000 claims 8
- 239000004065 semiconductor Substances 0.000 claims 5
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022069531A JP7668763B2 (ja) | 2017-11-21 | 2022-04-20 | セル面積を縮小し、チップレベルでのセル配置を改善するための金属０電源接地スタブ経路（ｍｅｔａｌ ｚｅｒｏ ｐｏｗｅｒ ｇｒｏｕｎｄ ｓｔｕｂ ｒｏｕｔｅ） |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/819,879 | 2017-11-21 | ||
| US15/819,879 US11120190B2 (en) | 2017-11-21 | 2017-11-21 | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
| PCT/US2018/052369 WO2019103783A1 (en) | 2017-11-21 | 2018-09-24 | Metal zero power and ground post routing to reduce cell area and improve cell placement at the chip level |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022069531A Division JP7668763B2 (ja) | 2017-11-21 | 2022-04-20 | セル面積を縮小し、チップレベルでのセル配置を改善するための金属０電源接地スタブ経路（ｍｅｔａｌ ｚｅｒｏ ｐｏｗｅｒ ｇｒｏｕｎｄ ｓｔｕｂ ｒｏｕｔｅ） |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021504941A JP2021504941A (ja) | 2021-02-15 |
| JP2021504941A5 true JP2021504941A5 (https=) | 2021-10-28 |
| JP7062767B2 JP7062767B2 (ja) | 2022-05-06 |
Family
ID=63966083
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020527813A Active JP7062767B2 (ja) | 2017-11-21 | 2018-09-24 | セル面積を縮小し、チップレベルでのセル配置を改善するための金属０電源接地スタブ経路（ｍｅｔａｌ ｚｅｒｏ ｐｏｗｅｒ ｇｒｏｕｎｄ ｓｔｕｂ ｒｏｕｔｅ） |
| JP2022069531A Active JP7668763B2 (ja) | 2017-11-21 | 2022-04-20 | セル面積を縮小し、チップレベルでのセル配置を改善するための金属０電源接地スタブ経路（ｍｅｔａｌ ｚｅｒｏ ｐｏｗｅｒ ｇｒｏｕｎｄ ｓｔｕｂ ｒｏｕｔｅ） |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022069531A Active JP7668763B2 (ja) | 2017-11-21 | 2022-04-20 | セル面積を縮小し、チップレベルでのセル配置を改善するための金属０電源接地スタブ経路（ｍｅｔａｌ ｚｅｒｏ ｐｏｗｅｒ ｇｒｏｕｎｄ ｓｔｕｂ ｒｏｕｔｅ） |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US11120190B2 (https=) |
| EP (1) | EP3714384A1 (https=) |
| JP (2) | JP7062767B2 (https=) |
| KR (2) | KR20220103208A (https=) |
| CN (1) | CN111373407A (https=) |
| WO (1) | WO2019103783A1 (https=) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10304728B2 (en) | 2017-05-01 | 2019-05-28 | Advanced Micro Devices, Inc. | Double spacer immersion lithography triple patterning flow and method |
| US10747931B2 (en) | 2017-07-28 | 2020-08-18 | Advanced Micro Devices, Inc. | Shift of circuit periphery layout to leverage optimal use of available metal tracks in periphery logic |
| US11120190B2 (en) | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
| US10438937B1 (en) | 2018-04-27 | 2019-10-08 | Advanced Micro Devices, Inc. | Metal zero contact via redundancy on output nodes and inset power rail architecture |
| US10818762B2 (en) | 2018-05-25 | 2020-10-27 | Advanced Micro Devices, Inc. | Gate contact over active region in cell |
| US11055469B2 (en) | 2018-07-31 | 2021-07-06 | Taiwan Semiconductor Manufacturing Company Ltd. | Power structure with power pick-up cell connecting to buried power rail |
| US11030372B2 (en) * | 2018-10-31 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for generating layout diagram including cell having pin patterns and semiconductor device based on same |
| US10796061B1 (en) * | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
| US11652050B2 (en) | 2020-12-28 | 2023-05-16 | Advanced Micro Devices, Inc. | Inset power post and strap architecture with reduced voltage droop |
| CN113657071B (zh) * | 2021-08-31 | 2023-10-13 | 杭州广立微电子股份有限公司 | 一种自动修正mos器件漏电通路的方法 |
| US12205897B2 (en) | 2021-09-23 | 2025-01-21 | Advanced Micro Devices, Inc. | Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells |
| US11862640B2 (en) | 2021-09-29 | 2024-01-02 | Advanced Micro Devices, Inc. | Cross field effect transistor (XFET) library architecture power routing |
| US12308370B2 (en) | 2021-09-29 | 2025-05-20 | Advanced Micro Devices, Inc. | Cross field effect transistors (XFETs) in integrated circuits |
| US11848269B2 (en) * | 2021-10-04 | 2023-12-19 | Advanced Micro Devices, Inc. | Techniques to create power connections from floating nets in standard cells |
Family Cites Families (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5889329A (en) | 1994-11-02 | 1999-03-30 | Lsi Logic Corporation | Tri-directional interconnect architecture for SRAM |
| US5578840A (en) * | 1994-11-02 | 1996-11-26 | Lis Logic Corporation | Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry |
| US5932900A (en) * | 1997-06-20 | 1999-08-03 | Faraday Technology Corporation | Flexible cell for gate array |
| JP2005175505A (ja) | 1997-08-21 | 2005-06-30 | Renesas Technology Corp | 半導体集積回路装置 |
| US6285088B1 (en) * | 1998-05-13 | 2001-09-04 | Texas Instruments Incorporated | Compact memory circuit |
| DE102004014472B4 (de) | 2004-03-24 | 2012-05-03 | Infineon Technologies Ag | Anwendungsspezifischer integrierter Halbleiter-Schaltkreis |
| JP2007073885A (ja) | 2005-09-09 | 2007-03-22 | Renesas Technology Corp | 半導体集積回路 |
| US7761831B2 (en) | 2005-12-29 | 2010-07-20 | Mosaid Technologies Incorporated | ASIC design using clock and power grid standard cell |
| US9009641B2 (en) * | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| JP4322888B2 (ja) | 2006-06-01 | 2009-09-02 | エルピーダメモリ株式会社 | 半導体装置 |
| JP5293939B2 (ja) | 2007-07-25 | 2013-09-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US8063415B2 (en) | 2007-07-25 | 2011-11-22 | Renesas Electronics Corporation | Semiconductor device |
| JP2009170520A (ja) | 2008-01-11 | 2009-07-30 | Seiko Epson Corp | 集積回路装置のレイアウト方法、集積回路装置のレイアウトプログラム、集積回路装置のレイアウトシステム、集積回路装置及び電子機器 |
| US7984395B2 (en) | 2008-01-17 | 2011-07-19 | Synopsys, Inc. | Hierarchical compression for metal one logic layer |
| JP5410082B2 (ja) | 2008-12-12 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| US8533641B2 (en) * | 2011-10-07 | 2013-09-10 | Baysand Inc. | Gate array architecture with multiple programmable regions |
| KR20130070252A (ko) | 2011-12-19 | 2013-06-27 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자의 스페어 로직 구현방법 및 그 구조 |
| US8901615B2 (en) * | 2012-06-13 | 2014-12-02 | Synopsys, Inc. | N-channel and P-channel end-to-end finfet cell architecture |
| JP2014060355A (ja) | 2012-09-19 | 2014-04-03 | Renesas Electronics Corp | 半導体集積回路の設計方法、設計装置及び設計プログラム |
| US10283437B2 (en) | 2012-11-27 | 2019-05-07 | Advanced Micro Devices, Inc. | Metal density distribution for double pattern lithography |
| US9331013B2 (en) | 2013-03-14 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated capacitor |
| JP6160335B2 (ja) | 2013-07-29 | 2017-07-12 | スズキ株式会社 | 並列多気筒エンジン |
| WO2015025441A1 (ja) | 2013-08-23 | 2015-02-26 | パナソニック株式会社 | 半導体集積回路装置 |
| US20160276287A1 (en) | 2013-12-06 | 2016-09-22 | Renesas Electronics Corporation | Semiconductor device |
| JP2016046479A (ja) | 2014-08-26 | 2016-04-04 | マイクロン テクノロジー， インク． | 半導体装置及び半導体装置の設計方法とプログラム |
| KR102369511B1 (ko) | 2015-07-08 | 2022-03-03 | 삼성전자주식회사 | 반도체 집적 회로 및 이를 포함하는 전자 시스템 |
| US9846759B2 (en) * | 2015-07-30 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Global connection routing method and system for performing the same |
| US10672708B2 (en) | 2015-11-30 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standard-cell layout structure with horn power and smart metal cut |
| US9785740B2 (en) * | 2015-12-18 | 2017-10-10 | Arm Limited | Computer implemented system and method for modifying a layout of standard cells defining a circuit component |
| US10109619B2 (en) * | 2016-06-06 | 2018-10-23 | Qualcomm Incorporated | Methods and apparatus for using split N-well cells in a merged N-well block |
| US11189569B2 (en) | 2016-09-23 | 2021-11-30 | Advanced Micro Devices, Inc. | Power grid layout designs for integrated circuits |
| US9837398B1 (en) | 2016-11-23 | 2017-12-05 | Advanced Micro Devices, Inc. | Metal track cutting in standard cell layouts |
| US10270430B2 (en) * | 2016-12-28 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same |
| US10503859B2 (en) | 2017-08-30 | 2019-12-10 | Arm Limited | Integrated circuit design and/or fabrication |
| US20190103394A1 (en) * | 2017-09-29 | 2019-04-04 | Qualcomm Incorporated | Thermally conscious standard cells |
| US11120190B2 (en) | 2017-11-21 | 2021-09-14 | Advanced Micro Devices, Inc. | Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level |
| US10438937B1 (en) | 2018-04-27 | 2019-10-08 | Advanced Micro Devices, Inc. | Metal zero contact via redundancy on output nodes and inset power rail architecture |
-
2017
- 2017-11-21 US US15/819,879 patent/US11120190B2/en active Active
-
2018
- 2018-09-24 EP EP18793071.4A patent/EP3714384A1/en active Pending
- 2018-09-24 KR KR1020227023819A patent/KR20220103208A/ko active Pending
- 2018-09-24 WO PCT/US2018/052369 patent/WO2019103783A1/en not_active Ceased
- 2018-09-24 KR KR1020207016403A patent/KR102421671B1/ko active Active
- 2018-09-24 CN CN201880075186.3A patent/CN111373407A/zh active Pending
- 2018-09-24 JP JP2020527813A patent/JP7062767B2/ja active Active
-
2021
- 2021-09-13 US US17/473,039 patent/US12455999B2/en active Active
-
2022
- 2022-04-20 JP JP2022069531A patent/JP7668763B2/ja active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2021504941A5 (https=) | ||
| KR102741111B1 (ko) | 매립된 파워 공급 레일을 이용한 파워 분배 네트워크 | |
| Hossen et al. | Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu $ TSVs | |
| CN103000625B (zh) | 2.5d/3d集成电路系统的esd保护 | |
| US9558312B2 (en) | Electromigration resistant standard cell device | |
| US12354962B2 (en) | Standard cell layout for better routability | |
| JP2015507372A5 (https=) | ||
| US12341098B2 (en) | Metal patterning for internal cell routing | |
| JP2009521811A5 (https=) | ||
| WO2018074172A1 (ja) | 半導体集積回路装置 | |
| US20240332304A1 (en) | Semiconductor integrated circuit device | |
| US20130069236A1 (en) | Efficient semiconductor device cell layout utilizing underlying local connective features | |
| CN112100967A (zh) | 一种标准单元版图、标准单元库版图及布线方法 | |
| CN111987064A (zh) | 抽头单元和半导体单元 | |
| KR101355263B1 (ko) | 레이아웃 스킴 및 반도체 디바이스의 디바이스 셀들을 형성하는 방법 | |
| US9929095B2 (en) | IO power bus mesh structure design | |
| CN101546345B (zh) | 电源供应网的规划方法及其相关集成电路 | |
| TWI648836B (zh) | 帶有介面電路系統之積體電路及用於此類介面電路系統之介面單元 | |
| US20240347460A1 (en) | Semiconductor integrated circuit device | |
| US20210125917A1 (en) | Integrated circuit with cells having metal layer configured based on directions from which intercell metal interconnects connects to the metal layer | |
| JP2002280457A (ja) | 半導体集積回路およびその配置配線方法 |