Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/394—Routing
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/394—Routing
  • G06F30/3947—Routing global
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/90—Masterslice integrated circuits
  • H10D84/903—Masterslice integrated circuits comprising field effect technology
  • H10D84/907—CMOS gate arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/90—Masterslice integrated circuits
  • H10D84/903—Masterslice integrated circuits comprising field effect technology
  • H10D84/907—CMOS gate arrays
  • H10D84/968—Macro-architecture
  • H10D84/974—Layout specifications, i.e. inner core regions
  • H10D84/975—Wiring regions or routing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/427—Power or ground buses
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/06—Power analysis or power optimisation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
  • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

• FIG. 4 is a generalized diagram of a top view of a standard cell layout for an inverter.
• FIG. 6 is a generalized diagram of a method for creating power grid connections for a standard cell layout.
• a cell includes one or more input nodes in metal one, one or more output nodes in metal one, and each of a power post and a ground reference post in metal zero below the posts in metal one.
• the cell is a standard cell in a cell layout library.
• the cell is a custom cell created for a particular area of a chip design.
• the power and ground posts include no vias to any upper metal layers.
• the power and ground posts are routed in metal zero to a boundary edge of the cell.
• the place-and-route tool doesn’t need to perform a further routing step after placing the cells.
• FIG. 1 generalized block diagrams of top views of cell layout 102 and cell layout 104 are shown.
• the active regions are not shown in the cell layouts 102 and 104 for ease of illustration.
• cell layout 102 for an inverter without placement of metal one (Metal 1 or Ml) posts for a power and ground connections.
• Cell layout 102 has an input pin labeled as“IN” in metal one (Ml) 150, an output pin labeled as“OUT” in Ml 150, a power supply pin labeled as“VDD” in metal zero (M0) 130 and a ground reference pin labeled as“GND” in M0 130.
• each of cell layout 102 and cell layout 104 has posts in MetalO 130, which includes no vias to any upper metal layers.
• Global routing for cell layouts 102 and 104 in a floorplan with neighboring cells uses MetalO 130, rather than using the typical Metal2 170.
• Cell layout 104 has the same amount of on-die area as cell layout 102 despite cell layout 104 includes routing for power connections with neighboring cells.
• the vertical metal one (Metall or Ml) 150 is used for routing to provide flexible connections to horizontal metal 2 (M2 or Metal2) 170 for creating power and ground connections with neighboring cells.
• M2 or Metal2 horizontal metal 2
• cell layout 104 does not use any vertical posts in Metall 150 or horizontal posts in Metal2 170 for power connections.
• the layout design rule checks are revised to allow the use of the M0 extensions 132.
• the software layout tool performing the layout has the DRCs revised.
• the place-and-route tool places the cells so that the cells abut one another, but the place-and-route tool does not verify the layout within the cells.
• horizontal routes in MetalO 130 end prior to the cell boundary edge and at least a non-zero threshold distance from the cell boundary edge.
• the devices (transistors) in the cell layouts 102 and 104 are non- planar devices (transistors).
• Non-planar transistors are a recent development in semiconductor processing for reducing short channel effects. Tri-gate transistors, Fin field effect transistors
• FETs gate all around transistors
• the cell layouts 102 and 104 use metal gate 110 in a vertical direction, trench silicide contacts 120 for the source and drain regions in the vertical direction, metal 0 (M0 or MetalO) 130 for local interconnections in the horizontal direction, contacts 140 for connecting the metal gate 110 to MetalO 130 and contacts 142 for connecting the trench silicide contact 120 to MetalO 130.
• metal 0 M0 or MetalO
• a software place-and-route tool would place a copy of cell layout 102 on the die of a chip design, and later attempt to place a vertical post in Metall 150 for VDD, a via 160 for connecting the vertical power post in Metall 150 to horizontal Metal2 170, and then route the power horizontal Metal2
• cell layout 104 has four pins, which include the input pin“IN” in Metall (Ml) 150, the output pin“OUT” in Ml 150, the power supply pin“VDD” in MetalO (M0) 130 extended to the cell boundary and the ground reference pin“GND” in M0 130 extended to the cell boundary.
• Cell layout 104 also has three metal gates 110. The ratio of total pins to metal gates 110 is above unity, since the ratio is four pins to three metal gates 110. Rather than using horizontal Metall 170 for routing power reference posts to neighboring cells, routing the power reference posts for cell layout 104 to neighboring cells is done by the extending M0 posts 132 to the cell boundary.
• an extra metal gate 110 would be added to satisfy design rules.
• Design rules prevent a vertical post in Metall 150 from being within a threshold distance of the cell boundary edge.
• vertical posts in Metall 150 need to be within a threshold distance of vertical metal gates 110.
• the design rules are set by the fabrication process.
• the extra metal gate 110 would provide extra distance between the vertical post in Metall 150 and the cell boundary edge.
• the type of routing using an extension of the horizontal posts in MetalO 130 is illustrated in the upcoming cell layout 200 (of FIG. 2).
• cell layouts 200 include an inverter on the left and any one of a variety of complex gates on the right as a neighboring cell.
• each of the inverter and the neighboring cell is a standard cell in a cell layout library.
• one or more of the inverter and the neighboring cell is a custom designed cell, which is separate from the cell layout library.
• the cell layout for the inverter does not include horizontal MO extensions 132 for the power and ground connections.
• the horizontal power and ground tracks in MetalO 130 are aligned with the horizontal power and ground tracks in MetalO 130 in the complex gate. Therefore, the place-and-route tool is modified to place the inverter to the left of the complex gate and add the extra horizontal route in MetalO 130, rather than the horizontal Metal2 170, between the power connections of the inverter and the complex gate. Additionally, the place-and-route tool adds the extra horizontal route in MetalO 130, rather than the horizontal Metal2 170, between the ground connections of the inverter and the complex gate.
• power and ground connections are routed in metal zero to the boundary edge of the cell (block 506).
• the cell layout library is updated with new standard cells.
• the next steps are for floorplanning a chip design.
• a place-and-route tool is used to select standard cells from the library, place the standard cells next to neighboring cells, and globally route the power and ground connections. If no variations of qualified cells is needed for placement in the chip floorplan (“no” branch of the conditional block 508), then placement and routing is completed with cells using other metal layers than metal zero for power and ground connections (block 510). For example, in some embodiments, the metal two (M2) layer is used for the power and ground connections.
• M2 metal two
• a variation of one of the qualified cells is needed for placement in the chip floorplan (“yes” branch of the conditional block 508), then one of the multiple variations is selected based on a neighboring cell in the floorplan (block 512). The selected variation of the qualified cell is placed next to the neighbor cell and the place-and-route tool moves to the next cell placement without further power and ground routing (block 514). The power and ground connections are made in metal zero by abutment of the selected qualified cell and its neighboring cell.
• the cells that qualify include one or more of an inverter, a 2-input Boolean NAND gate and a 2-input Boolean NOR gate.
• the number of uses of standard cells for an inverter, a 2-input Boolean NAND gate and a 2-input Boolean NOR gate in a chip floorplan can be appreciable in many designs.
• a computer accessible storage medium includes any storage media accessible by a computer during use to provide instructions and/or data to the computer.

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• 2017
  • 2017-11-21 US US15/819,879 patent/US11120190B2/en active Active
• 2018
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