CN111373407A - 用于在芯片极减小单元面积并改进单元布局的金属零电源接地短截线布线 - Google Patents

用于在芯片极减小单元面积并改进单元布局的金属零电源接地短截线布线 Download PDF

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Publication number
CN111373407A
CN111373407A CN201880075186.3A CN201880075186A CN111373407A CN 111373407 A CN111373407 A CN 111373407A CN 201880075186 A CN201880075186 A CN 201880075186A CN 111373407 A CN111373407 A CN 111373407A
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power
metal layer
cell
metal
ground
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CN201880075186.3A
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Chinese (zh)
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理查德·T·舒尔茨
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/968—Macro-architecture
    • H10D84/974—Layout specifications, i.e. inner core regions
    • H10D84/975—Wiring regions or routing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN201880075186.3A 2017-11-21 2018-09-24 用于在芯片极减小单元面积并改进单元布局的金属零电源接地短截线布线 Pending CN111373407A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/819,879 2017-11-21
US15/819,879 US11120190B2 (en) 2017-11-21 2017-11-21 Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
PCT/US2018/052369 WO2019103783A1 (en) 2017-11-21 2018-09-24 Metal zero power and ground post routing to reduce cell area and improve cell placement at the chip level

Publications (1)

Publication Number Publication Date
CN111373407A true CN111373407A (zh) 2020-07-03

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880075186.3A Pending CN111373407A (zh) 2017-11-21 2018-09-24 用于在芯片极减小单元面积并改进单元布局的金属零电源接地短截线布线

Country Status (6)

Country Link
US (2) US11120190B2 (https=)
EP (1) EP3714384A1 (https=)
JP (2) JP7062767B2 (https=)
KR (2) KR20220103208A (https=)
CN (1) CN111373407A (https=)
WO (1) WO2019103783A1 (https=)

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CN113657071A (zh) * 2021-08-31 2021-11-16 杭州广立微电子股份有限公司 一种自动修正mos器件漏电通路的方法

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US10747931B2 (en) 2017-07-28 2020-08-18 Advanced Micro Devices, Inc. Shift of circuit periphery layout to leverage optimal use of available metal tracks in periphery logic
US11120190B2 (en) 2017-11-21 2021-09-14 Advanced Micro Devices, Inc. Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
US10438937B1 (en) 2018-04-27 2019-10-08 Advanced Micro Devices, Inc. Metal zero contact via redundancy on output nodes and inset power rail architecture
US10818762B2 (en) 2018-05-25 2020-10-27 Advanced Micro Devices, Inc. Gate contact over active region in cell
US11055469B2 (en) 2018-07-31 2021-07-06 Taiwan Semiconductor Manufacturing Company Ltd. Power structure with power pick-up cell connecting to buried power rail
US11030372B2 (en) * 2018-10-31 2021-06-08 Taiwan Semiconductor Manufacturing Company Ltd. Method for generating layout diagram including cell having pin patterns and semiconductor device based on same
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
US11652050B2 (en) 2020-12-28 2023-05-16 Advanced Micro Devices, Inc. Inset power post and strap architecture with reduced voltage droop
US12205897B2 (en) 2021-09-23 2025-01-21 Advanced Micro Devices, Inc. Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells
US11862640B2 (en) 2021-09-29 2024-01-02 Advanced Micro Devices, Inc. Cross field effect transistor (XFET) library architecture power routing
US12308370B2 (en) 2021-09-29 2025-05-20 Advanced Micro Devices, Inc. Cross field effect transistors (XFETs) in integrated circuits
US11848269B2 (en) * 2021-10-04 2023-12-19 Advanced Micro Devices, Inc. Techniques to create power connections from floating nets in standard cells

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113657071A (zh) * 2021-08-31 2021-11-16 杭州广立微电子股份有限公司 一种自动修正mos器件漏电通路的方法
CN113657071B (zh) * 2021-08-31 2023-10-13 杭州广立微电子股份有限公司 一种自动修正mos器件漏电通路的方法

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Publication number Publication date
KR20220103208A (ko) 2022-07-21
KR102421671B1 (ko) 2022-07-15
US12455999B2 (en) 2025-10-28
EP3714384A1 (en) 2020-09-30
JP7062767B2 (ja) 2022-05-06
US20210406439A1 (en) 2021-12-30
JP2022101634A (ja) 2022-07-06
JP7668763B2 (ja) 2025-04-25
JP2021504941A (ja) 2021-02-15
US20190155979A1 (en) 2019-05-23
WO2019103783A1 (en) 2019-05-31
KR20200087190A (ko) 2020-07-20
US11120190B2 (en) 2021-09-14

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