JP2021082710A - Method for manufacturing semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device capable of curving a shoulder of a trench while suppressing an adverse effect on a channel part of the semiconductor device.SOLUTION: A method for manufacturing a semiconductor device comprises a trench forming step, a depositing step, a first etching step, and a second etching step. The trench forming step forms a trench penetrating a source region and a body region from a surface of a semiconductor substrate and extending in a depth direction. A drift region of a first conductivity type, the body region of a second conductivity type, and the source region of the first conductivity type are arranged in this order in the semiconductor substrate along the depth direction of the semiconductor substrate. The depositing step deposits a protection film on the surface of the semiconductor substrate and on an inner surface of the trench. The first etching step exposes the shoulder of the trench by selectively etching a part of the protection film by subjecting the surface of the semiconductor substrate and the inner surface of the trench to isotropic dry etching. The second etching step curves the shoulder of the trench exposed from the protection film by subjecting the surface of the semiconductor substrate and the inner surface of the trench to isotropic dry etching.SELECTED DRAWING: Figure 1

Description

The technique disclosed herein relates to a method of manufacturing a semiconductor device including a trench gate.

Patent Document 1 discloses a semiconductor device in which the shoulder portion of a trench provided with a trench gate is curved. In the semiconductor device provided with such a trench gate, the electric field concentration in the shoulder portion is relaxed, and the leakage current between the gate and the source is reduced.

Japanese Unexamined Patent Publication No. 2006-228901

Patent Document 1 discloses a manufacturing method in which the shoulder portion of a trench is curved by isotropic dry etching. In this manufacturing method, since isotropic dry etching is performed with the side surface of the trench exposed, the upper part of the side surface of the trench is etched more than necessary, and there is a concern that the channel portion may be adversely affected.

The present specification provides a manufacturing method capable of making the shoulder portion of a trench curved while suppressing an adverse effect on the channel portion of the semiconductor device.

In the method for manufacturing a semiconductor device disclosed in the present specification, a first conductive type drift region, a second conductive type body region, and a first conductive type source region are arranged in this order along the depth direction of the semiconductor substrate. A trench forming step of forming a trench extending from the surface of the semiconductor substrate through the source region and the body region in the depth direction, and forming a protective film on the surface of the semiconductor substrate and the inner surface of the trench. A film forming step of forming a film and an isotropic dry etching are performed, and a first etching step of selectively etching a part of the protective film to expose the shoulder portion of the trench and an isotropic dry etching are carried out. A second etching step of forming the shoulder portion of the trench exposed from the protective film into a curved surface can be provided. Here, as long as the drift region, the body region, and the source region are arranged in this order along the depth direction of the semiconductor substrate, another semiconductor region may intervene between the regions. For example, a JFET resistance reduction region in which the concentration of the first conductive type impurity is higher than that in the drift region may be interposed between the drift region and the body region. The material of the semiconductor substrate is not particularly limited, and may be, for example, silicon carbide. In the first etching step of the manufacturing method, isotropic dry etching is performed with the protective film coated on the surface of the semiconductor substrate and the inner surface of the trench. At this time, the plasma concentrates on the protective film covering the shoulder portion of the trench, so that the protective film covering the shoulder portion of the trench is selectively removed. Therefore, in the second etching step to be performed next, isotropic dry etching can be performed with only the shoulder portion of the trench exposed. As a result, it is possible to prevent the upper portion of the side surface of the trench from being etched more than necessary. As described above, in the above manufacturing method, the shoulder portion of the trench can be curved while suppressing the influence on the channel portion of the semiconductor device.

In the second etching step of the manufacturing method, a type of etching gas having an etching rate for the semiconductor substrate higher than the etching rate for the protective film may be used. According to this manufacturing method, the shoulder portion of the trench can be curved while suppressing etching of the protective film. This satisfactorily prevents the upper part of the side surface of the trench from being etched more than necessary.

In the above manufacturing method, the first etching step and the second etching step may be the same step. According to this manufacturing method, the shoulder portion of the trench can be curved in a small number of steps.

The cross-sectional view of the main part of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part of the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part of the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part of the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part of the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part of the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part of the manufacturing process of the semiconductor device of this embodiment is schematically shown. The cross-sectional view of the main part of the manufacturing process of the semiconductor device of this embodiment is schematically shown.

As shown in FIG. 1, the semiconductor device 1 is a type of power semiconductor element called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is a drain electrode 22 that covers the semiconductor substrate 10 and the back surface 10a of the semiconductor substrate 10. A source electrode 24 that covers the surface 10b of the semiconductor substrate 10 and a trench gate 30 provided on the surface layer of the semiconductor substrate 10 are provided. The trench gates 30 are arranged in a striped shape, for example, when observed from a direction orthogonal to the surface 10b of the semiconductor substrate 10.

The semiconductor substrate 10 is a substrate made of silicon carbide (SiC), and has an n ⁺ type drain region 11, an n type drift region 12, a p-type electric field relaxation region 13, and an n ⁺ type JFET resistance reduction region 14. , P-type body region 15, p ⁺ -type body contact region 16 and n ⁺ -type source region 17.

The drain region 11 is arranged on the back layer portion of the semiconductor substrate 10 and is provided at a position exposed on the back surface of the semiconductor substrate 10. The drain region 11 is also a base substrate for epitaxially growing the drift region 12, which will be described later. The drain region 11 is in ohmic contact with the drain electrode 22 that covers the back surface of the semiconductor substrate 10.

The drift region 12 is provided on the drain region 11. The drift region 12 is formed by crystal growth from the surface of the drain region 11 by utilizing an epitaxial growth technique. The impurity concentration in the drift region 12 is constant in the thickness direction of the semiconductor substrate 10.

The electric field relaxation region 13 is provided so as to cover the bottom surface of the trench gate 30, and can relax the electric field concentrated on the bottom surface of the trench gate 30. In this cross section, the electric field relaxation region 13 is separated from the body region 15 by the drift region 12 and the JFET resistance reduction region 14. However, in a cross section (not shown), the electric field relaxation region 13 may be connected to the body region 15. The electric field relaxation region 13 is formed by ion-implanting a p-type impurity (for example, aluminum) toward the bottom surface of the trench for forming the trench gate 30 by using an ion implantation technique.

The JFET resistance reduction region 14 is provided between the drift region 12 and the body region 15, separates the drift region 12 and the body region 15, and is a region in which the concentration of n-type impurities is higher than that of the drift region 12. The JFET resistance reduction region 14 extends from the side surface of one trench gate 30 to the side surface of the other trench gate 30 between adjacent trench gates 30. The JFET resistance reduction region 14 is formed at a position where n-type impurities (for example, nitrogen) are ion-implanted toward the surface of the semiconductor substrate 10 using ion implantation technology and are in contact with both the drift region 12 and the body region 15. To.

The body region 15 is provided on the JFET resistance reduction region 14, and is arranged on the surface layer portion of the semiconductor substrate 10. The body region 15 is in contact with the side surface of the trench gate 30. The body region 15 is formed on the surface layer portion of the semiconductor substrate 10 by ion-implanting p-type impurities (for example, aluminum) toward the surface of the semiconductor substrate 10 by using the ion implantation technique.

The body contact region 16 is provided on the body region 15, is arranged on the surface layer portion of the semiconductor substrate 10, is provided at a position exposed on the surface of the semiconductor substrate 10, and is p-type rather than the body region 15. This is a region where the concentration of impurities is high. The body contact region 16 is in ohmic contact with the source electrode 24 that covers the surface 10b of the semiconductor substrate 10. The body contact region 16 is formed on the surface layer portion of the semiconductor substrate 10 by ion-implanting a p-type impurity (for example, aluminum) toward the surface of the semiconductor substrate 10 by using an ion implantation technique.

The source region 17 is provided on the body region 15, is arranged on the surface layer portion of the semiconductor substrate 10, and is provided at a position exposed on the surface 10b of the semiconductor substrate 10. The source region 17 is separated from the JFET resistance reduction region 14 by the body region 15. The source region 17 is in contact with the side surface of the trench gate 30. The source region 17 is in ohmic contact with the source electrode 24 that covers the surface 10b of the semiconductor substrate 10. The source region 17 is formed on the surface layer portion of the semiconductor substrate 10 by ion-implanting n-type impurities (for example, nitrogen) toward the surface of the semiconductor substrate 10 by using the ion implantation technique.

At the position where the source region 17 is provided, the shoulder portion 30a of the trench TR in which the trench gate 30 is embedded is curved. The shoulder portion 30a of the trench TR is a portion where the surface 10b of the semiconductor substrate 10 and the side surface of the trench gate 30 intersect. When the shoulder portion 30a of the trench TR is curved in this way, the electric field concentration in the shoulder portion 30a is relaxed, and the leakage current between the gate and the source is reduced.

The trench gate 30 extends from the surface 10b of the semiconductor substrate 10 along the depth direction (vertical direction of the paper surface) of the semiconductor substrate 10, and has a gate insulating film 32 and a gate electrode 34. The trench gate 30 penetrates the source region 17, the body region 15, and the JFET resistance reduction region 14 to reach the drift region 12. The gate insulating film 32 is silicon oxide. The gate electrode 34 is coated with a gate insulating film 32 and is polysilicon containing impurities.

Next, the operation of the semiconductor device 1 will be described with reference to FIG. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the trench gate 30 is grounded, the semiconductor device 1 is turned off. In the semiconductor device 1, the electric field relaxation region 13 is provided so as to cover the bottom surface of the trench gate 30. Therefore, the electric field concentration in the gate insulating film 32 on the bottom surface of the trench gate 30 is relaxed, and the semiconductor device 1 can have a high withstand voltage.

When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage equal to or higher than the threshold voltage that is more positive than the source electrode 24 is applied to the gate electrode 34 of the trench gate 30, the semiconductor device 1 is turned on. Is. At this time, an inversion layer is formed in a portion of the body region 15 that separates the source region 17 and the JFET resistance reduction region 14 so as to face the side surface of the trench gate 30. The electrons supplied from the source region 17 reach the JFET resistance reduction region 14 via the inversion layer. The electrons that have reached the JFET resistance reduction region 14 flow to the drift region 12 via the JFET resistance reduction region 14. When such a JFET resistance reduction region 14 is provided, a current can flow so as to bypass the depletion layer extending from the electric field relaxation region 13 into the drift region 12. Therefore, the increase in resistance due to such a depletion layer, that is, the increase in JFET resistance is suppressed. As described above, the semiconductor device 1 has a structure suitable for a miniaturized structure in which the pitch width of the trench gate 30 is narrow.

Next, a method of manufacturing the semiconductor device 1 will be described. First, as shown in FIG. 2, a semiconductor substrate in which a drain region 11, a drift region 12, a JFET resistance reduction region 14, a body region 15, and a source region 17 are arranged in this order along the depth direction of the semiconductor substrate 10. Prepare 10. The drain region 11 is exposed on the back surface 10a of the semiconductor substrate 10, and the source region 17 is exposed on the front surface 10b of the semiconductor substrate 10. A body contact region 16 is also formed between the source regions 17 on the surface layer portion of the semiconductor substrate 10. The semiconductor substrate 10 is crystal-grown from the drain region 11 to the drift region 12 by using the epitaxial growth technique, and then n-type impurities and p-type impurities are used toward the surface 10b of the semiconductor substrate 10 by using the ion implantation technique. Is ion-implanted to form a JFET resistance reduction region 14, a body region 15, a body contact region 16, and a source region 17.

Next, as shown in FIG. 3, the resist film 42 is patterned on the surface 10b of the semiconductor substrate 10 by using a photolithography technique. The resist film 42 is patterned so that a part of the source region 17 is exposed from the opening. Next, using the anisotropic dry etching technique, a trench TR extending from the surface 10b of the semiconductor substrate 10 exposed from the opening of the resist film 42 along the depth direction of the semiconductor substrate 10 is formed (trench forming step). .. The trench TR is formed so as to reach the drift region 12 from the surface 10b of the semiconductor substrate 10 through the source region 17, the body region 15, and the JFET resistance reduction region 14. The trench TR may be formed so as to penetrate the source region 17 and the body region 15 and its bottom surface is located in the JFET resistance reduction region 14.

Next, as shown in FIG. 4, using the ion implantation technique, p-type impurities (for example, aluminum) are ion-implanted into the drift region 12 exposed on the bottom surface of the trench TR, and the p-type impurities (for example, aluminum) are ion-implanted on the drift region 12. The electric field relaxation region 13 exposed on the bottom surface of the trench TR is formed.

Next, as shown in FIG. 5, a protective film 44 is formed so as to cover the surface 10b of the semiconductor substrate 10 and the side surfaces and the bottom surface of the trench TR by using the CVD technique (deposition step). The protective film 44 is a thin film made of silicon oxide and has a thickness of about 100 nm.

Next, as shown in FIG. 6, a part of the protective film 44 is etched by using an isotropic dry etching technique to form a shoulder portion 30a where the surface 10b of the semiconductor substrate 10 and the side surface of the trench TR intersect. Expose (first etching step). In this isotropic dry etching step, for example, CF ₄ / O ₂ gas is used as the etching gas. In this isotropic dry etching step, since the curvature of the corner portion of the protective film 44 covering the shoulder portion 30a of the trench TR is high, plasma is concentrated on the corner portion of the protective film 44, so that the protective film 44 is formed. The corners are selectively removed. In this way, the corners of the protective film 44 are self-selectively etched, and only the shoulder portion 30a of the trench TR is exposed from the protective film 44.

Next, as shown in FIG. 7, the shoulder portion 30a of the trench TR exposed from the protective film 44 is curved by using an isotropic dry etching technique (second etching step). In this isotropic dry etching step, for example, CF ₄ / O ₂ gas is used as the etching gas. Regarding the etching rate with CF ₄ / O ₂ gas, the etching rate of silicon carbide with respect to the semiconductor substrate 10 is higher than the etching rate of silicon oxide with respect to the protective film 44. Therefore, the shoulder portion 30a of the trench TR can be curved while suppressing the etching of the protective film 44. As a result, it is possible to prevent the upper portion of the side surface of the trench TR from being etched more than necessary. For example, if isotropic dry etching is performed while the inner surface of the trench TR is not coated with the protective film 44, the side surface of the trench TR is etched more than necessary, resulting in etching damage to the channel portion and an inclined channel portion. Therefore, there is a concern that the electron mobility of the channel portion may decrease. In this manufacturing method, since the side surface of the trench TR is suppressed from being etched more than necessary, it is possible to prevent such a situation from occurring.

The first etching step and the second etching step described above are the same continuous steps. That is, it is carried out continuously using the same CDE device and the same etching gas. Therefore, in reality, the corner portion of the protective film 44 is etched, and at the same time, the shoulder portion 30a of the trench TR is curved. In this respect as well, it is well suppressed that the side surface of the trench TR is etched more than necessary.

Next, as shown in FIG. 8, an etching technique is used to remove the protective film 44 that covers the inner surface of the trench TR. Next, the gate insulating film 32 is deposited in the trench TR by using the CVD technique. Next, the gate electrode 34 is filled in the trench by using the CVD technique. Finally, when the drain electrode 22 is formed on the back surface of the semiconductor substrate 10 and the source electrode 24 is formed on the front surface of the semiconductor substrate 10, the semiconductor device 1 is completed.

In the above manufacturing method, the protective film 44 is formed only for forming the trench TR into a curved surface. In the modified example of the above manufacturing method, for example, prior to the ion implantation step for forming the electric field relaxation region 13 shown in FIG. 4, a protective film for suppressing the introduction of aluminum is formed on the side surface of the trench TR. I have something to do. The protective film for preventing ion implantation may be used as the protective film 44. As a result, it is not necessary to form the protective film 44 only for forming the trench TR into a curved surface, and the manufacturing man-hours are reduced.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

1: Semiconductor device 10: Semiconductor substrate 11: Drain region 12: Drift region 13: Electric field relaxation region 14: JFET resistance reduction region 15: Body region 16: Body contact region 17: Source region 22: Drain electrode 24: Source electrode 30: Trench gate 30a: Shoulder 32: Gate insulating film 34: Gate electrode

Claims (4)

The source region and the source region are arranged from the surface of the semiconductor substrate in which the first conductive type drift region, the second conductive type body region, and the first conductive type source region are arranged in this order along the depth direction of the semiconductor substrate. A trench forming step of forming a trench that penetrates the body region and extends in the depth direction.
A film forming step of forming a protective film on the surface of the semiconductor substrate and the inner surface of the trench, and
The first etching step of performing isotropic dry etching and selectively etching a part of the protective film to expose the shoulder portion of the trench.
A method for manufacturing a semiconductor device, comprising a second etching step of performing isotropic dry etching to form a curved surface of the shoulder portion of the trench exposed from the protective film. The method for manufacturing a semiconductor device according to claim 1, wherein in the second etching step, a type of etching gas having an etching rate for the semiconductor substrate higher than the etching rate for the protective film is used. The method for manufacturing a semiconductor device according to claim 2, wherein the first etching step and the second etching step are the same steps. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the material of the semiconductor substrate is silicon carbide.

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