JP2021072301A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which a vertical crack that occurs in a bonding layer of the semiconductor device can be suppressed.SOLUTION: A substrate (11) of a semiconductor substrate (100) according to the present invention includes a semiconductor chip arrangement region where at least one semiconductor chip (1) is disposed. Between a base (7) and a second metal layer (4), a base bonding layer (6) and a third metal layer (8) with a smaller linear expansion coefficient than the base bonding layer (6) are provided. The base bonding layer (6) is held between the third metal layer (8) and at least one of the second metal layer (4) and the base (7). Around the third metal layer (8), a columnar part where the base bonding layer (6) is not held between the second metal layer (4) and the base (7) does not exist. In the plan view and the cross-sectional view of the semiconductor device, at least one outer periphery of the third metal layer (8) falls within the outer periphery of the semiconductor chip arrangement region.SELECTED DRAWING: Figure 4

Description

The present invention relates to a semiconductor device.

Semiconductor devices using IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effective Transistors), etc. are used as devices responsible for power conversion and control of electric vehicles, railway vehicles, power generation systems, etc. There is. Since the semiconductor chip becomes hot due to self-heating during operation of the semiconductor device, ensuring reliability against a heat load becomes an issue. In order to meet this demand, for example, the technique described in Patent Document 1-2 is used as a technique for improving heat dissipation and a technique for preventing the occurrence of cracks in the bonding material due to the difference in the coefficient of thermal expansion of the members. Are known.

JP-A-2019-54069 Japanese Unexamined Patent Publication No. 2015-167171

Until now, most of the main causes of cracks generated in the bonding material due to the repeated heat load acting on the semiconductor device are due to the shear deformation of the bonding material caused by the difference in the amount of thermal deformation of the member to be bonded. was.

However, in recent years, a phenomenon called vertical crack has been confirmed in a bonding material of a semiconductor device, which is completely different from the above-mentioned crack (hereinafter referred to as horizontal crack). Lateral cracks occur at the ends of the joint material because they are caused by shear stress, while vertical cracks occur near the central part of the joint material where the temperature is high. Vertical cracks are considered to be deterioration due to the formation of grain boundary voids in the solder, and the phenomenon is completely different from that of horizontal cracks, so new measures are required. Therefore, the inventor of the present application has discovered through experiments that the formation of grain boundary voids is accelerated by the temperature and stress of the vertical cracks generated in the high temperature portion of the semiconductor device. It was found that the stress reduction of is effective.

In view of the above problems, an object of the present invention is to provide a semiconductor device capable of suppressing vertical cracks generated in the bonding layer of the semiconductor device.

In one aspect of the semiconductor device of the present invention for solving the above problems, a semiconductor chip, a substrate, and a base are laminated in this order, and the substrate is formed with a first metal layer provided on the surface of the semiconductor chip. A semiconductor having a second metal layer provided on the surface on the base side and an insulating layer provided between the first metal layer and the second metal layer, and a substrate on which at least one semiconductor chip is arranged. It has a chip arrangement region, and has a chip bonding layer and a third metal layer having a linear expansion coefficient smaller than that of the chip bonding layer between the semiconductor chip and the first metal layer. A pillar portion in which a chip bonding layer is interposed between at least one of them and the third metal layer, and the chip bonding layer is not interposed between the semiconductor chip and the first metal layer around the third metal layer. Is not present, and when the plane and cross section of the semiconductor device are viewed, at least one outer periphery of the third metal layer is provided so as to be contained inside the outer periphery of the semiconductor chip arrangement region.

Further, in another aspect of the semiconductor device of the present invention for solving the above problems, the semiconductor chip, the substrate, and the base are laminated in this order, and the substrate is provided on the surface on the semiconductor chip side. It has one metal layer, a second metal layer provided on the surface on the base side, and an insulating layer provided between the first metal layer and the second metal layer, and the substrate has at least one semiconductor chip. It has a semiconductor chip arrangement region to be arranged, and has a chip bonding layer and a third metal layer having a linear expansion coefficient smaller than that of the chip bonding layer between the semiconductor chip and the first metal layer, and is a semiconductor chip and a first metal layer. A chip bonding layer is interposed between at least one of the 1 metal layers and the third metal layer, and a chip bonding layer is interposed between the semiconductor chip and the first metal layer around the third metal layer. It is characterized in that there is no pillar portion that does not disappear, and at least one outer periphery of the third metal layer is provided so as to fit inside the outer periphery of the semiconductor chip arrangement region when the plane and cross section of the semiconductor device are viewed. And.

More specific configurations of the present invention are described in the claims.

According to the present invention, it is possible to provide a semiconductor device capable of suppressing vertical cracks generated in the bonding layer of the semiconductor device.

Issues, configurations and effects other than those described above will be clarified by the description of the following embodiments.

Schematic cross-sectional view showing the structure of the first embodiment of the semiconductor device of the present invention. Top view of the semiconductor device of the present invention (first example) Top view of the semiconductor device of the present invention (second example) The figure which shows a part of FIG. Schematic cross-sectional view of a conventional semiconductor device FIG. 4 shows the magnitude of the amount of thermal deformation. Schematic diagram of a part of the semiconductor device of Comparative Example 1 Schematic diagram of a part of the semiconductor device of Comparative Example 2 Schematic diagram of a part of the semiconductor device of Comparative Example 3 Schematic diagram showing a comparison of the average normal stress distribution in the base bonding layer of the semiconductor device of the first embodiment of the present invention and the semiconductor device of Comparative Example 1. Schematic diagram showing a comparison of the average normal stress distributions of the semiconductor device of Comparative Example 2 and the semiconductor device of Comparative Example 1. Schematic diagram showing a comparison of the average normal stress distributions of the semiconductor device of Comparative Example 3 and the semiconductor device of Comparative Example 1. Schematic cross-sectional view showing the structure of the second embodiment of the semiconductor device of the present invention. Schematic cross-sectional view showing the structure of the third embodiment of the semiconductor device of the present invention. Schematic cross-sectional view showing the structure of the fourth embodiment of the semiconductor device of the present invention. Schematic cross-sectional view showing the structure of the fifth embodiment of the semiconductor device of the present invention. Schematic cross-sectional view showing the structure of the sixth embodiment of the semiconductor device of the present invention. Schematic cross-sectional view showing the structure of the seventh embodiment of the semiconductor device of the present invention. Schematic cross-sectional view showing the structure of the eighth embodiment of the semiconductor device of the present invention.

Hereinafter, embodiments suitable for carrying out the present invention will be described with reference to the drawings as appropriate. However, the present invention is not limited to the embodiments taken up here, and can be appropriately combined and improved without changing the gist.

<First Embodiment>
FIG. 1 is a schematic cross-sectional view showing the structure of the first embodiment of the semiconductor device of the present invention. The semiconductor device 100 has a laminated structure in which the semiconductor chip 1, the substrate 11, and the base 7 are joined to each other. FIG. 1 shows an embodiment in which one substrate 11 is provided on one base 7, but the number of substrates 11 mounted on one base 7 is not limited, and a plurality of substrates 11 may be mounted. ..

The semiconductor chip 1 is, for example, a power transistor or diode such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Transistor), and more specifically, for example, Si, SiC, or GaN is used. ..

The substrate 11 has a first metal layer 3, a second metal layer 4, and an insulating layer 5. The first metal layer 3 is provided on the surface of the substrate 11 on the semiconductor chip 1 side, and the second metal layer 4 is provided on the surface of the substrate 11 on the base 7 side. In other words, the semiconductor chip 1 is bonded to the surface of the first metal layer 3 via the chip bonding layer 2, and the base bonding layer 6 is bonded to the surface of the second metal layer 4. The insulating layer 5 is provided between the first metal layer 3 and the second metal layer 4.

As the material of the first metal layer 3 and the second metal layer 4, a metal material having good electrical conductivity and thermal conductivity is preferable. Specifically, Cu, Cu alloys, Al and Al alloys and the like are desirable. The insulating layer 5 is preferably made of a material having high insulating properties and thermal conductivity, and ceramics such as aluminum nitride, aluminum oxide, and silicon nitride are used, for example.

It is desirable that the base 7 has high rigidity and thermal conductivity. Specifically, Cu, Cu alloy, Al, Al alloy, AlSiC, MgSiC and the like are used.

A chip bonding layer 2 is provided between the semiconductor chip 1 and the substrate 11 (first metal layer 3), and a base bonding layer 6 is provided between the substrate 11 (second metal layer 4) and the base 7. Have. The chip bonding layer 2 and the base bonding layer 6 are preferably those having high thermal conductivity, such as solder containing Pb or Sn as a main component. For the chip bonding layer 2, a diffusion bonding material, a sintered bonding material of Cu nanoparticles or Ag nanoparticles, or the like may be used.

The first metal layer 3 is a part of an electric circuit, and is connected to the semiconductor chip 1 and the terminal 10 for electrical connection with the outside by using the wiring 12.

The semiconductor chip 1, the substrate 11, the chip bonding layer 2 and the base bonding layer 6 are housed in the case 9 and sealed by the sealing material 13. A material having high insulating properties, such as resin, is used for the case 9. As the sealing material 13, for example, a resin or a silicone gel having high insulating properties is used.

FIG. 2 is a top view (first example) of the semiconductor device of the present invention. FIG. 2 is a schematic top view of the semiconductor chips 1a, 1b, 1c, 1d, the first metal layer 3, and the insulating layer 5. As described above, a plurality of semiconductor chips 1 may be mounted on one substrate 11. Since the area of the substrate 11 on which the semiconductor chip 1 can be mounted is limited, the plurality of semiconductor chips 1 are generally arranged adjacent to each other to form the semiconductor chip arrangement region 14. The semiconductor chip arrangement region 14 is an region in which one or a plurality of semiconductor chips 1 (1a, 1b, 1c, 1d in FIG. 2) are arranged. The semiconductor chip arrangement region 14 is an region that overlaps the semiconductor chip 1 when there is one semiconductor chip 1, and an region that overlaps the semiconductor chip 1 when a plurality of semiconductor chips 1 are arranged adjacent to each other. The region between the semiconductor chips 1 arranged adjacent to each other is also included. The term “adjacent to each other” as used herein also includes an adjacency in the diagonal direction. For example, in FIG. 2, between semiconductor chips 1a and semiconductor chips 1b adjacent to each other, between semiconductor chips 1a and semiconductor chips 1c, between semiconductor chips 1b and semiconductor chips 1d, semiconductor chips 1c and semiconductor chips 1d. Includes between the semiconductor chip 1a and the semiconductor chip 1d and between the semiconductor chip 1b and the semiconductor chip 1c. The semiconductor chip arrangement region 14 is a portion of the semiconductor device 100 where the temperature is particularly high.

FIG. 3 is a top view (second example) of the semiconductor device of the present invention. FIG. 3 shows a schematic top view of the semiconductor chip 1, the first metal layer 3, and the insulating layer 5 in the same manner as in FIG. 2, and shows an arrangement example different from that in FIG. In FIG. 3, a plurality of substrates 11 are included. As shown in FIG. 3, in the semiconductor chip arrangement region 14, semiconductor chips 1 arranged on different substrates 11 may be adjacent to each other. The semiconductor chip arrangement region 14 shown in FIGS. 2 and 3 is a region that becomes particularly hot in the semiconductor device 100, and its shape differs depending on the layout of the semiconductor device 100.

FIG. 4 is a diagram showing a part of FIG. As shown in FIG. 4, in the semiconductor device of the present invention, the third metal layer 8 is arranged between the second metal layer 4 and the base 7. The third metal layer 8 is arranged so as to be located inside the outer periphery of the semiconductor chip arrangement region 14 when the plane and the cross section of the semiconductor device 100 are viewed. The shape of the third metal layer 8 is not particularly limited, and may be, for example, a polygonal prism, a polygonal pyramid, a cylinder, a cone, or a polygonal prism or a cylinder having a partial recess, etc. The shape may be included.

The coefficient of linear expansion of the base metal of the third metal layer 8 is preferably lower than the coefficient of linear expansion of the base bonding layer 6. For example, metals such as Cu, Al, Fe, Ni and W, metal alloys thereof, or composite materials of different materials such as CIC (Copper Invar Copper) clad material may be used. Further, the third metal layer 8 may be plated, for example, for the purpose of good bonding with the solder. In the present embodiment, the base bonding layer 6 is interposed between at least one of the second metal layer 4 and the base 7 and the third metal layer 8, and the film thickness of the third metal layer 8 is the base bonding layer 6. It is preferable that the film thickness is smaller than that of. If the film thickness of the third metal layer 8 is equal to or greater than the film thickness of the base bonding layer 6, the stress reducing effect of the high temperature portion described later may not be sufficiently obtained. As in the fifth embodiment described later, the film thickness of the third metal layer 8 may be larger than that of the base bonding layer 6.

FIG. 5 is a schematic cross-sectional view of a conventional semiconductor device. FIG. 5 illustrates the direction of in-plane stress acting on the base bonding layer 6 when the semiconductor chip 1 generates heat in the conventional structure without the third metal layer 8. The semiconductor chip 1 self-heats during operation, and the heat is conducted mainly toward the base 7, so that each member thermally expands. The base bonding layer 6 has a coefficient of linear expansion of about 25 to 29 ppm / K in the case of solder, for example, whereas the insulating layer 5 has a linear expansion coefficient of about 2 to 8 ppm when the material is ceramics, for example. When the materials of the first metal layer 3 and the second metal layer 4 are, for example, Cu, Cu alloy, Al, and Al alloy, the linear expansion coefficient is about 16 to 23 ppm / K. Therefore, the coefficient of linear expansion of the substrate 11 as a whole varies depending on the combination of thicknesses of each layer, but is about 10 to 20 ppm / K between the first metal layer 3, the second metal layer 4, and the insulating layer 5.

On the other hand, the base 7 is, for example, Cu, Cu alloy, Al, Al alloy, AlSiC, MgSiC or the like, and has a linear expansion coefficient of about 7 to 23 ppm. As described above, the coefficient of linear expansion of the base bonding layer 6 is relatively larger than the coefficient of linear expansion of the substrate 11 and the base 7. When the temperature rises due to the heat generation of the semiconductor chip 1, the base bonding layer 6 tries to thermally expand, but the deformation is restricted because the upper and lower surfaces are bonded to the member having a relatively low coefficient of linear expansion as described above. , The compressive stress in the direction indicated by the arrow in FIG. 5 acts on the in-plane direction of the base bonding layer 6. In the base bonding layer 6, immediately below the semiconductor chip arrangement region 14, the temperature becomes high due to heat conduction from the semiconductor chip 1, and the above-mentioned compressive stress acts, so that the formation of grain boundary voids in the solder is accelerated and vertical cracks occur. It becomes a factor.

FIG. 6 is a diagram showing the magnitude of the amount of thermal deformation in FIG. FIG. 6 is a schematic view showing the magnitude of the relative amount of thermal deformation of the base bonding layer 6 in the thickness direction when the semiconductor chip 1 generates heat in the present embodiment. Since the third metal layer 8 has a smaller coefficient of linear expansion than the base bonding layer 6, the base bonding layer in the region A where the base bonding layer 6 and the third metal layer 8 overlap when the cross section of the semiconductor device 100 is viewed. The amount of thermal expansion of 6 and the third metal layer 8 in the thickness direction is smaller than the amount of thermal expansion of the base bonding layer 6 other than the region A. Therefore, the region A of the base bonding layer 6 is pulled in the thickness direction from other than the region A. Therefore, tensile stress acts on the region A. As the average normal stress in the region A, the compressive stress shown in FIG. 5 is reduced by the tensile stress in the thickness direction, so that the average normal stress is reduced as compared with the case where the third metal layer 8 is not provided.

Next, the thermal stress reducing effect of the semiconductor device of the present invention will be described in comparison with the structure of the conventional semiconductor device. FIG. 7 is a schematic cross-sectional view showing a part of the semiconductor device of Comparative Example 1. The semiconductor device of Comparative Example 1 does not have the third metal layer 8 unlike the structure of the first embodiment of the present invention shown in FIG.

FIG. 8 is a schematic cross-sectional view showing a part of the semiconductor device of Comparative Example 2. Unlike the structure of the first embodiment of the present invention shown in FIG. 6, the structure of Comparative Example 2 has not only the third metal layer 8 but also the pillar portion 15 between the second metal layer 4 and the base 7. Have. The column portion 15 penetrates the base bonding layer 6 and is a metal material having high thermal conductivity such as Cu, Cu alloy, Al and Al alloy, and has a smaller coefficient of linear expansion than the base bonding layer 6. Consists of materials. The column portion 15 is in contact with or is integral with the second metal layer 4 and the base 7. By having the pillar portion 15, it becomes easy to make the thickness of the base bonding layer 6 uniform, so that it is possible to prevent the end portion of the base bonding layer 6 from becoming extremely thin. Therefore, there is an effect that so-called lateral cracks generated from the end portion of the base bonding layer 6 due to the shear stress caused by the difference in thermal deformation between the substrate 11 and the base 7 can be reduced. This is the same as the configuration described in Patent Document 1 described above.

FIG. 9 is a schematic cross-sectional view of a part of the semiconductor device of Comparative Example 3. 9 is different from the structure of the first embodiment of the present invention shown in FIG. 6, and when the cross section of the semiconductor device is viewed, the third metal layer 8 is located outside the outer circumference of the semiconductor chip arrangement region 14. By using a material having a higher thermal conductivity than that of the base bonding layer 6 as the material of the third metal layer 8, there is an effect of promoting heat diffusion and improving heat dissipation performance. This is the same as the configuration described in Patent Document 2 described above.

FIG. 10 is a schematic view showing a comparison of the average normal stress distribution in the base bonding layer 6 of the semiconductor device of the first embodiment of the present invention and the semiconductor device of Comparative Example 1. In Comparative Example 1 which does not have the third metal layer 8, the compressive stress indicated by the arrow in FIG. 5 is the dominant stress. When the semiconductor chip 1 generates heat, the temperature becomes higher in the region closer to the center of the semiconductor chip arrangement region 14, so that the compressive stress shown in FIG. 5 is also higher in the region closer to the center of the semiconductor chip arrangement region 14, which is a slightly mountainous distribution. It becomes. The closer to the center of the semiconductor chip arrangement region 14, the higher the temperature, and there is concern about vertical cracks. However, in the present invention, the stress in that region can be reduced and the effect of suppressing vertical cracks can be obtained.

FIG. 11 is a schematic diagram showing a comparison of the average normal stress distributions of the semiconductor device of Comparative Example 2 and the semiconductor device of Comparative Example 1. Since the column portion (the portion where the base bonding layer 6 does not intervene between the second metal layer 4 and the base 7) 15 of Comparative Example 2 has a smaller coefficient of linear expansion than that of the base bonding layer 6, the column portion 15 The amount of thermal expansion in the thickness direction is smaller than the amount of thermal expansion in the thickness direction of the region A shown in FIG. Therefore, the column portion 15 does not pull the region A in the thickness direction, but rather compresses the region A. Therefore, a sufficient effect of suppressing vertical cracks cannot be obtained.

FIG. 12 is a schematic diagram showing a comparison of the average normal stress distribution in the base bonding layer of the semiconductor device of Comparative Example 3 and the semiconductor device of Comparative Example 1. In Comparative Example 3, since the outer shape of the third metal layer 8 is located outside the outer shape of the semiconductor chip arrangement region 14, a sufficient stress reduction effect is obtained in a region near the center of the semiconductor chip arrangement region 14 where vertical cracks are a concern. As a result, the effect of suppressing vertical cracks cannot be obtained.

The present invention is particularly effective when the chip bonding layer 2 and the base bonding layer 6 are solders containing Sn as a main component. The major aspect of the present invention is that it is possible to prevent the occurrence of vertical cracks in a solder containing Sn as a main component, which has higher fatigue strength than a solder containing Pb as a main component and whose main component is Sn, in which vertical cracks are more likely to determine the joint life than horizontal cracks. It is one of the effects.

<Second Embodiment>
FIG. 13 is a schematic cross-sectional view showing the structure of the second embodiment of the semiconductor device of the present invention. In the second embodiment, the third metal layer 8 and the second metal layer 4 are integrated. The end of the third metal layer 8 may have a taper or the like. According to the second embodiment, the same effect as that of the first embodiment can be obtained, and the assembling property is improved.

<Third Embodiment>
FIG. 14 is a schematic cross-sectional view showing the structure of the third embodiment of the semiconductor device of the present invention. In the third embodiment, the third metal layer 8 and the base 7 are integrated. The end of the third metal layer 8 may have a taper or the like. According to the third embodiment, the same effect as that of the first embodiment can be obtained, and the assembling property is improved.

<Fourth Embodiment>
FIG. 15 is a schematic cross-sectional view showing the structure of the fourth embodiment of the semiconductor device of the present invention. The fourth embodiment has a convex portion 16 integrated with the base 7. The convex portion 16 is arranged so as to surround the third metal layer 8. According to the fourth embodiment, the same effect as that of the first embodiment can be obtained, and the position of the third metal layer 8 is displaced when the base bonding layer 6 is melted and bonded by reflow or the like at the time of assembly. Has the effect of preventing.

<Fifth Embodiment>
FIG. 16 is a schematic cross-sectional view showing the structure of the fifth embodiment of the semiconductor device of the present invention. The fifth embodiment has a recess 17 on the surface of the base 7 to be joined to the base bonding layer 6. When the semiconductor device is viewed from a plane, the outer shape of the recess 17 is located inside the outer circumference of the semiconductor chip arrangement region 14. The third metal layer 8 is arranged inside the recess 17. In the present embodiment, the film thickness of the third metal layer may be equal to or larger than the film thickness of the base bonding layer, but the base bonding layer 6 exists between the second metal layer 4 and the third metal layer 8. ..

According to the fifth embodiment, the same effect as that of the first embodiment can be obtained, and the position of the third metal layer 8 is displaced when the base bonding layer 6 is melted and bonded by reflow or the like at the time of assembly. Has the effect of preventing.

<Sixth Embodiment>
FIG. 17 is a schematic cross-sectional view showing the structure of the sixth embodiment of the semiconductor device of the present invention. The sixth embodiment has a recess 17 on the surface of the base 7 to be joined to the base bonding layer 6. When the semiconductor device is viewed from a plane, the outer shape of the recess 17 is located inside the outer circumference of the semiconductor chip arrangement region 14. The present embodiment has protrusions 18, which are integrated with the surface of the third metal layer 8 facing the base 7. The protrusion 18 is arranged inside the recess 17.

According to the sixth embodiment, the same effect as that of the first embodiment can be obtained, and the position of the third metal layer 8 is displaced when the base bonding layer 6 is melted and bonded by reflow or the like at the time of assembly. Has the effect of preventing.

<7th Embodiment>
FIG. 18 is a schematic cross-sectional view showing the structure of the seventh embodiment of the semiconductor device of the present invention. The seventh embodiment has a third metal layer 8 between the semiconductor chip 1 and the first metal layer 3. According to the seventh embodiment, the same effect as that of the first embodiment can be obtained in the chip bonding layer 2, and there is an effect of suppressing vertical cracks in the chip bonding layer 2.

<8th Embodiment>
FIG. 19 is a schematic cross-sectional view showing the structure of the eighth embodiment of the semiconductor device of the present invention. The eighth embodiment has a configuration in which the first embodiment and the seventh embodiment are combined, that is, both the chip bonding layer 2 and the base bonding layer 6 have the third metal layer 8. By having such a configuration, it is possible to prevent the occurrence of vertical cracks in both the chip bonding layer 2 and the base bonding layer 6.

<9th embodiment>
In FIG. 18, the third metal layer 8 and the semiconductor chip 1 may be integrated. The end of the third metal layer 8 may have a taper or the like. According to the ninth embodiment, the same effect as that of the seventh embodiment can be obtained, and the assembling property is improved.

<10th Embodiment>
In FIG. 18, the third metal layer 8 and the first metal layer 3 may be integrated. The end of the third metal layer 8 may have a taper or the like. According to the tenth embodiment, the same effect as that of the seventh embodiment can be obtained, and the assembling property is improved.

As described above, according to the present invention, it has been shown that a semiconductor device capable of suppressing vertical cracks generated in the bonding layer of the semiconductor device can be provided.

The present invention is not limited to the above-described examples, and includes various modifications. The above-described embodiment describes the present invention in an easy-to-understand manner, and is not necessarily limited to the one having all the configurations described. It is also possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

1,1a, 1b, 1c, 1d ... Semiconductor chip, 2 ... Chip bonding layer, 3 ... First metal layer, 4 ... Second metal layer, 5 ... Insulation layer, 6 ... Base bonding layer, 7 ... Base, 8 ... Third metal layer, 9 ... case, 10 ... terminal, 11 ... substrate, 12 ... wiring, 13 ... encapsulant, 14 ... semiconductor chip arrangement area, 15 ... pillar, 16 ... convex, 17 ... concave, 18 ... Protrusion, 100 ... Semiconductor device.

Claims (12)

The semiconductor chip, the substrate, and the base are laminated in this order,
The substrate is provided between the first metal layer provided on the surface on the semiconductor chip side, the second metal layer provided on the surface on the base side, and between the first metal layer and the second metal layer. With an insulating layer
The substrate has a semiconductor chip arrangement region in which at least one of the semiconductor chips is arranged.
Between the base and the second metal layer, there is a base bonding layer and a third metal layer having a linear expansion coefficient smaller than that of the base bonding layer, and at least one of the second metal layer and the base. A column in which the base bonding layer is interposed between the third metal layer and the third metal layer, and the base bonding layer is not interposed between the second metal layer and the base around the third metal layer. There is no part,
A semiconductor device characterized in that at least one outer circumference of the third metal layer is provided so as to be contained inside the outer circumference of the semiconductor chip arrangement region when the plane and the cross section of the semiconductor device are viewed. The semiconductor chip arrangement region is an region that overlaps the semiconductor chip when there is one semiconductor chip, and a region that overlaps the semiconductor chip when a plurality of the semiconductor chips are arranged adjacent to each other. The semiconductor device according to claim 1, wherein the region is between semiconductor chips arranged adjacent to each other. The semiconductor device according to claim 1, wherein the film thickness of the third metal layer is smaller than the film thickness of the base bonding layer. The semiconductor device according to claim 1, wherein the third metal layer and the second metal layer are integrated. The semiconductor device according to claim 1, wherein the third metal layer and the base are integrated. The semiconductor device according to claim 1, wherein the base has a convex portion protruding toward the base bonding layer, and the convex portion is provided so as to surround the third metal layer. The semiconductor device according to claim 1, wherein the base has a recess on the surface on which the base bonding layer is provided, and at least a part of the third metal layer is housed in the recess. The semiconductor chip, the substrate, and the base are laminated in this order,
The substrate is provided between the first metal layer provided on the surface on the semiconductor chip side, the second metal layer provided on the surface on the base side, and between the first metal layer and the second metal layer. With an insulating layer
The substrate has a semiconductor chip arrangement region in which at least one of the semiconductor chips is arranged.
A chip bonding layer and a third metal layer having a linear expansion coefficient smaller than that of the chip bonding layer are provided between the semiconductor chip and the first metal layer, and among the semiconductor chip and the first metal layer. The chip bonding layer is interposed between at least one of them and the third metal layer, and the chip bonding layer is interposed between the semiconductor chip and the first metal layer around the third metal layer. There is no pillar part that disappears,
A semiconductor device characterized in that at least one outer circumference of the third metal layer is provided so as to be contained inside the outer circumference of the semiconductor chip arrangement region when the plane and the cross section of the semiconductor device are viewed. The semiconductor chip arrangement region is an region that overlaps the semiconductor chip when there is one semiconductor chip, and a region that overlaps the semiconductor chip when a plurality of the semiconductor chips are arranged adjacent to each other. The semiconductor device according to claim 8, wherein the region is between semiconductor chips arranged adjacent to each other. The semiconductor device according to claim 8, wherein the film thickness of the third metal layer is smaller than the film thickness of the chip bonding layer. The semiconductor device according to claim 8, wherein the third metal layer and the semiconductor chip are integrated. The semiconductor device according to claim 8, wherein the third metal layer and the first metal layer are integrated.

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