JP2013219194A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2013219194A
JP2013219194A JP2012088671A JP2012088671A JP2013219194A JP 2013219194 A JP2013219194 A JP 2013219194A JP 2012088671 A JP2012088671 A JP 2012088671A JP 2012088671 A JP2012088671 A JP 2012088671A JP 2013219194 A JP2013219194 A JP 2013219194A
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Prior art keywords
semiconductor device
base body
convex portion
component
metal base
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JP2012088671A
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Japanese (ja)
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Hiroko Mori
寛子 森
Hiroshi Yamamoto
浩史 山本
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Sansha Electric Manufacturing Co Ltd
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Sansha Electric Manufacturing Co Ltd
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Priority to JP2012088671A priority Critical patent/JP2013219194A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of increasing the thickness of a soldered edge part that is easily deteriorated during a heat cycle test with a simple configuration and improving a fatigue tolerance dose of solder.SOLUTION: A semiconductor device 1 has a plate-like base body 2 having rigidity, and a component 3 mounted on the base body 2 with solder 4. In the semiconductor device 1 of this invention, the base body 2 has a protrusion part 2A formed in an area one size smaller than the area of the component 3 on the surface mounted with the component 3. The component 3 is matched to the center of the protrusion part 2A to be soldered onto the base body 2.

Description

この発明は、パワーモジュール等に用いられる半導体装置に関する。   The present invention relates to a semiconductor device used for a power module or the like.

金属ベース上に、半導体チップを半田付けすることで、金属ベースを介して放熱が促進されるようにした半導体装置が知られている。このような半導体装置は、ヒートサイクル試験時に、温度上昇と冷却を繰り返すと、半田層に疲労が蓄積し、半田が劣化して破壊に至る場合がある。   2. Description of the Related Art A semiconductor device is known in which heat radiation is promoted through a metal base by soldering a semiconductor chip on the metal base. In such a semiconductor device, if the temperature rise and cooling are repeated during the heat cycle test, fatigue may accumulate in the solder layer, and the solder may deteriorate and break down.

そこで、特許文献１では、ベース板の半導体チップ外周近傍に対向する位置に突起を設け、突起の外側に溝を形成するなどして、劣化が起こりやすい半田付け端部の厚みを調整し、疲労耐量を向上させている。   Therefore, in Patent Document 1, by adjusting the thickness of the soldering end portion where deterioration is likely to occur by providing a protrusion at a position facing the vicinity of the outer periphery of the semiconductor chip of the base plate and forming a groove on the outside of the protrusion. The tolerance is improved.

特開２００２−５７２８０号公報JP 2002-57280 A

上記特許文献１のように金属ベースに溝を形成する場合、横から見て金属ベースを半導体チップより長くする必要があるため、半導体装置の小型化を阻害する要因となる。   When the groove is formed in the metal base as in Patent Document 1, it is necessary to make the metal base longer than the semiconductor chip when viewed from the side, which is a factor that hinders downsizing of the semiconductor device.

また、半導体チップを金属ベースの両面に半田付けする場合、両面に溝を形成すると、溝部分の金属ベースが薄くなり、局所的に剛性が低下するので、金属ベースが変形しやすく、加工が難しくなる。   In addition, when soldering a semiconductor chip on both sides of a metal base, if grooves are formed on both sides, the metal base in the groove portion becomes thin and the rigidity is locally reduced, so the metal base is easily deformed and difficult to process. Become.

さらに、半導体チップとしてメサ等の耐圧保持構造がある場合、チップ端部と金属ベースとの距離が短く、放電しやすくなってしまう。特に半田量が多く、半田溶融時にパターンから流れた半田が金属ベースに付着して半田ボールになっているときなど、チップ端部と金属ベースとの距離が近くなるため、より放電しやすくなるという問題が生じる。   In addition, when the semiconductor chip has a pressure-resistant holding structure such as a mesa, the distance between the chip end and the metal base is short, and it becomes easy to discharge. In particular, when the amount of solder is large and the solder that flows from the pattern when the solder melts adheres to the metal base and forms a solder ball, the distance between the chip end and the metal base is reduced, which makes it easier to discharge. Problems arise.

本発明は上記課題に鑑みてなされたものであり、簡単な構成で、ヒートサイクル試験時に劣化しやすい半田付け端部の厚みを増すことが出来、半田の疲労耐量を向上させることが出来る半導体装置を提供することを目的とする。   The present invention has been made in view of the above problems, and has a simple structure, a semiconductor device capable of increasing the thickness of a soldering end portion that is likely to deteriorate during a heat cycle test, and improving the solder fatigue resistance. The purpose is to provide.

半導体装置は、剛性を有する板状のベース体と、ベース体上に半田付けにより搭載される部品と、を有する。そして、この発明の半導体装置では、ベース体は、部品搭載面に、部品面積よりもひとまわり小さい面積で形成される凸部を有し、部品は、凸部の中央に整合して前記ベース体上に半田付けされる。   The semiconductor device has a plate-like base body having rigidity and components mounted on the base body by soldering. In the semiconductor device of the present invention, the base body has a convex portion formed on the component mounting surface with an area slightly smaller than the component area, and the component is aligned with the center of the convex portion and the base body Soldered on top.

本発明では、半田付け端部の厚みを増すために、ベース体の対応する箇所に溝を形成する必要がない。よって、横から見てベース体を半導体チップより長くする必要がないため、半導体装置の小型化を実現可能である。また、ベース体の剛性が局所的に低下することがなく、ベース体の加工性を確保することが出来る。   In the present invention, in order to increase the thickness of the soldering end portion, it is not necessary to form a groove in a corresponding portion of the base body. Therefore, since it is not necessary to make the base body longer than the semiconductor chip when viewed from the side, it is possible to reduce the size of the semiconductor device. In addition, the base body rigidity is not locally reduced, and the workability of the base body can be ensured.

凸部はベース体と一体で形成することも可能であるし、ベース体に、ベース体と熱膨張係数の略等しい材質の板片を半田付けまたは接着することにより形成することも出来る。   The convex portion can be formed integrally with the base body, or can be formed by soldering or bonding a plate piece of a material having substantially the same thermal expansion coefficient as the base body to the base body.

凸部の形状は、立方体、直方体、円柱（いずれも断面形状が矩形。）の他、側面が鋭角の斜面に形成された立体（断面形状が底辺の長い台形。）としても良い。凸部の断面形状を台形とした場合は、ヒートサイクル試験時にベース体のエッジと半田とが当接する部分に集中する力が凸部の斜面に沿って分散されるため、半田がひび割れするのをより効果的に防止出来る。   The shape of the convex portion may be a cube, a rectangular parallelepiped, or a cylinder (all of which have a rectangular cross-sectional shape), or a solid (a trapezoid with a long cross-sectional shape) having a side surface formed on an inclined surface having an acute angle. When the cross-sectional shape of the convex part is a trapezoid, the force that concentrates on the part where the edge of the base body and the solder abuts during the heat cycle test is distributed along the slope of the convex part, so that the solder cracks. It can be prevented more effectively.

凸部がベース体の両面に形成されると、ベース体の表裏を有効利用してコンパクトに部品を搭載することが可能である。また、ベース体の使用量を減らせるため、コストの削減にもなる。   When the convex portions are formed on both sides of the base body, it is possible to mount components compactly by effectively using the front and back surfaces of the base body. In addition, since the amount of the base body used can be reduced, the cost can be reduced.

ベース体に搭載される部品としては、半導体チップの他、ＤＢＣ（Direct Bonding Copper）基板を用いることも出来る。また、ベース体にＤＢＣ基板を使用することも可能である。   As a component mounted on the base body, a DBC (Direct Bonding Copper) substrate can be used in addition to a semiconductor chip. It is also possible to use a DBC substrate for the base body.

この発明によれば、簡単な構成で、ヒートサイクル試験時に劣化しやすい半田付け端部の厚みを増すことが出来、半田の疲労耐量を向上させることが出来る。   According to the present invention, it is possible to increase the thickness of the soldering end portion that is likely to deteriorate during the heat cycle test with a simple configuration, and to improve the solder fatigue resistance.

は第１の実施形態に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to a first embodiment. は第２の実施形態に係る半導体装置を示す断面図である。These are sectional drawings showing a semiconductor device concerning a 2nd embodiment. は第３の実施形態に係る半導体装置を示す断面図である。These are sectional drawings which show the semiconductor device which concerns on 3rd Embodiment. は第４の実施形態に係る半導体装置を示す断面図である。These are sectional drawings showing a semiconductor device concerning a 4th embodiment. は第５の実施形態に係る半導体装置を示す断面図である。These are sectional views showing a semiconductor device concerning a 5th embodiment.

以下、図面を参照して本発明の実施の形態に係る半導体装置を説明する。   Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.

図１（Ａ）〜図１（Ｃ）は第１の実施形態に係る半導体装置を示す断面図である。図１（Ａ）〜図１（Ｃ）に示すように、第１の実施形態に係る半導体装置１は、金属ベース２および半導体チップ３を有する。   FIG. 1A to FIG. 1C are cross-sectional views showing the semiconductor device according to the first embodiment. As shown in FIGS. 1A to 1C, the semiconductor device 1 according to the first embodiment includes a metal base 2 and a semiconductor chip 3.

金属ベース２は熱伝導性の高い材料（例えば、銅）によって形成された剛性を有する板状の部材である。金属ベース２の半導体チップ３搭載面に凸部２Ａが形成され、凸部２Ａ上の中央に整合させて半導体チップ３が半田４で半田付けされる。凸部２Ａ上面の面積は、半導体チップ３の面積よりもひとまわり小さいサイズに設定されている。そのため、半導体チップ３の端部は、凸部２Ａよりも一段低い面で金属ベース２と半田付けされることになり、この部分の半田４の厚みを増すことになる。   The metal base 2 is a plate-like member having rigidity and formed of a material having high thermal conductivity (for example, copper). A convex portion 2A is formed on the surface of the metal base 2 on which the semiconductor chip 3 is mounted, and the semiconductor chip 3 is soldered with solder 4 in alignment with the center on the convex portion 2A. The area of the upper surface of the convex portion 2A is set to a size slightly smaller than the area of the semiconductor chip 3. Therefore, the end portion of the semiconductor chip 3 is soldered to the metal base 2 on a surface that is one step lower than the convex portion 2A, and the thickness of the solder 4 in this portion is increased.

本発明では、半田付け端部の厚みを増すために、金属ベース２の対応する箇所に溝を形成する必要がない。よって、横から見て金属ベース２を半導体チップ３より長くする必要がないため、半導体装置１の小型化を実現可能である。また、金属ベース２の剛性が局所的に低下することがなく、金属ベースの加工性を確保することが出来る。   In the present invention, it is not necessary to form a groove at a corresponding location on the metal base 2 in order to increase the thickness of the soldering end. Therefore, since it is not necessary to make the metal base 2 longer than the semiconductor chip 3 when viewed from the side, the semiconductor device 1 can be downsized. Further, the rigidity of the metal base 2 is not locally reduced, and the workability of the metal base can be ensured.

凸部２Ａは、金属ベース２の所望部分をエッチングしたり、プレス成形すれば、簡単に金属ベース２と一体形成することが出来る。   The convex portion 2A can be easily formed integrally with the metal base 2 by etching a desired portion of the metal base 2 or by press molding.

凸部２Ａの形状は、図１（Ａ）のような立方体、直方体、円柱（いずれも断面形状が矩形。）の他、図１（Ｂ）に示すように、側面が鋭角の斜面に形成された立体（断面形状が底辺の長い台形。）としても良い。図１（Ｂ）のように凸部２Ａの断面形状を台形とした場合は、ヒートサイクル試験時に金属ベース２のエッジと半田４とが当接する部分に集中する力が凸部２Ａの斜面に沿って分散されるため、半田４がひび割れするのをより効果的に防止出来る。   The shape of the convex portion 2A is a cube, a rectangular parallelepiped, and a cylinder (all of which are rectangular in cross section) as shown in FIG. 1A, and a side surface is formed on an inclined surface having an acute angle as shown in FIG. It may be a solid (a trapezoid with a long cross-sectional shape). When the cross-sectional shape of the convex portion 2A is a trapezoid as shown in FIG. 1B, the force concentrated on the portion where the edge of the metal base 2 and the solder 4 abuts along the slope of the convex portion 2A during the heat cycle test. Therefore, it is possible to more effectively prevent the solder 4 from cracking.

図１（Ｃ）に示すように、端部に耐圧保持構造がある半導体チップ３’を接合する場合でも、半導体チップ３を凸部２Ａで高い位置に持ち上げているため、半導体チップ３端部と金属ベース２の距離を長く取ることが出来、放電を効果的に防止出来る。金属ベース２上に半導体チップ３’を接合した後に、樹脂（不図示。）でモールドするが、金属ベース２とチップ端部との距離が離れているため、両者の隙間に樹脂が回りこみやすく、モールド加工が容易で、樹脂で確実に絶縁することが出来る。   As shown in FIG. 1C, even when the semiconductor chip 3 ′ having a pressure-resistant holding structure is joined to the end portion, the semiconductor chip 3 is lifted to a high position by the convex portion 2A. The distance of the metal base 2 can be increased, and discharge can be effectively prevented. After the semiconductor chip 3 'is bonded onto the metal base 2, it is molded with a resin (not shown). However, since the distance between the metal base 2 and the end of the chip is large, the resin easily flows into the gap between the two. It is easy to mold and can be reliably insulated with resin.

図１（Ａ）、図１（Ｂ）のように、端部に耐圧保持構造がない半導体チップ３を金属ベース２上に接合したものでは、半導体チップ３と金属ベース２との面積が等しい場合、全体でほぼ四角形状の周囲を樹脂でモールドするだけなので、モールドが容易に行える。   As shown in FIGS. 1A and 1B, when the semiconductor chip 3 having no pressure-resistant holding structure at the end is joined to the metal base 2, the areas of the semiconductor chip 3 and the metal base 2 are equal. Since the entire periphery of the substantially square shape is simply molded with resin, molding can be performed easily.

このような本発明の作用効果は以下に例示する種々の実施形態においても同様に得られることになる。   Such effects of the present invention can be obtained in the same manner in various embodiments exemplified below.

図２は、第２の実施形態に係る半導体装置を示す断面図である。図２に示すように、第２の実施形態に係る半導体装置１では、平板状の金属ベース２上に、金属ベース２と熱膨張係数の略等しい材質の板片５を半田６により接合することにより、金属ベース２とは異なる別部材で金属ベース２の半導体チップ３搭載面に凸部を形成したものである。なお、半田６に替えて接着剤を用いても良い。板片５は、金属ベース２と同一の材質で作製するのが好適である。   FIG. 2 is a cross-sectional view showing a semiconductor device according to the second embodiment. As shown in FIG. 2, in the semiconductor device 1 according to the second embodiment, a plate piece 5 made of a material having substantially the same thermal expansion coefficient as that of the metal base 2 is joined to the flat metal base 2 with solder 6. Thus, a convex portion is formed on the surface of the metal base 2 on which the semiconductor chip 3 is mounted using a different member than the metal base 2. Note that an adhesive may be used instead of the solder 6. The plate piece 5 is preferably made of the same material as the metal base 2.

この実施形態によると、凸部を形成するために金属ベース２を加工することが不要となる。   According to this embodiment, it is not necessary to process the metal base 2 to form the convex portion.

図３（Ａ）、図３（Ｂ）は、第３の実施形態に係る半導体装置を示す断面図である。図３（Ａ）、図３（Ｂ）に示すように、第３の実施形態に係る半導体装置１では、凸部２Ａを金属ベース２の上下両面に形成し、金属ベース２の両面に半導体チップ３を半田付けにより接合するようにしたものである。このようにしても、金属ベース２の強度が保たれるため、容易に加工することが出来る。   FIG. 3A and FIG. 3B are cross-sectional views showing a semiconductor device according to the third embodiment. As shown in FIGS. 3A and 3B, in the semiconductor device 1 according to the third embodiment, convex portions 2A are formed on both upper and lower surfaces of the metal base 2, and semiconductor chips are formed on both surfaces of the metal base 2. 3 is joined by soldering. Even if it does in this way, since the intensity | strength of the metal base 2 is maintained, it can process easily.

この実施形態によると、金属ベース２の表裏を有効利用してコンパクトに半導体チップ３を搭載することが可能である。また、金属ベース２の使用量を減らせるため、コストの削減にもなる。   According to this embodiment, it is possible to mount the semiconductor chip 3 compactly by effectively using the front and back of the metal base 2. Moreover, since the usage-amount of the metal base 2 can be reduced, it also becomes cost reduction.

図４は、第４の実施形態に係る半導体装置を示す断面図である。第４の実施形態に係る半導体装置１では、金属ベース２の凸部２Ａに接合される部品として、半導体チップ３に替えて、ＤＢＣ（Direct Bonding Copper）基板７を用いたものである。ＤＢＣ基板７は、図示のようにセラミック基板７１の表裏面に銅板７２，７３が張り合わされた構成である。   FIG. 4 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. In the semiconductor device 1 according to the fourth embodiment, a DBC (Direct Bonding Copper) substrate 7 is used in place of the semiconductor chip 3 as a component bonded to the convex portion 2A of the metal base 2. The DBC substrate 7 has a configuration in which copper plates 72 and 73 are bonded to the front and back surfaces of a ceramic substrate 71 as shown in the figure.

図５は、第５の実施形態に係る半導体装置を示す断面図である。第５の実施形態に係る半導体装置１では、ベース体として、金属ベース２の代わりに、上記ＤＢＣ基板７を用い、セラミック基板７１表面の銅板７２に半導体チップ３が接合される凸部７２Ａを形成したものである。   FIG. 5 is a cross-sectional view showing a semiconductor device according to the fifth embodiment. In the semiconductor device 1 according to the fifth embodiment, instead of the metal base 2, the DBC substrate 7 is used as a base body, and a convex portion 72 </ b> A where the semiconductor chip 3 is bonded to the copper plate 72 on the surface of the ceramic substrate 71 is formed. It is a thing.

以上、本発明によると、簡単な構成で、ヒートサイクル試験時に劣化しやすい半田付け端部の厚みを増すことが出来、半田の疲労耐量を向上させることが出来る。   As described above, according to the present invention, it is possible to increase the thickness of the soldered end portion that is likely to deteriorate during the heat cycle test with a simple configuration, and to improve the fatigue resistance of the solder.

上述の実施形態の説明は、すべての点で例示であって、制限的なものではないと考えられるべきである。この発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、この発明の範囲には、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The above description of the embodiment is to be considered in all respects as illustrative and not restrictive. The scope of the present invention is shown not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention is intended to include all modifications within the meaning and scope equivalent to the claims.

１…半導体装置
２…金属ベース
２Ａ…凸部
３…半導体チップ
４…半田
５…板片
７…ＤＢＣ基板
７１…セラミック基板
７２…銅板
７２，７３…銅板
７２Ａ…凸部 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Metal base 2A ... Convex part 3 ... Semiconductor chip 4 ... Solder 5 ... Plate piece 7 ... DBC substrate 71 ... Ceramic substrate 72 ... Copper plate 72, 73 ... Copper plate 72A ... Convex part

Claims (9)

剛性を有する板状のベース体と、
前記ベース体上に半田付けにより搭載される部品と、
を有する半導体装置において、
前記ベース体は、前記部品搭載面に、前記部品面積よりもひとまわり小さい面積で形成される凸部を有し、前記部品は、前記凸部の中央に整合して前記ベース体上に半田付けされる半導体装置。 A plate-like base body having rigidity;
A component mounted by soldering on the base body;
In a semiconductor device having
The base body has a convex portion formed on the component mounting surface with an area slightly smaller than the component area, and the component is soldered onto the base body in alignment with the center of the convex portion. Semiconductor device. 前記凸部は前記ベース体と一体で形成された、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the convex portion is formed integrally with the base body. 前記凸部は前記ベース体に、前記ベース体と熱膨張係数の略等しい材質の板片を半田付けまたは接着することにより形成された、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the convex portion is formed by soldering or bonding a plate piece made of a material having substantially the same thermal expansion coefficient as the base body to the base body. 前記凸部の断面形状が矩形である、請求項１〜３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein a cross-sectional shape of the convex portion is a rectangle. 前記凸部の断面形状が底辺の長い台形である、請求項１〜４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein a cross-sectional shape of the convex portion is a trapezoid having a long base. 前記凸部が前記ベース体の両面に形成された、請求項１〜５のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the convex portions are formed on both surfaces of the base body. 前記部品が半導体チップである、請求項１〜６のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the component is a semiconductor chip. 前記部品がＤＢＣ基板である、請求項１〜６のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the component is a DBC substrate. 前記ベース体がＤＢＣ基板である、請求項１〜７のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the base body is a DBC substrate.
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