JP2021027264A - Semiconductor device, manufacturing method of the same, and electronic device - Google Patents

Abstract

To provide a semiconductor device that ensures yield and reliability by suppressing an occurrence of cracks in a passivation film on a chip surface, a manufacturing method of the same, and an electronic device including the semiconductor device.SOLUTION: A semiconductor device includes a wiring with a slit, bumps on the wiring, and a chip having a passivation film on a surface of the bumps. In an area adjacent to the slit, the wiring is in contact with the bumps.SELECTED DRAWING: Figure 1

Description

The present embodiment relates to a semiconductor device, a method for manufacturing the same, and an electronic device including the semiconductor device.

In recent years, with the demand for higher functionality and miniaturization of electronic devices equipped with semiconductor devices, high-density integration and high-density mounting of electronic components such as semiconductor integrated circuits have been progressing. In general, in order to perform miniaturization and electrical connection of multi-pin electronic components, bonding with solder or mounting with a film such as an anisotropic conductive film (ACF) is generally performed. Use.

The method using ACF has a lower processing temperature at the time of mounting than the method using solder, and narrow pitch electrodes can be mounted collectively at the approximate electrode height, but pressure must be applied at the time of mounting. It has been difficult to mount a plurality of electronic components at once and to mount electronic components of different sizes adjacent to each other.

In addition, joining with solder has low connection resistance and high reliability as compared with crimping ACF for electrical conduction. In the joining method, the chips on which the bumps are formed are temporarily placed on the mounting portion of an FPC (Flexible printed circuits), and then the bumps are heated and melted by reflow to be electrically connected. The connecting portion of the bump is protected by filling and curing an underfill sealing resin between the chip and the FPC. However, in the method using solder, the processing temperature at the time of mounting is higher than in the method using ACF, and excessive stress is applied to the bumps on the chip due to the thermal expansion of the wiring such as copper on the film, and the chip surface. Cracks occur in the passivation film that protects the solder.

The cracks generated in the passivation film serve as an intrusion route of moisture from the outside, and the moisture corrodes the wiring and causes fluctuations in the characteristics of the chip, resulting in a decrease in the yield and reliability of the chip. For this reason, it has been difficult to secure the yield and reliability of the chips even in the construction method using bumps.

Japanese Unexamined Patent Publication No. 10-173005 Japanese Unexamined Patent Publication No. 2003-100809

DARBIN R. EDWARDS et al. , "Shear Stress Evaluation of Plastic Packages", IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. CHMT-12, NO. 4 p618-627, DECEMBER 1987

In the present embodiment, a slit is provided in the wiring in contact with the bump in order to suppress the occurrence of cracks generated in the passivation film. By adjusting the layout of the slit and the bump, the stress of the wiring around the bump at the time of heat crimping of the chip is reduced, and the load applied to the passivation film on the chip surface via the bump can be reduced. This makes it possible to suppress the occurrence of cracks that occur in the passivation film.

One aspect of the present embodiment provides a semiconductor device that suppresses the occurrence of cracks generated in the passivation film on the chip surface and secures the yield and reliability. In addition, another aspect of the present embodiment provides a method for manufacturing the semiconductor device. In addition, another aspect of the present embodiment provides an electronic device including the semiconductor device.

One embodiment of the present embodiment includes a wiring having a slit, a bump on the wiring, and a chip on the bump containing a passivation film on the surface, and the wiring is said to be in a region adjacent to the slit. It is a semiconductor device that comes into contact with bumps.

Further, another aspect of the present embodiment includes the wiring having the first slit and the second slit, the bump on the wiring, and the chip on the bump including the passion film on the surface. A semiconductor device in which the wiring is in contact with the bump in the region between the one slit and the second slit.

Further, another aspect of the present embodiment is an electronic device including the above-mentioned semiconductor device.

Further, another aspect of the present embodiment includes a step of crimping the wiring having the first slit and the second slit and the bump in contact with the chip, and between the first slit and the second slit. This is a method for manufacturing a semiconductor device in which the wiring is in contact with the bump in the above region.

According to the present embodiment, it is possible to provide a semiconductor device that suppresses the occurrence of cracks generated in the passivation film on the chip surface and secures the yield and reliability. Further, it is possible to provide a method for manufacturing the semiconductor device. Further, it is possible to provide an electronic device provided with the semiconductor device.

FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device of one aspect of the present embodiment. FIG. 3 is a plan layout view of the periphery of the chip of the semiconductor device according to the embodiment. FIG. 4 is an enlarged plan layout view of wiring in the chip peripheral portion of the semiconductor device according to the present embodiment. FIG. 5 is a schematic cross-sectional view of the periphery of the bump in the semiconductor device of one aspect of the present embodiment. FIG. 6 is a plan layout diagram illustrating the positional relationship between slits and bumps in the semiconductor device of one aspect of the present embodiment. FIG. 7 is a plan layout view of the periphery of the chip of the semiconductor device of this embodiment. FIG. 8 is a plan layout view of the semiconductor device of the present embodiment. FIG. 8A is a semiconductor device of sample 1 provided with wiring without a slit, and (b) L is 73 μm, W is 50 μm, and the short side of the slit. This is a sample 2 semiconductor device having a side length of 25 μm in the direction. 9A and 9B are plan layout views of the semiconductor device of this embodiment. FIG. 9A is a semiconductor device of sample 3 in which (a) L is 73 μm, W is 40 μm, and the length of the side of the slit in the lateral direction is 30 μm, and (b). ) This is a semiconductor device of Sample 4 in which L is 73 μm, W is 30 μm, and the length of the side of the slit in the lateral direction is 35 μm. FIG. 10 is a diagram for explaining the evaluation result of the crack occurrence frequency in the semiconductor device of this embodiment, and is a crack image of (a) sample 1 and (b) a crack image of sample 2. FIG. 11 is a diagram for explaining the evaluation result of the crack occurrence frequency in the semiconductor device of this embodiment, and is a crack image of (a) sample 3 and (b) a crack image of sample 4. FIG. 12 is a plan layout view of the semiconductor device of this embodiment. FIG. 13 is a schematic plan view of a conventional semiconductor device.

Next, the present embodiment will be described with reference to the drawings. In the description of the drawings described below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness of each component and the plane dimensions is different from the actual one. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that parts of the drawings having different dimensional relationships and ratios are included.

Further, the embodiments shown below exemplify devices and methods for embodying the technical idea, and do not specify the material, shape, structure, arrangement, etc. of each component. In this embodiment, various modifications can be made within the scope of claims.

One aspect of this embodiment is as follows.

[1] A semiconductor device comprising a wiring having a slit, a bump on the wiring, and a chip on the bump containing a passivation film on the surface, and the wiring is in contact with the bump in a region adjacent to the slit. ..

[2] The semiconductor device according to [1], wherein the ratio of the length of the side in the longitudinal direction of the slit to the length of the side in the longitudinal direction of the bump is 2.4 or more.

[3] The semiconductor device according to [1] or [2], wherein the side in the longitudinal direction of the slit is parallel to the side in the longitudinal direction of the wiring.

[4] The semiconductor device according to any one of [1] to [3], wherein the angle formed between the longitudinal side of the slit and the longitudinal side of the bump is 45 ° to 135 °. ..

[5] The semiconductor device according to any one of [1] to [4], wherein a part of the bump is superimposed on the slit.

[6] The ratio of the length of the side in the longitudinal direction of the slit to the length of the side in the lateral direction of the slit is 2.1 or less, according to any one of [1] to [5]. Semiconductor device.

[7] The wiring having the first slit and the second slit, the bump on the wiring, and the chip on the bump containing the passion film on the surface are provided, and the first slit and the second slit are provided. A semiconductor device in which the wiring contacts the bump in the intervening region.

[8] The semiconductor device according to [7], wherein the ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the longitudinal direction of the bump is 2.4 or more.

[9] The semiconductor device according to [8], wherein the ratio of the length of the side in the longitudinal direction of the second slit to the length of the side in the longitudinal direction of the bump is 2.4 or more.

[10] The semiconductor device according to any one of [7] to [9], wherein the first slit and the second slit have the same shape.

[11] The semiconductor device according to any one of [7] to [10], wherein the side in the longitudinal direction of the first slit is parallel to the side in the longitudinal direction of the wiring.

[12] The item according to any one of [7] to [11], wherein the angle formed between the longitudinal side of the first slit and the longitudinal side of the bump is 45 ° to 135 °. Semiconductor device.

[13] The semiconductor device according to any one of [7] to [12], wherein a part of the bump is superimposed on the first slit.

[14] The ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the lateral direction of the first slit is 2.1 or less, any one of [7] to [13]. The semiconductor device according to the section.

[15] The semiconductor device according to any one of [1] to [14], wherein the length of the side of the bump in the longitudinal direction is 25 to 35 μm.

[16] The semiconductor device according to any one of [1] to [15], wherein the bump contains gold.

[17] The semiconductor device according to any one of [1] to [16], wherein the wiring includes copper.

[18] The semiconductor device according to any one of [1] to [17], wherein the length of the side of the wiring in the lateral direction is 30 μm to 400 μm and shorter than the chip.

[19] An electronic device including the semiconductor device according to any one of [1] to [18].

[20] The wiring has a step of crimping the wiring having the first slit and the second slit and the bump in contact with the chip, and the wiring is the bump in the region between the first slit and the second slit. A method of manufacturing a semiconductor device that comes into contact with.

[21] The method for manufacturing a semiconductor device according to [20], wherein the ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the longitudinal direction of the bump is 2.4 or more.

[22] The method for manufacturing a semiconductor device according to [21], wherein the ratio of the length of the side in the longitudinal direction of the second slit to the length of the side in the longitudinal direction of the bump is 2.4 or more.

[23] The method for manufacturing a semiconductor device according to any one of [20] to [22], wherein the first slit and the second slit have the same shape.

[24] The method for manufacturing a semiconductor device according to any one of [20] to [23], wherein a part of the bump is superimposed on the first slit.

[25] The ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the lateral direction of the first slit is 2.1 or less, any one of [20] to [24]. The method for manufacturing a semiconductor device according to the section.

The semiconductor device and the manufacturing method thereof according to the present embodiment will be described with reference to the drawings.

FIGS. 1 to 6 show a semiconductor device according to an embodiment of the present embodiment. The semiconductor device of one embodiment of the present embodiment includes a film 1, a bump 2, a resist 3, an underfill material 4, a chip 10, a wiring 12, an output lead 14, and an input lead 16.

FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present embodiment, FIG. 2 is a schematic cross-sectional view of the semiconductor device according to the present embodiment, and FIG. FIG. 4 is an enlarged plan layout diagram of wiring around the chip peripheral portion of the semiconductor device of one embodiment of the present embodiment, and FIG. 5 is an enlarged plan layout diagram of the wiring around the chip of the semiconductor device of the present embodiment, and FIG. It is a schematic cross-sectional view of the periphery, and FIG. 6 is a plan layout diagram for explaining the positional relationship between the slit and the bump in the one-mode semiconductor device of the present embodiment.

As shown in FIG. 1, the semiconductor device of one aspect of the present embodiment includes a plurality of input leads 16 individually connected to each input terminal of the chip 10 and a plurality of individually connected to each output terminal of the chip 10. The output lead 14 of the above and the wiring 12 that superimposes on the chip 10 and directly supplies a signal to the power supply of the circuit unit included in the chip 10 are provided.

As shown in FIG. 13, the conventional semiconductor device has a configuration in which the wiring 12 is not provided, but the semiconductor device of one aspect of the present embodiment is provided with the wiring 12 in addition to the conventional configuration. The wiring 12 is thicker than the input lead 16 and the output lead 14, and can reduce the impedance in the longitudinal direction of the wiring 12 and suppress the generation of noise in the signal supplied from the wiring 12.

As shown in FIG. 3, the wiring 12 overlaps with the chip 10. As shown in FIG. 4, there are a plurality of wirings 12 in the peripheral portion of the chip 10, and in one embodiment of the present embodiment, five wirings are superimposed on the chip 10. In one embodiment of the present embodiment, a plurality of wirings 12 exist, but the wiring 12 is not limited to this, and only one wiring 12 may exist and may be superimposed on the chip 10. The length (thickness) of the side of the wiring 12 in the lateral direction is 30 to 400 μm, which is shorter than that of the chip 10.

Since the signal can be directly supplied to the power supply of the circuit portion in the chip 10 by using the wiring 12 without going through the internal wiring of the chip 10 itself, high-speed operation and electrical stability of the semiconductor device including the chip 10 are ensured. be able to.

A bump 2 is provided on the wiring 12. The bump 2 of the power supply wiring region 18 shown in FIG. 4 is electrically connected to the power supply wiring (not shown), and the bump 2 in the region other than the power supply wiring region 18 has a function as a support for supporting the film 1. If there are too many bumps 2 in a region other than the power supply wiring region 18, the pressure applied to the entire chip 10 becomes large, and the passivation film on the surface of the chip 10 is cracked. Further, when the underfill material 4 is formed, the resin to be the underfill material 4 is poured and sealed, but at this time, air bubbles are mixed in the resin or on the back side of the bump 2 (the side in the direction in which the resin flows). Since it is difficult for the resin to enter, voids may occur, which may affect the reliability of the semiconductor device. Further, since the bump 2 is formed of a material such as gold, it is preferable not to provide too many bumps 2 from the viewpoint of cost. On the other hand, if the number of bumps 2 in the area other than the power supply wiring area 18 is too small, the distance between the bumps 2 becomes wide, the film 1 bends, the film 1 cannot be supported, and the chip 10 and the film 1 come into contact with each other. It ends up. In consideration of these, it is preferable to appropriately adjust the arrangement and number of bumps 2. The pitch interval of the bumps 2 preferably has a region of, for example, 500 to 800 μm and a region of 100 to 600 μm.

Further, as shown in FIG. 5, the wiring 12 is provided so as to be sandwiched between the film 1 and the bump 2. For the film 1, for example, a polyimide having a thickness of 35 μm can be used. For the wiring 12, for example, copper or aluminum having a thickness of 8 μm can be used, and it is preferable to use copper from the viewpoint of conductivity. For the bump 2, for example, gold having a thickness of 12 to 18 μm can be used.

The chip 10 includes semiconductor integrated circuits such as ICs (Integrated Circuits) and LSIs (Large Scale Integration). A passivation film is provided on the surface of the chip 10, and the passivation film protects the chip 10.

The resist 3 has a function of preventing solder from adhering to other than the contacts that make an electrical connection and causing a short circuit. The resist 3 also functions as a spacer for adjusting the gap between the chip 10 and the surface of the film 1. The resist 3 has, for example, a thickness of 5 to 40 μm, preferably 10 to 30 μm.

The underfill material 4 can be appropriately selected according to the type of the solder material and its melting point. For the underfill material 4, for example, an epoxy resin can be used.

Here, the wiring 12 will be described in detail. The wiring 12 has a slit, and the slit has a function of reducing the stress of the wiring at the time of thermocompression bonding of the chip 10. FIG. 6 is a plan layout diagram illustrating the positional relationship between the slit 20 and the bump 2.

In the present embodiment, the wiring 12 has a plurality of slits 20, and the ratio of the length L of the side in the longitudinal direction to the length of the side in the lateral direction in each slit 20 is 2.1 or less. Further, the longitudinal side of each slit 20 is parallel to the longitudinal side of the wiring 12. In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, one of the slits 20 and the other slit 20 may be provided in parallel with each other separated from each other.

The bump 2 is in contact with the wiring 12 in the region 22 adjacent to the slit 20. The ratio of the length L of the longitudinal side of the slit 20 to the length W of the longitudinal side of the bump 2 in the region 22 is 2.4 or more. Further, the length W of the side in the longitudinal direction of the bump 2 in the region 22 is 25 to 35 μm. The length of the side of the bump 2 itself in the longitudinal direction is 50 to 200 μm. In the present embodiment, one bump 2 has a region that is in contact with the wiring 12 of the region 22 between the two slits 20 and overlaps with the slit 20, but the chip is not limited to this. As long as the configuration is such that the stress of the wiring 12 at the time of thermocompression bonding of 10 is reduced, the bump 2 may not overlap with the slit 20 or one bump 2 may be adjacent to one slit 20. The angle formed between the longitudinal side and the longitudinal side of the bump 2 may be 45 ° to 135 °. Further, each slit 20 may have the same shape or a different shape, but it is preferable that each slit 20 has the same shape from the viewpoint of simplifying the manufacturing process.

If thick wiring is used on the film described above, the wiring thermally expands during thermocompression bonding of the chip to be subjected to high temperature treatment, and the stress increases, and a load is applied to the passivation film on the chip surface via the bumps. By providing a slit in the wiring and adjusting the layout of the slit and the bump, the load applied to the passivation film on the chip surface can be reduced and the occurrence of cracks generated in the passivation film can be suppressed.

Here, a method for manufacturing the semiconductor device of the present embodiment will be described.

The wiring 12 and the resist 3 having the slits described above are formed on the film 1.

Next, a bump in contact with the chip 10 is formed.

Next, the slit 20 of the wiring 12 is aligned with the bump 2 in contact with the opposing chip, and the chip is mounted. As described above, the bump 2 is in contact with the wiring 12 in the region 22 adjacent to the slit 20. The pressure, temperature, time, and the like of the crimping when the chip 10 is mounted are appropriately adjusted.

Next, in the reflow furnace, heat treatment is performed in an atmosphere of an inert gas such as nitrogen to melt the bumps 2 and thermoset the resin to be the underfill material 4 filled between the film 1 and the chips to underfill. Form the material 4.

Through the above steps, the semiconductor device of the present embodiment can be manufactured.

In the semiconductor device of the present embodiment, a slit is provided in the wiring and the positions of the slit and the bump are adjusted to suppress the occurrence of cracks in the passivation film on the chip surface during thermocompression bonding of the chip, thereby ensuring the yield and reliability. can do.

Further, the semiconductor device of the present embodiment can be provided in an electronic device, for example, a smartphone, a tablet terminal, a personal computer, a wearable terminal, a data terminal, a bar code scanner, a battery charger, a surveillance camera, a gas alarm, a medical device, and the like. Healthcare equipment, industrial equipment such as robots, car navigation, engine control unit, electric power steering, in-vehicle equipment such as in-vehicle camera module, AV equipment such as TV, home theater, audio, inkjet head printer, air conditioner, refrigerator, rice cooker, It can be used in various applications such as home appliances such as dryers. By providing the semiconductor device of the present embodiment, it is possible to provide an electronic device that ensures yield and reliability.

[Other Embodiments]
As mentioned above, some embodiments have been described, but the statements and drawings that form part of the disclosure are exemplary and should not be understood to be limiting. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques. As described above, the present embodiment includes various embodiments not described here.

Hereinafter, the above-described embodiment will be described in more detail with reference to Examples, but the above-described embodiment is not limited to the following Examples.

In this embodiment, the frequency of cracks generated in the passivation film on the chip surface due to the difference in position between the slit and the bump in the above-mentioned semiconductor device was evaluated.

The semiconductor device used in this evaluation includes a film 1, a bump 2, a resist 3, a chip 10, and a wiring 12 as shown in the above-described embodiment. FIG. 7 shows a plan layout diagram around the chip of the semiconductor device used in this evaluation.

As the film 1, a polyimide film having a thickness of 8 μm was used. As the bump 2, a gold bump having a longitudinal side length of 80 μm, a lateral side length of 33 μm, and a thickness of 15 ± 3 μm was used. The resist 3 uses an insulating ink that protects the wiring circuit from foreign matter and moisture from the outside. As the wiring 12, copper wiring having a thickness of 200 to 400 μm and a thickness of 8 μm was used.

As shown in the above embodiment, the chip 10 is mounted on the wiring 12.

It should be noted that the sample 1 in which the wiring 12 shown in FIG. 8A is not provided with a slit, the length L of the side in the longitudinal direction of the slit 20 shown in FIG. 8B is 73 μm, and the bump in the region 22 (see FIG. 6). Sample 2, the length W of the side in the longitudinal direction of 2 is 50 μm, the length of the side of the slit 20 in the lateral direction is 25 μm, L shown in FIG. 9A is 73 μm, W is 40 μm, and the lateral direction of the slit. Sample 3 having a side length of 30 μm and Sample 4 having L of 73 μm, W of 30 μm, and the side length of the slit in the lateral direction of 35 μm shown in FIG. 9B were prepared and evaluated. The L / W of sample 2 was 1.5, the L / W of sample 3 was 1.8, and the L / W of sample 4 was 2.4. Further, in the slit 20, the ratio of the length L of the side in the longitudinal direction to the length of the side in the lateral direction was 2.9 for sample 2, 2.4 for sample 3, and 2.1 for sample 4.

The passivation film on the surface of the chip 10 after the chip 10 was mounted on the wiring 12 was observed using an optical microscope. The obtained optical micrographs are shown in FIGS. 10 and 11. 10 (a) is the surface of sample 1, FIG. 10 (b) is the surface of sample 2, FIG. 11 (a) is the surface of sample 3, and FIG. 11 (b) is the surface of sample 4. is there.

As shown in FIGS. 10 and 11, the sample 1 in which the wiring 12 is not provided with the slit has cracks 30 over a wide range. The frequency of cracks in Sample 1 was 92%. Further, cracks 30 are also generated in the samples 2 and 3 in which the wiring 12 is provided with slits. The frequency of occurrence of Sample 2 and Sample 3 was 78% and 57%, respectively. On the other hand, the occurrence of cracks could not be confirmed in the sample 4 in which the wiring 12 was provided with the slit. The frequency of cracks in Sample 4 was 14%, confirming that it was at a practical level. From the above evaluation results, it was confirmed that the frequency of crack occurrence was reduced by providing the wiring 12 with slits and increasing the L / W.

For example, it was suggested that the L / W could be made larger than that of sample 4, which is a practical level, and the frequency of crack occurrence could be reduced by adopting the configuration as shown in FIG.

1 ... film, 2 ... bump, 3 ... resist, 4 ... underfill material, 10 ... chip, 12 ... wiring, 14 ... output lead, 16 ... input lead, 18 ... power supply wiring area, 20 ... slit, 22 ... area, 30 ... crack

Claims (25)

Wiring with slits and
With the bump on the wiring
A chip having a passivation film on the surface of the bump is provided.
A semiconductor device in which the wiring is in contact with the bump in a region adjacent to the slit. The semiconductor device according to claim 1, wherein the ratio of the length of the side in the longitudinal direction of the slit to the length of the side in the longitudinal direction of the bump is 2.4 or more. The semiconductor device according to claim 1 or 2, wherein the side in the longitudinal direction of the slit is parallel to the side in the longitudinal direction of the wiring. The semiconductor device according to any one of claims 1 to 3, wherein the angle formed between the longitudinal side of the slit and the longitudinal side of the bump is 45 ° to 135 °. The semiconductor device according to any one of claims 1 to 4, wherein a part of the bump is superimposed on the slit. The semiconductor device according to any one of claims 1 to 5, wherein the ratio of the length of the side in the longitudinal direction of the slit to the length of the side in the lateral direction of the slit is 2.1 or less. Wiring with a first slit and a second slit,
With the bump on the wiring
A chip having a passivation film on the surface of the bump is provided.
A semiconductor device in which the wiring is in contact with the bump in the region between the first slit and the second slit. The semiconductor device according to claim 7, wherein the ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the longitudinal direction of the bump is 2.4 or more. The semiconductor device according to claim 8, wherein the ratio of the length of the side in the longitudinal direction of the second slit to the length of the side in the longitudinal direction of the bump is 2.4 or more. The semiconductor device according to any one of claims 7 to 9, wherein the first slit and the second slit have the same shape. The semiconductor device according to any one of claims 7 to 10, wherein the side in the longitudinal direction of the first slit is parallel to the side in the longitudinal direction of the wiring. The semiconductor device according to any one of claims 7 to 11, wherein the angle formed between the longitudinal side of the first slit and the longitudinal side of the bump is 45 ° to 135 °. The semiconductor device according to any one of claims 7 to 12, wherein a part of the bump is superimposed on the first slit. The semiconductor according to any one of claims 7 to 13, wherein the ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the lateral direction of the first slit is 2.1 or less. apparatus. The semiconductor device according to any one of claims 1 to 14, wherein the length of the side in the longitudinal direction of the bump is 25 to 35 μm. The semiconductor device according to any one of claims 1 to 15, wherein the bump contains gold. The semiconductor device according to any one of claims 1 to 16, wherein the wiring includes copper. The semiconductor device according to any one of claims 1 to 17, wherein the length of the side of the wiring in the lateral direction is 30 to 400 μm and shorter than the chip. An electronic device including the semiconductor device according to any one of claims 1 to 18. It has a step of crimping a wiring having a first slit and a second slit and a bump in contact with a chip.
A method for manufacturing a semiconductor device in which the wiring contacts the bump in the region between the first slit and the second slit. The method for manufacturing a semiconductor device according to claim 20, wherein the ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the longitudinal direction of the bump is 2.4 or more. The method for manufacturing a semiconductor device according to claim 21, wherein the ratio of the length of the side in the longitudinal direction of the second slit to the length of the side in the longitudinal direction of the bump is 2.4 or more. The method for manufacturing a semiconductor device according to any one of claims 20 to 22, wherein the first slit and the second slit have the same shape. The method for manufacturing a semiconductor device according to any one of claims 20 to 23, wherein a part of the bump is superimposed on the first slit. The semiconductor according to any one of claims 20 to 24, wherein the ratio of the length of the side in the longitudinal direction of the first slit to the length of the side in the lateral direction of the first slit is 2.1 or less. Manufacturing method of the device.