JP2020096020A - Semiconductor device and data transfer method of the same - Google Patents

Abstract

To provide a semiconductor device capable of suitably communicating between chips.SOLUTION: The semiconductor device includes a first chip, a second chip, a third chip, a fourth chip, and a substrate on which the first to fourth chips are respectively mounted. The first chip is disposed adjacent to the second chip and the fourth chip. The third chip is disposed adjacent to the second chip and the fourth chip at a position different from that of the first chip. The second chip includes a first transfer circuit for transferring data from the first chip to the third chip. The fourth chip includes a second transfer circuit for transferring data from the third chip to the first chip.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor device and a data transfer method for the semiconductor device.

A multi-chip module type semiconductor device in which a plurality of chips are mounted on a substrate is known. For example, in a multi-chip module in which a plurality of chips are arranged on a substrate such as a silicon interposer, the chips are electrically connected using wiring formed in a wiring layer of the substrate.

JP, 2011-86820, A

An embodiment of the present invention has an object to provide a semiconductor device capable of favorably performing communication between chips.

To achieve the above object, a semiconductor device according to an embodiment of the present invention includes a first chip, a second chip, a third chip, a fourth chip, and the first to fourth chips. A semiconductor device comprising a mounted substrate, wherein the first chip is arranged adjacent to the second chip and the fourth chip, and the third chip is the second chip. Second chip is arranged adjacent to the fourth chip and the fourth chip at a position different from that of the first chip, and the second chip transfers data from the first chip to the third chip. And a second transfer circuit that transfers data from the third chip to the first chip.

It is a block diagram showing an example of a semiconductor device in one embodiment of the present invention. FIG. 3 is a block diagram showing an example of a transfer circuit of FIG. 1 and circuits around it. It is explanatory drawing which shows typically the example which mutually connects the bump provided in the chip of FIG. 1 with a signal line (wiring). FIG. 6 is a block diagram showing, as a comparative example, an example in which two chips located on a diagonal line are connected by a signal line without providing the transfer circuit shown in FIG. 1 in each chip. It is a block diagram which shows the example of the semiconductor device in another embodiment of this invention. It is a block diagram which shows the example of the semiconductor device in another embodiment of this invention. FIG. 6 is a perspective view showing an example of a system board on which the semiconductor device of FIG. 5 is mounted. It is a block diagram which shows the example of the semiconductor device in another embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the code indicating the signal line is also used as a signal name (data name). Further, in the following, unless otherwise specified, in a plan view (for example, when viewed in a direction in which the board BRD shown in FIG. 1 and the chips CP (CP1-CP4) arranged and mounted on the board BRD overlap each other). I will explain.

FIG. 1 is a block diagram showing an example of a semiconductor device according to an embodiment of the present invention. The semiconductor device SEM1 shown in FIG. 1 includes four semiconductor chips CP (first chip CP1, a substantially square-shaped (rectangular type) having four sides arranged in two rows and two columns in a plan view on the substrate BRD. The second chip CP2, the third chip CP3, the fourth chip CP4, and hereinafter may be simply referred to as the chip CP1, the chip CP2, the chip CP3, and the chip CP4, respectively). That is, the chips CP1 to CP4 are provided at different positions on the substrate BRD in plan view.

For example, each of the chips CP1 to CP4 is connected to a terminal of the substrate BRD via a bump provided on the back surface which is a surface facing the substrate BRD. It should be noted that components (electronic components, mechanical components) other than the chips CP1 to CP4 may be mounted on the substrate BRD. Further, for example, each of the chips CP1 to CP4 may have a plurality of arithmetic units each including an arithmetic unit and a memory. The computing unit is a product sum computing unit, an inner product computing unit, or the like.

The chips CP1 and CP3 are located on the first diagonal D1 which is one diagonal of the rectangular substrate BRD which is the arrangement region of the chips CP1 to CP4, and the chips CP2 and CP4 are the other diagonal of the substrate BRD. It is located on the second diagonal D2. Hereinafter, the first diagonal line D1 and the second diagonal line D2 may be simply referred to as diagonal lines D1 and D2, respectively. Further, when the diagonal lines D1 and D2 are described without distinction, they may be referred to as the diagonal line D. In the present embodiment, the outer shape of the substrate BRD in plan view and the shape of the arrangement region of the chips CP1 to CP4 are the same. That is, the diagonal line of the substrate BRD and the diagonal lines D1 and D2 of the arrangement region of the chips CP1 to CP4 coincide with each other. In the present specification, the fact that the chip CP is located on the diagonal line D of the substrate BRD means that the chip CP arranged in a plan view and the diagonal line D of the substrate BRD overlap each other, and a corner portion of the chip CP is It is not limited to being on the diagonal line D of the BRD.

The chip CP1 has an internal circuit INT1 and a transfer circuit TR1, and the chip CP2 has an internal circuit INT2 and a transfer circuit TR2. The chip CP3 has an internal circuit INT3 and a transfer circuit TR3, and the chip CP4 has an internal circuit INT4 and a transfer circuit TR4. In the following, each of internal circuits INT1-INT4 may be referred to as internal circuit INT, and each of transfer circuits TR1-TR4 may be referred to as transfer circuit TR.

The internal circuit INT1 of the first chip CP1 and the internal circuit INT2 of the second chip CP2, which are adjacent to each other with their sides facing each other, are connected via signal lines S12 and S21 provided on the substrate BRD. It The first chip CP1 has an input/output circuit IO12 that inputs and outputs signals such as data to the signal lines S12 and S21, and the second chip CP2 inputs and outputs signals such as data to the signal lines S12 and S21. It has an input/output circuit IO21.

The internal circuit INT2 of the second chip CP2 and the internal circuit INT3 of the third chip CP3, which are adjacent to each other with their respective sides facing each other, are connected via signal lines S23 and S32 provided on the substrate BRD. It The second chip CP2 has an input/output circuit IO23 that inputs and outputs signals such as data to the signal lines S23 and S32, and the third chip CP3 inputs and outputs signals such as data to the signal lines S23 and S32. It has an input/output circuit IO32.

The internal circuit INT3 of the third chip CP3 and the internal circuit INT4 of the fourth chip CP4, which are adjacent to each other with their sides facing each other, are connected via signal lines S34 and S43 provided on the substrate BRD. It The third chip CP3 has an input/output circuit IO34 that inputs and outputs signals such as data to the signal lines S34 and S43, and the fourth chip CP4 inputs and outputs signals such as data to the signal lines S34 and S43. It has an input/output circuit IO43.

The internal circuit INT4 of the fourth chip CP4 and the internal circuit INT1 of the first chip CP1 that are adjacent to each other with their sides facing each other are connected via signal lines S41 and S14 provided on the substrate BRD. It The fourth chip CP4 has an input/output circuit IO41 that inputs and outputs signals such as data to the signal lines S41 and S14, and the first chip CP1 inputs and outputs signals such as data to the signal lines S41 and S14. It has an input/output circuit IO14. The signal lines S12, S21, S23, S32, S34, S43, S41, S14 are connected to, for example, bumps BP (FIG. 3) provided in each chip CP. In the following, when various signal lines are described without distinction, they may be referred to as signal lines S.

On the other hand, a signal line S13a provided on the substrate BRD is provided between the first chip CP1 and the third chip CP3, which are arranged on the first diagonal D1 of the substrate BRD with their corners facing each other. The first transfer circuit TR2 of the second chip CP2 is connected to the signal line S13b provided on the substrate BRD. In addition, between the third chip CP3 and the first chip CP1, a signal line S31a provided on the substrate BRD, a second transfer circuit TR4 of the fourth chip CP4, and a signal line S31b provided on the substrate BRD are provided. Connected through.

The signal lines S24a provided on the substrate BRD and the third chip CP2 and the fourth chip CP4 located on the second diagonal line D2 of the substrate BRD, which are arranged so that their corners face each other, and the third line The third transfer circuit TR3 of the chip CP3 is connected to the signal line S24b provided on the substrate BRD. A signal line S42a provided on the substrate BRD, a fourth transfer circuit TR1 of the first chip CP1 and a signal line S42b provided on the substrate BRD are provided between the fourth chip CP4 and the second chip CP2. Connected through. Hereinafter, the first transfer circuit TR2, the second transfer circuit TR4, the third transfer circuit TR3, and the fourth transfer circuit TR1 may be simply referred to as transfer circuits TR2, TR4, TR3, and TR1, respectively.

With the above configuration, the semiconductor device SEM1 can mutually communicate signals such as data among the four chips CP1 to CP4. For this reason, for example, when performing an arithmetic operation using a plurality of arithmetic units mounted on each of the chips CP1 to CP4, it is possible to input/output data and arithmetic results used by the arithmetic units to all the other chips CP. it can. Therefore, the semiconductor device SEM1 is suitable for, for example, machine learning for performing data processing using a large number of data and a large number of parameters, particularly deep learning using a neural network.

The arrow attached to each signal line S indicates the transfer direction of the signal transmitted to the signal line S, and the symbol "/" attached to each signal line S indicates that the signal line S is composed of a plurality of bits. .. The signal S transmitted through the signal line S includes data and a clock. The number of bits of data is not particularly limited, but may be several tens to 100 bits.

The transfer circuit TR1 transfers the signal S42a transmitted from the internal circuit INT4 of the chip CP4 to the internal circuit INT2 of the chip CP2 as the signal S42b. The transfer circuit TR2 transfers the signal S13a transmitted from the internal circuit INT1 of the chip CP1 to the internal circuit INT3 of the chip CP3 as the signal S13b. The transfer circuit TR3 transfers the signal S24a transmitted from the internal circuit INT2 of the chip CP2 to the internal circuit INT4 of the chip CP4 as the signal S24b. The transfer circuit TR4 transfers the signal S31a transmitted from the internal circuit INT3 of the chip CP3 to the internal circuit INT1 of the chip CP1 as the signal S31b.

Then, in the arrangement area of the four chips CP1 to CP4, the two chips CP located on one diagonal line D are inserted through the transfer circuit TR provided on one of the two chips CP not located on one diagonal line D. A data transfer method for transferring data from one to the other is realized.

For example, the signal line (wiring) S13a can be provided between the opposite sides of the chips CP1 and CP2. Other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b can be similarly provided between the sides of the chip CP facing each other. Therefore, the number of signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b that can be wired is greater than that in the case where the corners between the two chips CP located on the diagonal line D are connected by diagonal wiring. Can be increased.

Further, for example, the plurality of signal lines S13a arranged between the sides of the chips CP1 and CP2 facing each other can have the same length. By suppressing the variation in the length of the signal line S13a, it is possible to reduce the skew of the signal transmitted via the signal line S13a, facilitate the timing design, and contribute to the high performance of the semiconductor device SEM1. be able to. The same applies to the other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b.

Further, the signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, S31b can be wired using the same rule as the wiring rule of the signal lines S12, S21 connecting between the chips CP1 and CP2, for example. .. Therefore, the layout design of the signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, S31b can be facilitated.

As shown in FIG. 1, in the present embodiment, the signal transmission path between the two chips CP located on the diagonal line D is clockwise, and the input path and the output path are different from each other. As a result, one transfer circuit TR (one of TR1 to TR4) can be arranged in each chip CP, and four chips CP can be designed using common layout data. As a result, the chip cost can be reduced and the cost of the semiconductor device SEM1 can be reduced. The signal transmission path between the two chips CP located on the diagonal line D may be counterclockwise.

For example, the transfer circuit TR2 outputs the data included in the signal S13a received from the chip CP1 only to the internal circuit INT3 of the chip CP3 and does not output the data to the internal circuit INT2 of the own chip CP2. That is, the internal circuit INT2 does not use the data included in the signal S13a transferred between the chips CP1 and CP3 for data processing and the like, and the transfer circuit TR2 includes the data included in the signals S13a and S13b between the chips CP1 and CP3. Function as a relay circuit of. The internal circuit INT2 may monitor the signal S13a transferred on the transfer circuit TR2.

The transfer circuit TR is preferably arranged on the center side of the arrangement region (in the embodiments shown in FIGS. 1 to 3, the center side of the substrate BRD) in each chip CP. As a result, as compared with the case where the transfer circuit TR is arranged on the outer peripheral side of the arrangement area (the outer peripheral side of the substrate BRD), the signal transmission path between the chips CP1 and CP3 and the signal transmission path between the chips CP2 and CP4. Can be shortened, and the signal transmission time can be shortened.

The substrate BRD may be a silicon interposer. The semiconductor device SEM1 may be formed by packaging the substrate BRD on which the chips CP1 to CP4 are mounted. Further, the chips CP1 to CP4 may be in a state of being sealed with resin or the like and packaged. Further, the semiconductor device SEM1 is connected to a printed circuit board or the like on which other semiconductor components or the like are mounted via bumps provided on the back surface which is the surface opposite to the surface of the board BRD on which the chips CP1 to CP4 are mounted. May be.

When the signal transmission path between the two chips CP located on the diagonal line D is bidirectional, for example, two transfer circuits TR1 and TR3 for transferring signals input/output between the chips CP2 and CP4 are provided. , Provided on only one of the chips CP1 and CP3. Similarly, two transfer circuits TR2 and TR4 that transfer signals input and output between the chips CP1 and CP3 are provided in only one of the chips CP2 and CP4.

For example, when the transfer circuits TR1 and TR3 are provided only on the chip CP1 and the transfer circuits TR2 and TR4 are provided only on the chip CP2, the layout design of the chips CP1 and CP2 and the layout design of the chips CP3 and CP4 must be performed respectively. I won't. Further, on the substrate BRD, a region in which the signal lines S are densely arranged and a region in which the signal lines S are sparsely generated occur, which makes it difficult to design the wiring layout.

Further, the internal circuits INT1 and INT2 of the chips CP1 and CP2 have smaller areas than the internal circuits INT3 and INT4 of the chips CP3 and CP4. Therefore, when the chips CP1 to CP4 have the same chip size, there may be a wasteful area where no circuit is formed in the areas of the internal circuits INT3 and INT4 of the chips CP3 and CP4. Furthermore, in order to eliminate a useless area, when the chip sizes of the chips CP3 and CP4 are made smaller than the chip sizes of the chips CP1 and CP2, it is necessary to design two types of chips.

FIG. 2 is a block diagram showing an example of the transfer circuit TR2 of FIG. 1 and circuits around it. The other transfer circuits TR1, TR3, TR4 and the circuits around them also have the same configuration as that of FIG.

The transfer circuit TR2 includes an input buffer 21, an input flip-flop (FF) 22, an error detection/correction circuit 23, a clock transfer circuit 24, staging FFs 25, FF26, an error detection/correction signal generation circuit 27, an output FF 28 and an output buffer 29. Have. The number of staging FFs inserted in the transfer circuit TR2 may be determined depending on the length of the signal transmission path and the clock frequency, and is not limited to the number shown in FIG.

The input buffer 21 receives the signal S13a of a plurality of bits from the chip CP1 via the signal line S13a, and outputs the received signal S13a to the input FF22. The input FF 22 captures the signal S13a in synchronization with a clock (not shown), and outputs the captured signal S13a to the error detection/correction circuit 23. The clock used by the input FF 22 is the clock used in the chip CP1 included in the signal S13a output from the chip CP1.

The error detection/correction circuit 23 detects or corrects an error in the data included in the signal S13a using the error detection/correction signal included in the signal S13a having a plurality of bits, and when the error is corrected, the error-corrected data is output. It outputs to the clock transfer circuit 24. Thus, even if an error occurs in the data received from the chip CP1 via the signal line S13a, the correct data with the error corrected can be transferred to the chip CP3.

If the error detection/correction circuit 23 detects an uncorrectable error, the error detection/correction circuit 23 may generate error information indicating the detection of the uncorrectable error. Further, when the error detection/correction circuit 23 corrects the data error, the error detection/correction circuit 23 may generate correction information indicating that the error has been corrected. Further, in this case, the error information or the correction information may be output to the internal circuit INT2 of the chip CP2. The internal circuit INT2 of the chip CP2 may hold the error information or the correction information when the error detection/correction circuit 23 generates the error information or the correction information. Information processing such as calculation of the correction rate may be performed.

Further, the error detection/correction circuit 23 may perform only error detection of data, and in this case, the error detection/correction signal generation circuit 11 of the internal circuit INT1 generates a signal for only error detection such as a parity bit. May be. Further, when the error detection/correction circuit 23 detects a data error, the error detection/correction circuit 23 may generate detection information indicating that an error has been detected, and output the generated detection information to the internal circuit INT2. The internal circuit INT2 may hold the detection information when the error detection/correction circuit 23 generates the detection information, and may perform information processing such as calculation of the error detection rate using the held detection information.

The error information, the correction information or the detection information generated by the error detection/correction circuit 23 and output to the internal circuit INT2, or the information generated based on the error information, the correction information or the detection information is the internal circuit INT2. May be output to the internal circuit INT3 of the chip CP3. In this case, for example, the error information, the correction information or the detection information, or the information generated based on the error information, the correction information or the detection information is the input/output circuit IO23 of the internal circuit INT2 and the signal line S23 shown in FIG. And may be transmitted to the internal circuit INT3 via the input/output circuit IO32 of the internal circuit INT3. This can prevent signals other than data, error detection/correction signals, and clocks from being transmitted to the signal line S13b, and the number of signal lines S13b can be minimized. In other words, the signal line S13b can be used only for the purpose of transferring data from the chip CP1 to the chip CP3.

The clock transfer circuit 24 converts the data included in the signal S13a synchronized with the clock of the chip CP1 into the data synchronized with the clock of the chip CP2, and outputs the data to the staging FF 25. For example, as the clock transfer circuit 24, an input asynchronous FIFO (First-In First-Out) may be used. The error detection/correction circuit 23 and the clock transfer circuit 24 may be connected in reverse order. That is, the data synchronized with the clock of the chip CP2 by the clock transfer circuit 24 may be subjected to error detection by the error detection/correction circuit 23, and the error may be arbitrarily corrected.

The staging FF 25 and FF 26 are an example of a relay circuit that sequentially relays data. When the transfer distance of the signal in the transfer circuit TR2 is short, the transfer circuit TR2 does not need to have the staging FF25 and FF26. In this case, the data output from the clock transfer circuit 24 may be directly output to the error detection/correction signal generation circuit 27.

The error detection/correction signal generation circuit 27 generates an error detection/correction signal for correcting an error in data of a plurality of bits, and outputs the generated error detection/correction signal to the output FF 28 together with the data. For example, the error detection/correction signal is an ECC (Error Correction Code) or the like. The output FF 28 outputs the data, the error detection/correction signal and the clock to the output buffer 29. The output buffer 29 outputs the data, the error detection/correction signal and the clock as the signal S13b to the chip CP3.

The internal circuit INT1 of the chip CP1 that outputs the signal S13a includes the error detection/correction signal generation circuit 11, the output FF 12, and the output buffer 13. The error detection/correction signal generation circuit 11, the output FF 12, and the output buffer 13 have the same functions as the error detection/correction signal generation circuit 27, the output FF 28, and the output buffer 29 of the transfer circuit TR2, respectively.

The internal circuit INT3 of the chip CP3 has an input buffer 31, an input FF 32, an error detection/correction circuit 33, and a clock transfer circuit 34. The input buffer 31, the input FF 32, the error detection/correction circuit 33, and the clock transfer circuit 34 have the same functions as the input buffer 21, the input FF 22, the error detection/correction circuit 23, and the clock transfer circuit 24 of the transfer circuit TR2, respectively. Have.

The input buffer 31 receives the signal S13b of multiple bits transferred from the chip CP1 via the transfer circuit TR2 of the chip CP2, and outputs the received signal S13b to the input FF32. The input FF 32 captures the signal S13b in synchronization with the clock of the chip CP2 included in the signal S13b, and outputs the captured signal S13b to the error detection/correction circuit 33.

The error detection/correction circuit 33 detects or corrects an error in the data included in the signal S13b using the error detection/correction signal included in the signal S13b, and when the error is corrected, the error-corrected data is clocked. It outputs to the transfer circuit 34. The clock transfer circuit 34 converts the data included in the signal S13b synchronized with the clock of the chip CP2 into the data synchronized with the clock of the chip CP3. Then, the internal circuit INT3 uses the signal S13b transferred from the chip CP1 via the transfer circuit TR2 of the chip CP2 to execute data processing and the like. When it is necessary to return the data after the data processing to the chip CP1, the internal circuit INT3 transfers the data to the chip CP1 via the transfer circuit TR4 of the chip CP4 shown in FIG. Further, the error detection/correction circuit 33 may perform only error detection, and in this case, the error detection/correction signal generation circuit 27 of the transfer circuit TR2 may generate a signal that only performs error detection such as a parity bit. Good.

The error detection/correction circuit 33 and the clock transfer circuit 34 may be connected in reverse order. That is, the data synchronized with the clock of the chip CP3 by the clock transfer circuit 34 may be subjected to error detection by the error detection/correction circuit 33, and the error may be arbitrarily corrected. Further, the transfer circuit TR2 may not have the error detection/correction circuit 23 and the error detection/correction signal generation circuit 27, and the transfer circuit TR1 may not have the error detection/correction signal generation circuit 11, The circuit TR3 may not have the error detection/detection/correction circuit 33.

FIG. 3 is an explanatory diagram schematically showing an example in which the bumps BP provided in the chips CP1 to CP4 of FIG. 1 are mutually connected by the signal line S (wiring). The signal line S is formed using, for example, a wiring layer of the substrate BRD such as a silicon interposer. The signal line S connected to the bump BP shown in FIG. 3 is wired based on the same wiring rule, for example, without being distinguished by the transfer destination of the signal. As a result, as described with reference to FIG. 1, it is possible to reduce variations in the lengths of the plurality of signal lines S and reduce skew of the signals S. Note that, in FIG. 3, the bumps BP are shown on each chip CP, and only the bumps BP facing each other are connected by the signal line S for easy understanding of the description. However, in reality, the bump BP is located between each chip CP and the substrate BRD. Further, in order to make the lengths of the signal lines S uniform, for example, the bumps BP arranged on the right side of the chip CP2 are connected to the bumps BP located on the inner side of the bumps BP arranged on the left side of the chip CP3 via the signal line S. To be done.

As a comparative example, FIG. 4 does not provide the transfer circuit TR shown in FIG. 1 in each chip CP, but uses two chips CP1, CP3 (or CP2, CP4) located on the diagonal line D1 (or D2) as signal lines. It is a block diagram which shows the example connected by S13, S31 (or S24, S42).

In this case, the bumps (not shown) provided in the corner regions of the chips CP1 to CP4 near the intersections of the diagonal lines D1 and D2 are used to connect both the input and output signal lines with diagonal wiring. Become. Furthermore, the signal lines S13 and S31 and the signal lines S24 and S42 must intersect. Therefore, if the number of signal lines S13, S31, S24, S42 is large, wiring may be difficult. Further, when the number of wiring layers of the substrate BRD such as a silicon interposer is increased to enable wiring, the cost may increase and the signal delay amount may increase. Further, if the lengths of the signal lines S13 and S31 (or S24 and S42) vary, skew may occur in the signal. On the other hand, in the embodiment shown in FIGS. 1 to 3, the above problems can be reduced.

As described above, in the embodiment shown in FIGS. 1 to 3, the data is transferred between the two chips CP located on the diagonal line D via the transfer circuit TR provided on the two chips CP not located on the diagonal line D. You can Since the signal lines S connected to the transfer circuit TR are provided on opposite sides of the two chips CP located on the diagonal line D, they can be wired as compared with the case of connecting by diagonal wiring substantially parallel to the diagonal line D. The number of signal lines S can be increased. Further, the two chips CP adjacent to each other via the sides facing each other can input/output data to/from each other via the input/output circuit IO. As a result, the four chips CP1 to CP4 can communicate data of the same amount of information with each other, and the chips CP1 to CP4 can favorably communicate with each other.

Since four chips CP1 to CP4 can mutually communicate data having the same amount of information, it is possible to divide the function realized by one chip into four chips CP1 to CP4 to form the semiconductor device SEM1. become. In this case, it can be expected that the yield, which is the yield rate of the chips CP, is improved as compared with the case where the function is realized by one chip. By improving the yield, the chip cost can be reduced and the cost of the semiconductor device SEM1 can be reduced.

Since it is possible to reduce variations in the lengths of the plurality of signal lines S that transmit data between the two chips CP located on the diagonal line D, it is possible to reduce skew of data transmitted via the signal lines S. As a result, the timing design can be facilitated and the performance of the semiconductor device SEM1 can be improved.

By arranging the transfer circuit TR on the central part side of the substrate BRD in the chip CP (the central part side of the arrangement region of the chip CP), the transfer circuit TR is arranged on the outer peripheral side of the substrate BRD (the outer peripheral side of the arrangement region of the chip CP). As compared with the case where they are arranged, the signal transmission path between the chips CP can be shortened, and the signal transmission time can be shortened. By disposing one transfer circuit TR on each chip CP, four chips CP can be designed using common layout data. As a result, the chip cost can be reduced and the cost of the semiconductor device SEM1 can be reduced.

Even when an error occurs in the data received from one chip CP via the signal line S, each transfer circuit TR detects the error by the error detection/correction circuit 23, or corrects the correct data to the other side. Can be transferred to the chip CP. Further, each transfer circuit TR uses the error detection/correction signal generation circuit 27 to generate an error detection/correction signal for detecting or correcting an error in the data transferred to the other chip CP. As a result, even if an error occurs in the data output from the transfer circuit TR, the error can be detected or corrected by the error detection/correction circuit 33 of the other chip CP that has received the data. Therefore, even when data transmission between the two chips CP located on the diagonal line D is performed via another chip CP, it is possible to reduce deterioration of data reliability.

FIG. 5 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. The same elements as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM2 illustrated in FIG. 5 is provided with the exception that the transfer circuits TR (TR1 to TR4) are provided on the outer peripheral side (outer peripheral side of the substrate BRD) of the arrangement region of the chips CP (CP1 to CP4). It has the same configuration as the semiconductor device SEM1 shown in FIG.

In this embodiment, since the distance over which the signal S is transmitted within each transfer circuit TR is long, each transfer circuit TR has a larger number of staging FFs (not shown) than in FIG. The configuration of each transfer circuit TR is the same as the configuration of the transfer circuit TR2 shown in FIG. 2 except that the number of staging FFs is large. The position of the transfer circuit TR provided in each chip CP is not limited to the position shown in FIG. 5, and may include, for example, the central portion of each chip CP. In addition, the transfer circuits TR may be distributed and provided in a plurality of regions of each chip CP. The semiconductor device SEM2 shown in FIG. 5 can obtain the same effect as the semiconductor device SEM1 shown in FIG.

FIG. 6 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. The same elements as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM3 shown in FIG. 6 has four chips CP (CP1 to CP4) mounted on the substrate BRD and having a rectangular shape (a kind of rectangular shape) having long sides and short sides. Each chip CP has a transfer circuit TR (TR1-TR4) similar to that shown in FIGS. 1 and 2, and relays signal transmission between the two chips CP located on the diagonal line D1 (or D2).

In addition, the central portion of the substrate BRD (the central portion of the arrangement area of the chips CP is so arranged that the peripheral shape of the arrangement areas of the chips CP1 to CP4 does not have a protruding portion, that is, the outer peripheral shape of the arrangement area is substantially rectangular. ), an empty area in which the chips CP1 to CP4 are not arranged is provided. In other words, each side of the rectangular arrangement area in which the chips CP1 to CP4 are arranged is formed by one long side and one short side of each chip CP. Further, the other one of the long sides of each chip CP faces the other one of the short sides of the adjacent chips CP, and the other one of the short sides of each chip CP is adjacent to the other short sides. It faces the other one of the long sides of the chip CP. The other one of the long sides of the two chips CP located on the diagonal line D1 (or D2) is opposed to each other via a vacant area. Further, the empty area is surrounded by four chips CP1 to CP4.

The other configuration of the semiconductor device SEM3 is similar to that of the semiconductor device SEM1 shown in FIG. The position of the transfer circuit TR provided in each chip CP is not limited to the position shown in FIG. In addition, the transfer circuits TR may be distributed and provided in a plurality of regions of each chip CP.

FIG. 7 is a perspective view showing an example of a system board SBRD on which the semiconductor device SEM3 of FIG. 6 is mounted. In FIG. 7, the semiconductor device SEM3 is mounted on the system board SBRD together with other electronic component ICs and the connector CN. For example, the system board SBRD is a printed circuit board. The system board SBRD may be connected to a back panel provided in a rack or the like (not shown) via the connector CN. A cluster may be formed by connecting a plurality of system boards SBRD to a rack or the like.

Note that the semiconductor device SEM1 in FIG. 1, the semiconductor device SEM2 in FIG. 5, and the semiconductor device SEM4 in FIG. 8 described later may be mounted on the system board SBRD as in FIG.

Also in the semiconductor device SEM3 of this embodiment, the same effect as that of the semiconductor device SEM1 shown in FIG. 1 can be obtained.

FIG. 8 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. The same elements as those in FIGS. 1 and 6 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM4 shown in FIG. 8 has four rectangular chips CP (CP1-CP4) mounted on the substrate BRD. Each chip CP has a transfer circuit TR (TR1-TR4) similar to that shown in FIGS. 1 and 2, and each transfer circuit TR has a signal between two chips CP located on the diagonal line D1 (or D2). Relay the transmission of.

In this embodiment, in order to minimize the size of the transfer circuit TR and the delay amount of the signal S transferred via the transfer circuit TR, the transfer circuit TR is similar to that of FIG. It is provided on the central portion side of the substrate BRD, which is the arrangement region of -CP4. Therefore, each of the chips CP1 to CP4 is mounted on the substrate BRD with one of the corners being close to the intersection of the diagonal lines D1 and D2. As a result, the outer sides of the chips CP1 to CP4 are not aligned on a straight line, the periphery of the arrangement region of the chips CP1 to CP4 has a protrusion, and the size of the substrate BRD is determined according to the protrusion. You can Further, by reducing the empty area in the arrangement area, the area of the chips CP1 to CP4 in the substrate BRD can be reduced. Therefore, it is possible to increase the area of the board BRD on which other electronic components can be mounted. The other configuration of the semiconductor device SEM4 is similar to that of the semiconductor device SEM1 shown in FIGS. 1 and 6. Also in the semiconductor device SEM4 of this embodiment, the same effect as that of the semiconductor device SEM1 shown in FIG. 1 can be obtained.

In the embodiments shown in FIGS. 1, 5, 6 and 8, the example in which the transfer circuit TR is provided in each chip CP has been described. However, when the data transfer between the chips CP2 and CP4 is necessary but the data transfer between the chips CP1 and CP3 is unnecessary, the transfer circuit TR is provided in the chips CP1 and CP3, and the chips CP2 and CP4 are provided. Need not be provided. Further, when the data transfer between the chips CP1 and CP3 is necessary but the data transfer between the chips CP2 and CP4 is not necessary, the transfer circuit TR is provided in the chips CP2 and CP4, and the chips CP1 and CP3 are provided. Need not be provided.

The present invention is not limited to the above specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

11 error detection/correction signal generation circuit 12 output flip-flop 13 output buffer 21 input buffer 22 input flip-flop 23 error detection/correction circuit 24 clock transfer circuit 25, 26 staging 27 error detection/correction signal generation circuit 28 output flip-flop 29 Output buffer 31 Input buffer 32 Input flip-flop 33 Error detection/correction circuit 34 Clock transfer circuit BP Bump BRD substrate CP (CP1, CP2, CP3, CP4) Chip D1, D2 Diagonal line INT (INT1, INT2, INT3, INT4) Internal Circuit S Signal line SEM1, SEM2, SEM3, SEM4 Semiconductor device TR (TR1, TR2, TR3, TR4) Transfer circuit IO Input/output circuit

Claims (9)

A semiconductor device comprising: a first chip, a second chip, a third chip, a fourth chip, and a substrate on which each of the first to fourth chips is mounted,
The first chip is disposed adjacent to the second chip and the fourth chip,
The third chip is arranged adjacent to the second chip and the fourth chip at a position different from that of the first chip,
The second chip includes a first transfer circuit that transfers data from the first chip to the third chip,
The fourth chip includes a second transfer circuit that transfers data from the third chip to the first chip.
Semiconductor device. Each of the first to fourth chips is a rectangle having four sides in a plan view, the sides of the adjacent chips face each other, and the first chip and the third chip have respective sides. The semiconductor device according to claim 1, wherein the corners face each other. 3. The semiconductor device according to claim 1, wherein the data transferred by the first and second transfer circuits is not used in a chip including the first and second transfer circuits. The third chip includes a third transfer circuit that transfers data from the second chip to the fourth chip,
The first chip includes a fourth transfer circuit that transfers data from the fourth chip to the second chip,
The semiconductor device according to any one of claims 1 to 3. The transfer circuit is
An error detection/correction circuit for detecting or correcting an error in data received from one of adjacent chips,
A relay circuit for relaying data output from the error detection/correction circuit,
An error detection/correction signal generation circuit that generates an error detection/correction signal that detects or corrects an error in data output from the relay circuit,
The semiconductor device according to claim 1, wherein the data output from the relay circuit and the detection/error correction signal are transferred to the other of adjacent chips. Each of the chips has an error detection/correction signal generation circuit that generates an error detection/correction signal that detects or corrects an error in the data output to the transfer circuit of any of the other chips, and detects the data error /Output to the transfer circuit of any one of the other chips together with a correction signal,
The error detection/correction circuit of the transfer circuit receives data and the error detection/correction signal from the one of the chips and detects or corrects an error in the data using the error detection/correction signal. The semiconductor device described. 6. The chip that receives data and the error detection/correction signal from the transfer circuit has an error detection/correction circuit that detects or corrects an error in the received data using the error detection/correction signal. Alternatively, the semiconductor device according to claim 6. 8. The semiconductor device according to claim 1, wherein the two chips arranged adjacent to each other have an input/output circuit for inputting/outputting data to/from each other. A data transfer method for a semiconductor device, comprising: a first chip, a second chip, a third chip, a fourth chip, and a substrate on which the first to fourth chips are mounted, respectively. ,
Data is transferred from the first chip, which is arranged adjacent to the second chip and the fourth chip, to the third chip via a first transfer circuit provided in the second chip. Then
A second transfer circuit provided in the fourth chip from the third chip arranged in a position different from the first chip adjacent to the second chip and the fourth chip. A data transfer method for a semiconductor device, comprising: transferring data to the first chip via a memory.

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