JP2023178356A - Semiconductor device, system board, cluster, and data transfer method for semiconductor device - Google Patents

Abstract

To provide a semiconductor device that can perform good communication between chips.SOLUTION: A semiconductor device includes a first chip, a second chip, a third chip, and a fourth chip. The first chip is arranged adjacent to the second chip and the fourth chip. The third chip is arranged adjacent to the second chip and the fourth chip at a different position from the first chip. Data of the first chip is transferred to the third chip via the second chip. Data of the third chip is transferred to the first chip via the fourth chip. Data transmitted from the first chip to the second chip is transmitted via a wiring layer provided on a silicon interposer located at a different location from the first chip, the second chip, the third chip, and the fourth chip.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor device, a system board, a cluster, and a data transfer method for a semiconductor device.

2. Description of the Related Art Multi-chip module type semiconductor devices in which a plurality of chips are mounted on a substrate are known. For example, in a multi-chip module in which a plurality of chips are arranged on a substrate such as a silicon interposer, the chips are electrically connected using wiring formed in a wiring layer of the substrate.

JP2011-86820A

Embodiments of the present invention aim to provide a semiconductor device that can perform communication between chips favorably.

In order to achieve the above object, a semiconductor device according to an embodiment of the present invention is a semiconductor device including a first chip, a second chip, a third chip, and a fourth chip, The first chip is arranged adjacent to the second chip and the fourth chip, and the third chip is arranged adjacent to the second chip and the fourth chip. The data of the first chip is transferred to the third chip via the second chip, and the data of the third chip is transferred to the fourth chip. Data transferred to the first chip via a chip and transmitted from the first chip to the second chip is transferred to the first chip, the second chip, the third chip, and The signal is transmitted via a wiring layer provided on a silicon interposer located at a different position from the fourth chip.

1 is a block diagram showing an example of a semiconductor device in an embodiment of the present invention. FIG. 2 is a block diagram showing an example of the transfer circuit of FIG. 1 and its surrounding circuits. FIG. FIG. 2 is an explanatory diagram schematically showing an example in which bumps provided on the chip in FIG. 1 are interconnected by signal lines (wiring). 2 is a block diagram showing, as a comparative example, an example in which the transfer circuit shown in FIG. 1 is not provided in each chip, and two chips located diagonally are connected by a signal line. FIG. FIG. 3 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. FIG. 3 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. FIG. 6 is a perspective view showing an example of a system board on which the semiconductor device of FIG. 5 is mounted. FIG. 3 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention.

Embodiments of the present invention will be described in detail below with reference to the drawings. Below, the symbols indicating signal lines are also used as signal names (data names). In addition, in the following, unless otherwise specified, in plan view (for example, when viewed in the direction in which the board BRD shown in FIG. 1 and the chips CP (CP1-CP4) arranged and mounted on the board BRD overlap). Give an explanation.

FIG. 1 is a block diagram showing an example of a semiconductor device according to an embodiment of the present invention. The semiconductor device SEM1 shown in FIG. 1 includes four semiconductor chips CP (first chip CP1, The chip has a second chip CP2, a third chip CP3, and a fourth chip CP4 (hereinafter sometimes simply referred to as chip CP1, chip CP2, chip CP3, and chip CP4, respectively). That is, the respective chips CP1 to CP4 are provided at different positions on the substrate BRD in plan view.

For example, each of the chips CP1 to CP4 is connected to a terminal of the substrate BRD via bumps provided on the back surface, which is the surface facing the substrate BRD. Note that other components (electronic components, mechanical components) other than the chips CP1 to CP4 may be mounted on the board BRD. Further, for example, each of the chips CP1 to CP4 may have a plurality of arithmetic units each including an arithmetic unit and a memory. The computing unit is a product-sum computing unit, an inner product computing unit, or the like.

Chips CP1 and CP3 are located on a first diagonal line D1 that is one diagonal line of the rectangular substrate BRD that is the arrangement area of chips CP1 to CP4, and chips CP2 and CP4 are located on the other diagonal line of the substrate BRD. It is located on the second diagonal line D2. Below, the first diagonal line D1 and the second diagonal line D2 may be simply referred to as diagonal lines D1 and D2, respectively. Moreover, when explaining the diagonal lines D1 and D2 without distinction, they may be called diagonal line D. Note that in this embodiment, the external shape of the substrate BRD in plan view matches the shape of the arrangement area of the chips CP1 to CP4. That is, the diagonal line of the substrate BRD and the diagonal lines D1 and D2 of the arrangement area of the chips CP1 to CP4 match. Furthermore, in this specification, the term "chip CP located on the diagonal line D of the substrate BRD" means that the chip CP arranged on the diagonal line D of the substrate BRD overlaps in plan view, and the corner of the chip CP It is not limited to being on the diagonal line D of BRD.

Chip CP1 has an internal circuit INT1 and a transfer circuit TR1, and chip CP2 has an internal circuit INT2 and a transfer circuit TR2. Chip CP3 has an internal circuit INT3 and a transfer circuit TR3, and chip CP4 has an internal circuit INT4 and a transfer circuit TR4. Hereinafter, each of the internal circuits INT1-INT4 may be referred to as an internal circuit INT, and each of the transfer circuits TR1-TR4 may be referred to as a transfer circuit TR.

The internal circuit INT1 of the first chip CP1 and the internal circuit INT2 of the second chip CP2, which are adjacent to each other with their sides facing each other, are connected via signal lines S12 and S21 provided on the substrate BRD. Ru. The first chip CP1 has an input/output circuit IO12 that inputs and outputs signals such as data to signal lines S12 and S21, and the second chip CP2 inputs and outputs signals such as data to and from signal lines S12 and S21. It has an input/output circuit IO21.

The internal circuit INT2 of the second chip CP2 and the internal circuit INT3 of the third chip CP3, which are adjacent to each other with their sides facing each other, are connected via signal lines S23 and S32 provided on the substrate BRD. Ru. The second chip CP2 has an input/output circuit IO23 that inputs and outputs signals such as data to signal lines S23 and S32, and the third chip CP3 inputs and outputs signals such as data to and from signal lines S23 and S32. It has an input/output circuit IO32.

The internal circuit INT3 of the third chip CP3 and the internal circuit INT4 of the fourth chip CP4, which are adjacent to each other with their sides facing each other, are connected via signal lines S34 and S43 provided on the substrate BRD. Ru. The third chip CP3 has an input/output circuit IO34 that inputs and outputs signals such as data to signal lines S34 and S43, and the fourth chip CP4 inputs and outputs signals such as data to and from signal lines S34 and S43. It has an input/output circuit IO43.

The internal circuit INT4 of the fourth chip CP4 and the internal circuit INT1 of the first chip CP1, which are adjacent to each other with their respective sides facing each other, are connected via signal lines S41 and S14 provided on the substrate BRD. Ru. The fourth chip CP4 has an input/output circuit IO41 that inputs and outputs signals such as data to signal lines S41 and S14, and the first chip CP1 inputs and outputs signals such as data to and from signal lines S41 and S14. It has an input/output circuit IO14. Each signal line S12, S21, S23, S32, S34, S43, S41, and S14 is connected, for example, to a bump BP (FIG. 3) provided on each chip CP. Below, when various signal lines are explained without distinction, they may be referred to as signal lines S.

On the other hand, a signal line S13a provided on the substrate BRD is connected between the first chip CP1 and the third chip CP3, which are arranged so that their corner portions face each other and are located on the first diagonal line D1 of the substrate BRD. It is connected via the first transfer circuit TR2 of the second chip CP2 and a signal line S13b provided on the substrate BRD. Further, between the third chip CP3 and the first chip CP1, a signal line S31a provided on the substrate BRD, a second transfer circuit TR4 of the fourth chip CP4, and a signal line S31b provided on the substrate BRD are connected. Connected via.

A signal line S24a provided on the substrate BRD and a third is connected via the third transfer circuit TR3 of the chip CP3 and the signal line S24b provided on the substrate BRD. Further, between the fourth chip CP4 and the second chip CP2, a signal line S42a provided on the substrate BRD, a fourth transfer circuit TR1 of the first chip CP1, and a signal line S42b provided on the substrate BRD are connected. Connected via. Below, the first transfer circuit TR2, the second transfer circuit TR4, the third transfer circuit TR3, and the fourth transfer circuit TR1 may be simply referred to as transfer circuits TR2, TR4, TR3, and TR1, respectively.

With the above configuration, the semiconductor device SEM1 can mutually communicate signals such as data between the four chips CP1 to CP4. Therefore, for example, when performing calculations using multiple calculation units installed on each chip CP1 to CP4, the data and calculation results used by the calculation units cannot be input/output to all other chips CP. can. Therefore, the semiconductor device SEM1 is suitable for, for example, machine learning that performs data processing using a large amount of data and a large number of parameters, particularly deep learning using a neural network.

The arrow attached to each signal line S indicates the transfer direction of the signal transmitted to the signal line S, and the symbol "/" attached to each signal line S indicates that the signal line S is composed of multiple bits. . The signal S transmitted through the signal line S includes data, a clock, and the like. The number of bits of data is not particularly limited, but may range from several tens of bits to about 100 bits.

The transfer circuit TR1 transfers the signal S42a transmitted from the internal circuit INT4 of the chip CP4 to the internal circuit INT2 of the chip CP2 as a signal S42b. The transfer circuit TR2 transfers the signal S13a transmitted from the internal circuit INT1 of the chip CP1 to the internal circuit INT3 of the chip CP3 as a signal S13b. The transfer circuit TR3 transfers the signal S24a transmitted from the internal circuit INT2 of the chip CP2 to the internal circuit INT4 of the chip CP4 as a signal S24b. The transfer circuit TR4 transfers the signal S31a transmitted from the internal circuit INT3 of the chip CP3 to the internal circuit INT1 of the chip CP1 as a signal S31b.

In the arrangement area of the four chips CP1 to CP4, the two chips CP located on one diagonal line D are transferred via the transfer circuit TR provided on one of the two chips CP that are not located on one diagonal line D. A data transfer method for transferring data from one side to the other is realized.

For example, the signal line (wiring) S13a can be provided between opposing sides of the chips CP1 and CP2. The other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b can be similarly provided between the mutually opposing sides of the chip CP. Therefore, the number of signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b that can be wired is greater than when the corners between two chips CP located on the diagonal line D are connected with diagonal wiring. can be increased.

Further, for example, the plurality of signal lines S13a wired between mutually opposing sides of the chips CP1 and CP2 can be made to have the same length. By suppressing variations in the length of the signal line S13a, it is possible to reduce the skew of signals transmitted via the signal line S13a, which facilitates timing design and contributes to higher performance of the semiconductor device SEM1. be able to. The same applies to the other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b.

Further, the signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b can be wired using the same wiring rules as the wiring rules for the signal lines S12 and S21 connecting between the chips CP1 and CP2, for example. . Therefore, the layout design of the signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b can be facilitated.

As shown in FIG. 1, in this embodiment, the signal transmission path between the two chips CP located on the diagonal line D is clockwise, and the input path and the output path are different from each other. As a result, one transfer circuit TR (one of TR1 to TR4) can be placed on each chip CP, and four chips CP can be designed using common layout data. As a result, the chip cost can be reduced, and the cost of the semiconductor device SEM1 can be reduced. Note that the signal transmission path between the two chips CP located on the diagonal line D may be counterclockwise.

For example, the transfer circuit TR2 outputs the data included in the signal S13a received from the chip CP1 only to the internal circuit INT3 of the chip CP3, and does not output it to the internal circuit INT2 of its own chip CP2. That is, the internal circuit INT2 does not use the data included in the signal S13a transferred between the chips CP1 and CP3 for data processing, etc., and the transfer circuit TR2 uses the data included in the signals S13a and S13b between the chips CP1 and CP3. functions as a relay circuit. Note that the internal circuit INT2 may monitor the signal S13a transferred on the transfer circuit TR2.

In each chip CP, the transfer circuit TR is preferably arranged on the center side of the arrangement area (in the embodiment shown in FIGS. 1 to 3, on the center side of the substrate BRD). As a result, the signal transmission path between chips CP1 and CP3 and the signal transmission path between chips CP2 and CP4 are improved compared to the case where the transfer circuit TR is placed on the outer circumferential side of the arrangement area (the outer circumferential side of the board BRD). can be shortened, and the signal transmission time can be shortened.

Note that the substrate BRD may be a silicon interposer. The semiconductor device SEM1 may be formed by packaging the substrate BRD on which the chips CP1 to CP4 are mounted. Furthermore, the chips CP1 to CP4 may be each sealed with a resin or the like and packaged. Further, the semiconductor device SEM1 is connected to a printed circuit board, etc., on which other semiconductor components, etc. are mounted, via bumps provided on the back surface, which is the surface opposite to the front surface of the board BRD on which the chips CP1-CP4 are mounted. It's okay.

Note that if the signal transmission path between two chips CP located on the diagonal line D is bidirectional, for example, two transfer circuits TR1 and TR3 that transfer signals input and output between chips CP2 and CP4 , is provided only on one of the chips CP1 and CP3. Similarly, two transfer circuits TR2 and TR4 that transfer signals input and output between chips CP1 and CP3 are provided only in one of chips CP2 and CP4.

For example, if only chip CP1 is provided with transfer circuits TR1 and TR3, and only chip CP2 is provided with transfer circuits TR2 and TR4, the layout design for chips CP1 and CP2 and the layout design for chips CP3 and CP4 must be performed respectively. It won't happen. Furthermore, since there are regions on the substrate BRD where the signal lines S are wired densely and regions where the signal lines S are wired sparsely, it becomes difficult to design the wiring layout.

Furthermore, the area of internal circuits INT1 and INT2 of chips CP1 and CP2 is smaller than that of internal circuits INT3 and INT4 of chips CP3 and CP4. For this reason, when chips CP1 to CP4 are made to have the same chip size, a wasted area where no circuit is formed may be created in the areas of internal circuits INT3 and INT4 of chips CP3 and CP4. Furthermore, if the chip sizes of the chips CP3 and CP4 are to be made smaller than the chip sizes of the chips CP1 and CP2 in order to eliminate wasted areas, it is necessary to design two types of chips.

FIG. 2 is a block diagram showing an example of the transfer circuit TR2 of FIG. 1 and its surrounding circuits. The other transfer circuits TR1, TR3, TR4 and their surrounding circuits also have the same configuration as in FIG. 2.

The transfer circuit TR2 includes an input buffer 21, an input flip-flop (FF) 22, an error detection/correction circuit 23, a clock switching circuit 24, a staging FF 25, FF 26, an error detection/correction signal generation circuit 27, an output FF 28, and an output buffer 29. has. Note that the number of staging FFs inserted into the transfer circuit TR2 may be determined depending on the length of the signal transmission path and the clock frequency, and is not limited to the number shown in FIG. 2.

The input buffer 21 receives a multi-bit signal S13a from the chip CP1 via the signal line S13a, and outputs the received signal S13a to the input FF22. The input FF 22 takes in the signal S13a in synchronization with a clock (not shown), and outputs the taken-in signal S13a to the error detection/correction circuit 23. Note that the clock used by the input FF22 is the clock used by the chip CP1, which is included in the signal S13a output from the chip CP1.

The error detection/correction circuit 23 uses the error detection/correction signal included in the multi-bit signal S13a to detect or correct an error in the data included in the signal S13a, and when the error is corrected, the error-corrected data is processed. It is output to the clock transfer circuit 24. Thereby, even if an error occurs in the data received from the chip CP1 via the signal line S13a, correct data with the error corrected can be transferred to the chip CP3.

Note that when the error detection/correction circuit 23 detects an uncorrectable error, it may generate error information indicating the detection of the uncorrectable error. Furthermore, when the error detection/correction circuit 23 corrects a data error, it may generate correction information indicating that the error has been corrected. Further, in this case, the error information or correction information may be output to the internal circuit INT2 of the chip CP2. Furthermore, when the error detection/correction circuit 23 generates error information or correction information, the internal circuit INT2 of the chip CP2 may hold the error information or correction information, and use the held error information or correction information to detect errors. Information processing such as calculation of a correction rate may also be performed.

Furthermore, the error detection/correction circuit 23 may perform only data error detection, and in this case, the error detection/correction signal generation circuit 11 of the internal circuit INT1 generates a signal that only detects errors such as parity bits. It's okay. Further, when detecting a data error, the error detection/correction circuit 23 may generate detection information indicating that an error has been detected, and output the generated detection information to the internal circuit INT2. When the error detection/correction circuit 23 generates detection information, the internal circuit INT2 may hold the detection information, and may perform information processing such as calculating an error detection rate using the held detection information.

Note that the error information, correction information, or detection information generated by the error detection/correction circuit 23 and output to the internal circuit INT2, or information generated based on the error information, correction information, or detection information, is output to the internal circuit INT2. The signal may be output to the internal circuit INT3 of the chip CP3 via. In this case, for example, the error information, correction information, or detection information, or information generated based on the error information, correction information, or detection information, is transmitted to the input/output circuit IO23 of the internal circuit INT2 shown in FIG. It may also be transmitted to the internal circuit INT3 via the input/output circuit IO32 of the internal circuit INT3. This can prevent signals other than data, error detection/correction signals, and clocks from being transmitted to the signal line S13b, and can minimize the number of signal lines S13b. In other words, the signal line S13b can be used only for transferring data from the chip CP1 to the chip CP3.

The clock transfer circuit 24 converts the data included in the signal S13a synchronized with the clock of the chip CP1 into data synchronized with the clock of the chip CP2, and outputs it to the staging FF25. For example, as the clock transfer circuit 24, an input asynchronous FIFO (First-In First-Out) may be used. Note that the order of connection between the error detection/correction circuit 23 and the clock transfer circuit 24 may be reversed. That is, the error detection/correction circuit 23 may detect errors in the data synchronized with the clock of the chip CP2 by the clock transfer circuit 24, and may optionally correct the errors.

The staging FF 25 and FF 26 are an example of a relay circuit that sequentially relays data. Note that if the signal transfer distance within the transfer circuit TR2 is short, the transfer circuit TR2 does not need to include the staging FF25 and FF26. In this case, the data output from the clock transfer circuit 24 may be directly output to the error detection/correction signal generation circuit 27.

The error detection/correction signal generation circuit 27 generates an error detection/correction signal for correcting errors in data of multiple bits, and outputs the generated error detection/correction signal to the output FF 28 together with the data. For example, the error detection/correction signal is an ECC (Error Correction Code) or the like. Output FF 28 outputs data, an error detection/correction signal, and a clock to output buffer 29. Output buffer 29 outputs the data, error detection/correction signal, and clock to chip CP3 as signal S13b.

Note that the internal circuit INT1 of the chip CP1 that outputs the signal S13a includes an error detection/correction signal generation circuit 11, an output FF12, and an output buffer 13. The error detection/correction signal generation circuit 11, output FF 12, and output buffer 13 have the same functions as the error detection/correction signal generation circuit 27, output FF 28, and output buffer 29 of the transfer circuit TR2, respectively.

The internal circuit INT3 of the chip CP3 includes an input buffer 31, an input FF32, an error detection/correction circuit 33, and a clock transfer circuit 34. The input buffer 31, input FF 32, error detection/correction circuit 33, and clock transfer circuit 34 have the same functions as the input buffer 21, input FF 22, error detection/correction circuit 23, and clock transfer circuit 24 of the transfer circuit TR2, respectively. have

The input buffer 31 receives the multi-bit signal S13b transferred from the chip CP1 via the transfer circuit TR2 of the chip CP2, and outputs the received signal S13b to the input FF32. The input FF 32 captures the signal S13b in synchronization with the clock of the chip CP2 included in the signal S13b, and outputs the captured signal S13b to the error detection/correction circuit 33.

The error detection/correction circuit 33 uses the error detection/correction signal included in the signal S13b to detect or correct an error in the data included in the signal S13b, and when the error is corrected, clocks the error-corrected data. It is output to the transfer circuit 34. The clock transfer circuit 34 converts the data included in the signal S13b synchronized with the clock of the chip CP2 into data synchronized with the clock of the chip CP3. Then, the internal circuit INT3 uses the signal S13b transferred from the chip CP1 via the transfer circuit TR2 of the chip CP2 to perform data processing and the like. When it is necessary to return the data after data processing to the chip CP1, the internal circuit INT3 transfers the data to the chip CP1 via the transfer circuit TR4 of the chip CP4 shown in FIG. Further, the error detection/correction circuit 33 may perform only error detection, and in this case, the error detection/correction signal generation circuit 27 of the transfer circuit TR2 may generate a signal that only detects errors such as parity bits. good.

Note that the order of connection between the error detection/correction circuit 33 and the clock transfer circuit 34 may be reversed. That is, the data synchronized with the clock of the chip CP3 by the clock transfer circuit 34 may be subjected to error detection by the error detection/correction circuit 33, and may be arbitrarily corrected. Further, the transfer circuit TR2 does not need to have the error detection/correction circuit 23 and the error detection/correction signal generation circuit 27, and the transfer circuit TR1 does not need to have the error detection/correction signal generation circuit 11. The circuit TR3 may not include the error detection/correction circuit 33.

FIG. 3 is an explanatory diagram schematically showing an example in which the bumps BP provided on the chips CP1 to CP4 in FIG. 1 are interconnected by a signal line S (wiring). The signal line S is formed using a wiring layer of the substrate BRD, such as a silicon interposer, for example. The signal lines S connected to the bumps BP shown in FIG. 3 are wired based on the same wiring rule, for example, without being distinguished by the signal transfer destination. Thereby, as explained with reference to FIG. 1, variations in the lengths of the plurality of signal lines S can be reduced, and the skew of the signals S can be reduced. Note that, in FIG. 3, bumps BP are shown on each chip CP to make the explanation easier to understand, and only the bumps BP facing each other are connected by a signal line S. However, in reality, the bumps BP are located between each chip CP and the substrate BRD. In order to make the lengths of the signal lines S uniform, for example, the bumps BP arranged on the right side of the chip CP2 are connected via the signal line S to the bumps BP located further back than the bumps BP arranged on the left side of the chip CP3. be done.

As a comparative example, FIG. 4 shows that the transfer circuit TR shown in FIG. It is a block diagram showing an example of connection in S13 and S31 (or S24 and S42).

In this case, the bumps (not shown) provided in the corner area of chips CP1-CP4 near the intersection of diagonal lines D1 and D2 are used to connect both input and output signal lines with diagonal wiring. Become. Furthermore, the signal lines S13 and S31 must intersect with the signal lines S24 and S42. Therefore, when the number of signal lines S13, S31, S24, and S42 is large, wiring may become difficult. Furthermore, if the number of wiring layers of the substrate BRD such as a silicon interposer is increased in order to enable wiring, the cost may increase and the amount of signal delay may increase. Furthermore, if the lengths of the signal lines S13, S31 (or S24, S42) vary, there is a risk that skew may occur in the signals. In contrast, the embodiments shown in FIGS. 1 to 3 can reduce the above problems.

As described above, in the embodiments shown in FIGS. 1 to 3, data is transferred between two chips CP located on the diagonal line D via the transfer circuit TR provided on the two chips CP that are not located on the diagonal line D. Can be done. Since the signal line S connected to the transfer circuit TR is provided on opposite sides of the two chips CP located on the diagonal line D, wiring is easier than when connecting with diagonal wiring substantially parallel to the diagonal line D. The number of signal lines S can be increased. Furthermore, two chips CP adjacent to each other via opposite sides can input and output data to each other via an input/output circuit IO. As a result, the four chips CP1 to CP4 can mutually communicate the same amount of data, and the chips CP1 to CP4 can mutually communicate favorably.

Since the same amount of data can be mutually communicated between the four chips CP1-CP4, it is possible, for example, to divide a function realized by one chip into four chips CP1-CP4 to form the semiconductor device SEM1. become. In this case, it can be expected that the yield rate, which is the percentage of non-defective chips CP, will be improved compared to the case where the function is realized with one chip. By improving the yield, it is possible to reduce the chip cost, and the cost of the semiconductor device SEM1 can be reduced.

Since variations in the lengths of the plurality of signal lines S that transmit data between two chips CP located on the diagonal line D can be reduced, the skew of data transmitted via the signal lines S can be reduced. As a result, timing design can be facilitated, and it is possible to contribute to higher performance of the semiconductor device SEM1.

By arranging the transfer circuit TR on the center side of the substrate BRD in the chip CP (on the center side of the placement area of the chip CP), the transfer circuit TR can be placed on the outer circumference side of the substrate BRD (on the outer circumference side of the placement area of the chip CP). Compared to the case where chips CP are arranged, the signal transmission path between the chips CP can be shortened, and the signal transmission time can be shortened. By arranging one transfer circuit TR on each chip CP, four chips CP can be designed using common layout data. As a result, the chip cost can be reduced, and the cost of the semiconductor device SEM1 can be reduced.

Even if an error occurs in the data received from one chip CP via the signal line S, each transfer circuit TR detects the error using the error detection/correction circuit 23, or transfers correct data with the error corrected to the other chip. can be transferred to the chip CP. Further, each transfer circuit TR generates an error detection/correction signal for detecting or correcting an error in data to be transferred to the other chip CP by using the error detection/correction signal generation circuit 27. Thereby, even if an error occurs in the data output from the transfer circuit TR, the error can be detected or corrected by the error detection/correction circuit 33 of the other chip CP that received the data. Therefore, even when data transmission between two chips CP located on the diagonal line D is performed via another chip CP, deterioration in data reliability can be reduced.

FIG. 5 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM2 shown in FIG. 5 is different from the one shown in FIG. The structure is similar to that of the semiconductor device SEM1 shown in FIG.

In this embodiment, since the distance over which the signal S is transmitted within each transfer circuit TR is long, each transfer circuit TR has a larger number of staging FFs (not shown) than in FIG. 2. The configuration of each transfer circuit TR is the same as the configuration of transfer circuit TR2 shown in FIG. 2, except that the number of staging FFs is large. Note that the position of the transfer circuit TR provided in each chip CP is not limited to the position shown in FIG. 5, and may include, for example, the center of each chip CP. Further, the transfer circuit TR may be provided in a distributed manner in a plurality of regions of each chip CP. The semiconductor device SEM2 shown in FIG. 5 can obtain the same effects as the semiconductor device SEM1 shown in FIG.

FIG. 6 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM3 shown in FIG. 6 has four chips CP (CP1 to CP4) each having a rectangular shape (a type of rectangular shape) having long sides and short sides and mounted on a substrate BRD. Each chip CP has a transfer circuit TR (TR1-TR4) similar to that in FIGS. 1 and 2, and relays signal transmission between two chips CP located on the diagonal line D1 (or D2).

In addition, the central part of the substrate BRD (the central part of the chip CP arrangement area ) is provided with an empty area where chips CP1-CP4 are not placed. In other words, each side of the rectangular arrangement area in which the chips CP1 to CP4 are arranged is formed by one of the long sides and one of the short sides of each chip CP. The other long side of each chip CP is opposite to the other short side of the adjacent chip CP, and the other short side of each chip CP is opposite to the other short side of the adjacent chip CP. It faces the other one of the long sides of the chip CP. The other longitudinal sides of the two chips CP located on the diagonal line D1 (or D2) face each other with an empty area interposed therebetween. Further, the free area is surrounded by four chips CP1 to CP4.

The other configuration of the semiconductor device SEM3 is similar to the configuration of the semiconductor device SEM1 shown in FIG. Note that the position of the transfer circuit TR provided in each chip CP is not limited to the position shown in FIG. 6. Further, the transfer circuit TR may be provided in a distributed manner in a plurality of regions of each chip CP.

FIG. 7 is a perspective view showing an example of a system board SBRD on which the semiconductor device SEM3 of FIG. 6 is mounted. In FIG. 7, the semiconductor device SEM3 is mounted on the system board SBRD together with other electronic components IC and connector CN. For example, the system board SBRD is a printed circuit board. The system board SBRD may be connected to a back panel provided on a rack (not shown) or the like via a connector CN. Furthermore, a cluster may be configured by connecting a plurality of system boards SBRD to a rack or the like.

Note that the semiconductor device SEM1 in FIG. 1, the semiconductor device SEM2 in FIG. 5, and the semiconductor device SEM4 in FIG. 8, which will be described later, may also be mounted on the system board SBRD as in FIG. 7.

Also in the semiconductor device SEM3 of this embodiment, the same effects as in the semiconductor device SEM1 shown in FIG. 1 can be obtained.

FIG. 8 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. Elements similar to those in FIGS. 1 and 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM4 shown in FIG. 8 has four rectangular chips CP (CP1-CP4) mounted on a substrate BRD. Each chip CP has a transfer circuit TR (TR1-TR4) similar to that in FIGS. 1 and 2, and each transfer circuit TR transfers signals between two chips CP located on a diagonal line D1 (or D2). relay the transmission of

In this embodiment, in order to minimize the size of the transfer circuit TR and to minimize the amount of delay of the signal S transferred via the transfer circuit TR, the transfer circuit TR is connected to the chip CP1 as in FIG. - Provided on the center side of the substrate BRD, which is the arrangement area of CP4. Therefore, each of the chips CP1 to CP4 is mounted on the substrate BRD with one of its corners close to the intersection of the diagonals D1 and D2. As a result, the outer sides of each of the chips CP1 to CP4 are not aligned on a straight line, and the periphery of the arrangement area of the chips CP1 to CP4 has a protrusion, and the size of the substrate BRD can be determined according to the protrusion. Can be done. Furthermore, by reducing the free space within the arrangement area, the area occupied by the chips CP1 to CP4 in the substrate BRD can be reduced. Therefore, the area in which other electronic components can be mounted on the board BRD can be increased. The other configuration of the semiconductor device SEM4 is similar to the configuration of the semiconductor device SEM1 shown in FIGS. 1 and 6. Also in the semiconductor device SEM4 of this embodiment, the same effects as in the semiconductor device SEM1 shown in FIG. 1 can be obtained.

Note that in the embodiments shown in FIGS. 1, 5, 6, and 8, examples have been described in which each chip CP is provided with a transfer circuit TR. However, if it is necessary to transfer data between the chips CP2 and CP4 but not between the chips CP1 and CP3, the transfer circuit TR is provided in the chips CP1 and CP3, and the transfer circuit TR is provided in the chips CP2 and CP3. does not need to be provided. Furthermore, if data transfer between chips CP1 and CP3 is required but data transfer between chips CP2 and CP4 is not required, the transfer circuit TR is provided in chips CP2 and CP4, and the transfer circuit TR is provided in chips CP1 and CP3. does not need to be provided.

The present invention is not limited to the above-described specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

11 Error detection/correction signal generation circuit 12 Output flip-flop 13 Output buffer 21 Input buffer 22 Input flip-flop 23 Error detection/correction circuit 24 Clock transfer circuit 25, 26 Staging 27 Error detection/correction signal generation circuit 28 Output flip-flop 29 Output buffer 31 Input buffer 32 Input flip-flop 33 Error detection/correction circuit 34 Clock transfer circuit BP Bump BRD Board CP (CP1, CP2, CP3, CP4) Chip D1, D2 Diagonal INT (INT1, INT2, INT3, INT4) Internal Circuit S Signal line SEM1, SEM2, SEM3, SEM4 Semiconductor device TR (TR1, TR2, TR3, TR4) Transfer circuit IO Input/output circuit

Claims (14)

A semiconductor device comprising a first chip, a second chip, a third chip, and a fourth chip,
the first chip is arranged adjacent to the second chip and the fourth chip,
The third chip is arranged adjacent to the second chip and the fourth chip at a different position from the first chip,
The data of the first chip is transferred to the third chip via the second chip,
The data of the third chip is transferred to the first chip via the fourth chip,
Data transmitted from the first chip to the second chip is transmitted to a silicon interposer located at a different location than the first chip, the second chip, the third chip, and the fourth chip. transmitted through the provided wiring layer,
Semiconductor equipment. A semiconductor device comprising a first chip, a second chip, a third chip, and a fourth chip,
the first chip is arranged adjacent to the second chip and the fourth chip,
The third chip is arranged adjacent to the second chip and the fourth chip at a different position from the first chip,
The data of the first chip is transferred to the third chip via the second chip,
The data of the third chip is transferred to the first chip via the fourth chip,
The data transmitted from the first chip to the second chip is on a circuit board located at a different location from the first chip, the second chip, the third chip, and the fourth chip. transmitted through a wiring layer provided in
Semiconductor equipment. The first to fourth chips are rectangular with four sides in a plan view, the adjacent chips have at least one side facing each other, and the first chip and the third chip has its corners facing each other,
The semiconductor device according to claim 1 or 2. The data passing through the second chip is not used for calculation by the internal circuit of the second chip, but is transferred from the first chip to the third chip via the second chip. and used for calculation by the internal circuit of the third chip,
The semiconductor device according to any one of claims 1 to 3. The data of the second chip is transferred to the fourth chip via the third chip,
The data of the fourth chip is transferred to the second chip via the first chip.
The semiconductor device according to any one of claims 1 to 4. The second chip and the fourth chip are
having an error detection/correction circuit for detecting or correcting errors in data received from one of the adjacent chips;
The semiconductor device according to any one of claims 1 to 5. In a plan view, an extension of a diagonal line that overlaps with two corners of the first chip overlaps with the third chip;
The semiconductor device according to any one of claims 1 to 6. the first chip and the third chip have the same layout design;
The semiconductor device according to any one of claims 1 to 7. the second chip and the fourth chip have the same layout design;
The semiconductor device according to claim 8. A system board including the semiconductor device according to claim 1 . a fifth chip different from the first chip, the second chip, the third chip and the fourth chip;
The system board according to claim 10. A cluster comprising a plurality of system boards according to claim 10 or claim 11. A data transfer method for a semiconductor device including a first chip, a second chip, a third chip, and a fourth chip,
the first chip is arranged adjacent to the second chip and the fourth chip,
The third chip is arranged adjacent to the second chip and the fourth chip at a different position from the first chip,
The data of the first chip is transferred to the third chip via the second chip,
The data of the third chip is transferred to the first chip via the fourth chip,
Data transmitted from the first chip to the second chip is transmitted to a silicon interposer located at a different location than the first chip, the second chip, the third chip, and the fourth chip. transmitted through the provided wiring layer,
Data transfer method for semiconductor devices. A data transfer method for a semiconductor device including a first chip, a second chip, a third chip, and a fourth chip,
the first chip is arranged adjacent to the second chip and the fourth chip,
The third chip is arranged adjacent to the second chip and the fourth chip at a different position from the first chip,
The data of the first chip is transferred to the third chip via the second chip,
The data of the third chip is transferred to the first chip via the fourth chip,
The data transmitted from the first chip to the second chip is on a circuit board located at a different location from the first chip, the second chip, the third chip, and the fourth chip. transmitted through a wiring layer provided in
Data transfer method for semiconductor devices.

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