JP2020096021A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of increasing the number of wires connecting chips.SOLUTION: A semiconductor device includes first to third chips arranged on a substrate, and in a plan view, the first chip is adjacent to the second chip, the third chip is adjacent to the second chip, the substrate is arranged so as to face the first chip through an empty area surrounded by the sides of the first to third chips and exposed from the first to third chips, and a first signal line that connects the first chip and the third chip is wired in the empty area.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to semiconductor devices.

A multi-chip module type semiconductor device in which a plurality of chips are mounted on a substrate is known. For example, in a multi-chip module in which a plurality of chips are arranged on a circuit board, the chips are connected using wires formed in a wiring layer of the board.

JP, 9-64269, A

When connecting a plurality of chips to each other, for example, it is possible to connect by wiring provided between opposite sides, but wiring is not arranged between chips located on a diagonal line of a chip placement region. It can be difficult.

Therefore, the semiconductor device of the embodiment of the present invention has first to third chips arranged on a substrate, and the first chip is adjacent to the second chip in plan view, and The third chip is adjacent to the second chip, and the third chip is surrounded by the sides of the first to third chips of the substrate, and the third chip is exposed through the empty region exposed from the first to third chips. A first signal line, which is arranged so as to face one chip and connects the first chip and the third chip, is laid in the empty area.

It is a block diagram showing an example of a semiconductor device in one embodiment of the present invention. 2 is a block diagram showing an example of a circuit provided in the chip of FIG. 1. FIG. As a comparative example, in another semiconductor device in which the corners of four chips are arranged close to each other, it is an explanatory diagram showing an example in which two chips located on the diagonal of the substrate are connected by signal lines. It is a block diagram which shows the example of the semiconductor device in another embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the code indicating the signal line is also used as a signal name (data name). Further, in the following, unless otherwise specified, in plan view (for example, when viewed in a direction in which the board BRD shown in FIG. 1 and the four chips CP (CP1-CP4) arranged and mounted on the board BRD overlap) Will be explained.

FIG. 1 is a block diagram showing an example of a semiconductor device according to an embodiment of the present invention. The semiconductor device SEM1 illustrated in FIG. 1 includes four semiconductor chips CP (CP1 to CP4) which are the first to fourth chips and are arranged on the rectangular substrate BRD in plan view. Each chip CP has a rectangular shape and has two long sides and two short sides. Further, a plurality of bumps BP are formed on the back surface of each chip CP facing the substrate BRD. Note that in FIG. 1, the bumps BP are illustrated without distinguishing the back surface and the front surface of each chip CP for the sake of easy understanding.

In other words, the semiconductor device SEM1 shown in FIG. 1 has the first to fourth chips arranged on the substrate, and the first chip is adjacent to the second chip when seen in a plan view. There is. The third chip is adjacent to the second chip, is adjacent to the two chips, respectively, and is surrounded by the sides of the first to third chips of the substrate, and the first to third chips are surrounded. It is arranged so as to face the first chip through an empty area exposed from. Then, a first signal line connecting the first chip and the third chip facing each other through the empty area is wired in the empty area.

Furthermore, the fourth chip is adjacent to the first chip and the third chip, and the empty area is exposed by being surrounded by the first to fourth chips. In the present specification, the term "surrounding" means that the outer circumference of a certain range is surrounded, and is not limited to being completely surrounded. That is, in FIG. 1, a substantially rectangular range SP surrounded by the four chips CP1 to CP4 of the substrate BRD is a free area, but there is no edge of the chip CP in a part of the outer peripheral portion of the free area SP. Even within the scope of the present invention.

The four chips CP1 to CP4 are arranged on the rectangular substrate BRD by changing the longitudinal direction DIR by 90 degrees, and the four chips CP1 to CP4 are arranged on the four sides of the substrate BRD. The side and the short side are on the same line. In other words, in each chip CP, one of the long sides faces one of the short sides of the adjacent chips CP, and the other of the long sides faces the outer periphery of the substrate BRD. In addition, in each chip CP, one of the short sides faces one of the long sides of another adjacent chip CP, and the other of the short sides faces the outer periphery of the substrate BRD.

In other words, one of the long sides of the first chip CP1 faces one of the short sides of the second chip CP2, and one of the long sides of the second chip CP2 is the third side. Of one of the short sides of the third chip CP3, one of the long sides of the third chip CP3 faces one of the short sides of the fourth chip CP4, and One of the long sides faces one of the short sides of the first chip CP1.

In this embodiment, the sides of the first chip CP1 and the sides of the third chip CP3, and the sides of the second chip CP2 and the sides of the fourth chip CP4, which face each other through the empty area SP, are parallel to each other. It is arranged.

That is, the empty area SP in which the chips CP1 to CP4 are not arranged is provided in the central portion of the substrate BRD which is the arrangement area of the chips CP1 to CP4. As described above, by arranging the sides of the two chips CP facing the respective sides of the substrate BRD so as to be aligned and disposing the chips CP on the substrate BRD, the size of the arrangement region of the chips CP, that is, the substrate BRD in the present embodiment. The size of can be reduced. As a result, the cost of the semiconductor device SEM1 can be reduced. Further, by reducing the size of the substrate BRD, it is possible to reduce the size of the printed circuit board or the like on which the semiconductor device SEM1 is mounted, and it is possible to reduce the cost of the system including the semiconductor device SEM1.

The two chips CP whose long sides and short sides are adjacent to each other are connected to each other by connecting the bumps BP formed on each chip CP to the signal lines S (wiring) formed on the substrate BRD. To be done. At this time, the signal lines S are arranged in a direction orthogonal to the long side and the short side to provide the number of signal lines S corresponding to the length of the facing portion of the long side and the short side. You can

Further, the two chips CP facing each other through the empty area SP have the signal lines S (wiring; first signal line, second signal line) formed with the bumps BP formed on each chip CP in the empty area SP. ) Is connected to each other. At this time, the signal line S is orthogonal to the side adjacent to the empty area SP of the chip CP (that is, facing the other chip CP via the empty area SP) (that is, the empty area SP is By wiring in a direction toward a partial side of the chip CP that faces through the signal line S, the signal line S can be arranged on a side (hereinafter, a partial side) adjacent to the empty area of the chip CP.

That is, in this embodiment, the connection between the chips CP facing each other through the empty area SP can be performed by the same method as the connection between the chips CP in which the long side and the short side are adjacent to each other. This is because the provision of the vacant region SP allows the formation of partial sides having a certain length in the portions facing each other on the chip CP, and between the partial sides, the signal lines S are arranged in the orthogonal direction. This is because they can be placed.

Therefore, it is possible to increase the number of signal lines S connecting the chips CP facing each other through the empty area SP, as compared with the case where the empty area SP is not provided. As a result, the four chips CP can communicate data of the same amount of information with each other. For example, when an arithmetic operation is executed using a plurality of arithmetic units mounted on each of the chips CP1 to CP4, data and arithmetic results used by the arithmetic units can be input to and output from all the other chips CP. Therefore, the semiconductor device SEM1 is suitable for, for example, machine learning for performing data processing using a large number of data and a large number of parameters, particularly deep learning using a neural network.

Further, when data having the same amount of information can be mutually communicated between the four chips CP, for example, it is possible to divide the function realized by one chip into four chips CP to form the semiconductor device SEM1. .. In this case, the yield, which is the yield rate of the chips CP, can be improved as compared with the case where the function is realized by one chip. As a result, the chip cost can be reduced and the cost of the semiconductor device SEM1 can be reduced.

Further, in the two chips CP facing each other through the empty area SP, the bumps BP formed near the partial sides can be connected to the signal line S, so that the variation in the length of the signal line S can be reduced and the signal line S can be reduced. It is possible to reduce skew of data transmitted via the. As a result, the timing design can be facilitated and the performance of the semiconductor device SEM1 can be improved.

Note that, for example, the signal line S is formed using the wiring layer of the substrate BRD, and the signal line S formed in the wiring layer is, for example, an electrode on the substrate BRD via the conductive material provided in the through hole. Connected to. Then, the bumps BP are soldered to the electrodes on the substrate BRD, so that the chips CP are connected via the signal lines S. In the present embodiment, the conductive material provided in the through hole and the electrode on the substrate BRD are also part of the signal line S.

FIG. 2 is a block diagram showing an example of a circuit provided in the chip CP of FIG. Each chip CP has an error detection/correction signal generation circuit 11, an output flip-flop (FF) 12, and an output buffer 13 corresponding to the output destination chip CP of the signal S (S12, S21, S13, S31). ing. In addition, each chip CP has an input buffer 21, an input flip-flop (FF) 22, an error detection/correction circuit 23, and a clock transfer circuit 24, corresponding to the chip CP that outputs the signal S.

The symbol "/" attached to each signal line S12, S21, S13, S31 indicates that the signal lines S12, S21, S13, S31 are composed of a plurality of bits. The signals transmitted through the signal lines S12, S21, S13, S31 include data and clocks. The number of bits of data is not particularly limited, but may be several tens to 100 bits.

FIG. 2 shows a circuit block that inputs and outputs signals S12 and S21 between chips CP1 and CP2, and a circuit block that inputs and outputs signals S13 and S31 between chips CP1 and CP3. Although not shown in FIG. 2, the circuit block that inputs/outputs the signal S between the chips CP2 and CP3, between the chips CP3 and CP4, and between the chips CP4 and CP1 inputs/outputs the signals S12 and S21 between the chips CP1 and CP2. 2 is similar to the circuit block of FIG. The circuit block that inputs and outputs the signal S between the chips CP2 and CP4 is the same as the circuit block in FIG. 2 that inputs and outputs the signals S13 and S31 between the chips CP1 and CP3.

Hereinafter, a circuit block for inputting/outputting the signals S12 and S21 between the chips CP1 and CP2 will be described. In the chip CP1, the error detection/correction signal generation circuit 11 generates an error detection/correction signal for correcting a data error, and outputs the generated error detection/correction signal to the output FF 12 together with the data. For example, the error detection/correction signal is an ECC (Error Correction Code) or the like. The output FF 12 outputs the data, the error detection/correction signal and the clock to the output buffer 13. The output buffer 13 outputs the data, the error detection/correction signal, and the clock to the chip CP2 as a multi-bit signal S12.

The input buffer 21 of the chip CP2 receives the signal of a plurality of bits from the chip CP1 via the signal line S12 and outputs the received signal to the input FF22. The input FF 22 captures the signal S12 in synchronization with the clock of the chip CP1 included in the signal S12, and outputs the captured signal S12 to the error detection/correction circuit 23.

The error detection/correction circuit 23 detects or corrects the error of the data included in the signal S12 using the error detection/correction signal included in the signal, and when the error is corrected, the error-corrected data is clocked. It outputs to the replacement circuit 24. Thus, even if an error occurs in the data received from the chip CP1 via the signal line S12, the correct data with the error corrected can be processed in the chip CP2.

The error detection/correction circuit 23 may perform only error detection. In this case, the error detection/correction signal generation circuit 11 of the chip CP1 that outputs the signal S12 to the signal line S12 only detects errors such as parity bits. May be generated.

When detecting an uncorrectable error, the error detection/correction circuit 23 may generate error information indicating the detection of the uncorrectable error. In addition, when the error detection/correction circuit 23 corrects an error in the data, the error detection/correction circuit 23 may generate correction information indicating that the error has been corrected. Further, when the error detection/correction circuit 23 detects an error in the data, the error detection/correction circuit 23 may generate detection information indicating that the error has been detected.

For example, the internal circuit of the chip CP2 may hold the error information, the correction information or the detection information when the error detection/correction circuit 23 generates the error information, the correction information or the detection information. Information processing such as calculation of an error correction rate may be performed using the detection information. Further, the internal circuit of the chip CP2 may output the generated error information, correction information, detection information, calculated error correction rate, or the like to the chip CP1.

The clock transfer circuit 24 converts the data included in the signal S12 synchronized with the clock of the chip CP1 into the data synchronized with the clock of the chip CP2. Then, the internal circuit of the chip CP2 uses the data transferred from the chip CP1 to execute data processing and the like. When it is necessary to return the data after the data processing to the chip CP1, the chip CP2 uses the error detection/correction signal generation circuit 11 to generate an error detection/correction signal for correcting the error of the data returned to the chip CP1. Then, the chip CP2 outputs the generated error detection/correction signal, data, and clock to the chip CP1 via the output FF 12 and the output buffer 13. The input buffer 21, the input FF 22, the error detection/correction circuit 23, and the clock transfer circuit 24 of the chip CP1 operate similarly to the input buffer 21, the input FF 22, the error detection/correction circuit 23, and the clock transfer circuit 24 of the chip CP2. To do.

The error detection/correction circuit 23 and the clock transfer circuit 24 may be connected in reverse order. That is, the data synchronized with the clock of the chip CP2 by the clock transfer circuit 24 may be subjected to error detection by the error detection/correction circuit 23, and the error may be arbitrarily corrected. Further, each of the chips CP1 to CP4 may not have the error detection/correction signal generation circuit 11 and the error detection/correction circuit 23.

The circuit block used for transmitting a signal from the chip CP1 to the chip CP3 is the same as the description of the circuit block used for transmitting a signal from the chip CP1 to the chip CP2 described above, except that the signal line S13 is used. .. The circuit block used for transmitting a signal from the chip CP3 to the chip CP1 is the same as the description of the circuit block used for transmitting a signal from the chip CP2 to the chip CP1 described above, except that the signal line S31 is used. ..

FIG. 3 shows, as a comparative example, in another semiconductor device in which corners of four chips CP (CP1-CP4) are arranged close to each other, two chips CP located on a diagonal line D1 (or D2) of a substrate BRD. 3 is an explanatory diagram showing an example in which signal lines S are connected to each other. FIG. It should be noted that, in FIG. 3, the illustration in the vicinity of the intersection of the diagonal lines D1 and D2 is omitted for the sake of clarity.

In FIG. 3, the signal line S is diagonally wired along the diagonal line D1 (or D2) using the bumps BP provided in the corner regions of the chips CP1-CP4 near the intersections of the diagonal lines D1 and D2. .. Further, the signal line S connecting between the chips CP1 and CP3 and the signal line S connecting between the chips CP2 and CP4 intersect. Therefore, when the number of bits of data transmitted between the chips CP1 and CP3 or between the chips CP2 and CP4 is large, it may be difficult to wire all the signal lines S. Further, when the number of wiring layers of the substrate BRD such as a silicon interposer is increased to enable wiring, the cost may increase and the signal delay amount may increase.

Further, as shown in FIG. 3, the signal line S has a length that varies depending on the position of the bump BP to be connected, so that the signal S may be skewed. On the other hand, in the semiconductor device SEM1 of FIG. 1, since the signal line S is wired in the direction orthogonal to the sides of the chips CP facing each other via the empty area SP, the above problems can be reduced.

As described above, in the embodiment shown in FIGS. 1 and 2, the wiring provided between the chips CP facing each other can be easily arranged, and the number of signal lines S connecting the chips can be increased. Therefore, for example, it is possible to mutually communicate data having the same amount of information between the four chips CP, and the function realized by one chip CP is divided into four chips CP to be integrated in the semiconductor device SEM1. It becomes possible to do. In this case, the yield, which is the yield rate of the chips CP, can be improved as compared with the case where the function is realized by one chip. Therefore, the chip cost can be reduced, and the cost of the semiconductor device SEM1 can be reduced.

Further, since the signal line S can be connected to the bump BP provided near the partial side exposed in the empty area SP, the variation in the length of the signal line S can be reduced, and the signal line S is transmitted. Data skew can be reduced. As a result, the timing design can be facilitated and the performance of the semiconductor device SEM1 can be improved.

Further, by arranging the rectangular chips CP1 to CP4 on the substrate BRD by changing the longitudinal direction DIR by 90 degrees, the empty region SP is formed in the arrangement region of the chips CP (the central portion of the substrate BRD). While forming, the outer sides of the chips CP1 to CP4 can be aligned with the arrangement region of the chip CP (outer periphery of the substrate BRD). As a result, it is possible to reduce the size of the area in which the chips CP are arranged or the size of the substrate BRD while securing the empty area SP for wiring the signal lines S.

FIG. 4 is a block diagram showing an example of a semiconductor device according to another embodiment of the present invention. The same elements as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor device SEM1 shown in FIG. 4 is different from the semiconductor device SEM1 shown in FIG. 1 in that chips CP (CP1-CP4) having a small difference in length between the long side and the short side are arranged on the substrate BRD. It has the same configuration as. Note that each chip CP may be square.

When the difference between the length of the long side and the length of the short side of each chip CP is small, when an empty area SP is created for the wiring of the signal line S, the outer side of each chip CP1-CP4 is linear. It may not be aligned, and some sides may protrude. In this case, the size of the chip arrangement region or the substrate BRD is determined according to the protruding side.

In the semiconductor device SEM2 illustrated in FIG. 4, the area of the substrate BRD increases according to the protruding side, and for example, the size of the package of the semiconductor device SEM2 increases, but the signal line S is wired using the empty area SP. The method is the same as in FIG. Therefore, similar to FIG. 1, it is possible to increase the number of signal lines S that can be wired between the chips CP facing each other via the empty area SP. Further, the variation in the length of the signal line S connecting between the opposing chips CP via the empty area SP can be reduced, so that the skew of the data transmitted via the signal line S can be reduced. As a result, the timing design can be facilitated and the performance of the semiconductor device SEM2 can be improved.

In the present specification, “to face” is not limited to “to face” so that the sides are parallel to each other. Further, terms such as parallel, orthogonal, straight line, and uniform are not limited to being used as strict meanings. That is, the above terms are allowed to include design margins, tolerances, and manufacturing variations of chips, substrates, semiconductor devices, and the like.

The present invention is not limited to the above specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

11 error detection/correction signal generation circuit 12 output flip-flop 13 output buffer 21 input buffer 22 input flip-flop 23 error detection/correction circuit 24 clock transfer circuit BP bump BRD substrate CP (CP1, CP2, CP3, CP4) chip D1, D2 Diagonal line S Signal line SEM1, SEM2 Semiconductor device

Claims (4)

Having first to third chips arranged on a substrate,
In plan view,
The first chip is adjacent to the second chip,
The third chip is adjacent to the second chip, and the third chip is surrounded by the sides of the first to third chips of the substrate, and the third chip is exposed through an empty area exposed from the first to third chips. Is arranged to face the first chip,
A semiconductor device, wherein a first signal line connecting the first chip and the third chip is wired in the empty area. Further, a fourth chip adjacent to the first chip and the third chip is provided, and the empty area is surrounded by the first to fourth chips and exposed from the first to fourth chips. The semiconductor device according to claim 1, wherein The first to third chips have a rectangular shape,
The semiconductor according to claim 1 or 2, wherein the first signal line is wired so as to extend in a direction orthogonal to a side of the first chip and the side of the third chip that face each other through the empty area. apparatus. 4. The semiconductor device according to claim 2, wherein a second signal line connecting the second chip and the fourth chip is wired in the empty area.

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