JPH06161798A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor which is equipped with a self- diagnostic function in a machine-cycle and an information processing system by simple constitution which has high reliability. CONSTITUTION:Processors 1 and 2 which have substantially the same logical function, physical constitution elements, and two physical arrangement and a comparator circuit which detects coincidence or non-coincidence between corresponding signals of the two processors 1 and 2 are formed on the same semiconductor chip or in the same package, and the output signal of the comparator circuit is led out. Consequently, they can be handled as one process from outside and signal comparisons can be made on the semiconductor chip or in the package, so the function for taking a self-diagnosis in machine cycles is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to a technique effective when used in an information processing device that requires high reliability such as space use.

[0002]

2. Description of the Related Art Fault-tolerant systems for high reliability are implemented by multiplexing devices and chips. For example, as an example of a high reliability system in which even if one of the processors fails, it can be masked by taking a majority vote of the outputs of three processors.
There is 683. As an example of achieving high reliability at the semiconductor chip level, there is US Pat. No. 4,849,657. This technique doubles the flip-flops used for the counter and takes the logical sum of the outputs so that the failure of one does not affect the whole.

[0003]

The inventor of the present application conducted a study on a processor suitable for applications such as space applications and financial applications where a system down due to a failure is not allowed even for a moment. I realized that it would be better to have a function to detect errors in units. In this way, if the processor itself can make a failure determination in the machine cycle, it becomes possible to eliminate the failure by duplicating the system.

An object of the present invention is to provide an information processing apparatus having a machine cycle self-diagnosis function. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, two processors whose logical functions, physical components and physical arrangements are substantially the same, and corresponding signals of the two processors are matched / matched.
A comparison circuit that detects a mismatch is formed in the same semiconductor chip or the same package, and the output signal of the comparison circuit is output to the outside.

[0006]

According to the above-mentioned means, since it can be handled as one processor from the outside and the signal comparison is performed within the semiconductor chip or the package, it has a failure diagnosis function in a machine cycle. be able to.

[0007]

1 is a schematic layout diagram of an embodiment of a processor according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

On the semiconductor chip, two processor modules 1 and 2 having exactly the same logical function, physical components and physical layout are mounted. In these processor modules 1 and 2, each circuit is geometrically arranged symmetrically (mirror inversion) with a substantially center line dividing a semiconductor chip into left and right as a symmetry line. A comparison circuit is provided on the line of symmetry.

FIG. 3 shows an internal block diagram of one embodiment of the line-symmetrical processor modules 1 and 2. Each circuit block in the figure is drawn according to the geometrical arrangement on the semiconductor chip.

In the processor module 1, an instruction buffer is arranged in the first stage from the top, and a decoder is arranged in the second stage. In the third stage, the control unit on the left side
An address calculation unit for calculating an address is arranged side by side on the right side. In the fourth row, a data operation unit is arranged on the left side and a general-purpose register is arranged on the right side. And
An input / output interface is arranged at the bottom.

On the other hand, in the processor module 2, similarly to the above, the first instruction buffer from the top,
The decoders are sequentially arranged in the second stage, but in the third stage, the control unit is arranged on the right side and the address operation unit is arranged on the left side, which is the opposite of the left and right of the processor module 1.
Also in the fourth stage, the data operation unit is arranged on the right side and the general-purpose register is arranged on the left side, which is opposite to the left and right of the processor module 1. An input / output interface is arranged in the lowest stage as in the processor module 1.

In the figure, the circuit elements and wirings constituting each circuit block are symmetrically arranged corresponding to the symmetrical arrangement as described above. That is, based on the processor module 1, the processor module 2 is configured by a mirror-inverted circuit pattern. Thus, the two processor modules 1 and 2 have logical functions,
The physical components and the physical arrangement are the same, and the relative relationship of the physical arrangement is line symmetric.

The reason for arranging the two processor modules 1 and 2 symmetrically with respect to the line of symmetry as in this embodiment is as follows. The comparison circuit compares the corresponding signals of the two processor modules 1 and 2. In this case, in the comparison circuit, the signal propagation time from the processor module 1 and the signal propagation time from the processor module 2 are coincident with each other in order to perform a comparison operation in real time on a signal that changes at high speed in a machine cycle. This is because it is necessary to let them do it.

In FIG. 1, a semiconductor chip contains two processor modules 1 and 2 and a comparison circuit. This semiconductor chip is configured as one semiconductor integrated circuit device by a known packaging technique, and the same input signal is supplied from the external input terminal to the two processor modules 1 and 2, and the two processor modules 1
And 2 are made to perform exactly the same operation. The signal of one of the processor modules is output to the external output terminal of the semiconductor integrated circuit device. As a result, the semiconductor integrated circuit device can be seen only as one processor module from the outside, but is different from the conventional one having only one processor in that the comparison output signal is output from the comparison circuit. Only.

When the processor modules 1 and 2 are operated by the clock pulse supplied from the outside, the external terminal to which the clock pulse is supplied is arranged near the symmetry line. As a result, the two processor modules 1 and 2 can be operated at substantially the same clock timing.

When the processor modules 1 and 2 are operated by the clock pulse generated by the clock pulse generating circuit built in the semiconductor chip as described later, the clock pulse generating circuit, like the comparison circuit, is on the symmetry line. Is located in. As a result, the clock pulse generation circuit and the clock pulse supply wiring to the two processor modules 1 and 2 are made to have substantially the same length. Instead of this configuration, each processor module 1
And 2 may each have a built-in clock pulse generation circuit. In this case, in the processor modules 1 and 2, the positions where the clock pulse generation circuits are provided are arranged symmetrically with respect to the line of symmetry so that clock pulses synchronized with each other are formed.

FIG. 2 is a schematic layout diagram of another embodiment of the processor according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by the well-known semiconductor integrated circuit manufacturing technique as described above.

On the semiconductor chip, two processor modules 1 and 2 having exactly the same logical function, physical components and physical layout are mounted. These processor modules 1 and 2 are arranged point-symmetrically with respect to a substantially central point of the semiconductor chip. That is, when the processor module 1 is rotated 180 ° with respect to the center, it becomes equivalent to the processor module 2. A comparison circuit is provided on the center point.

FIG. 4 shows an internal block diagram of an embodiment of the processor modules 1 and 2 which are made point-symmetrical. Each circuit block in the figure is drawn according to the geometrical arrangement on the semiconductor chip.

In the processor module 1, an instruction buffer is arranged in the first stage from the top, and a decoder is arranged in the second stage from the top. In the third stage, the control unit on the left side
The address calculation units are arranged side by side on the right side. In the fourth row, a data operation unit is arranged on the left side and a general-purpose register is arranged on the right side. An input / output interface is arranged at the bottom.

On the other hand, in the processor module 2, 1 in the processor module 1 described above.
Since they are rotated by 80 °, the upper and lower sides and the left and right sides are reversed. From the top, the input / output interface is on the first stage, and the general-purpose register and the data operation unit are on the second stage.
In the second stage, the address calculation unit and the control unit are arranged,
A decoder is arranged at the fourth stage and an instruction buffer is arranged at the final stage. In the second and third stages, the data operation unit and the control unit are arranged on the right side and the general-purpose register and the address operation unit are arranged on the left side, which are opposite to the left and right of the processor module 1.

In the figure, the circuit elements and wirings constituting the corresponding circuit blocks of the two processor modules 1 and 2 are provided in a vertically inverted relationship corresponding to the point symmetry as described above. . With the processor module 1 as a reference, the processor module 2 is configured by a mirror inversion and a vertically inverted circuit pattern. Thus, the two processor modules 1 and 2
Have the same logical function, physical components and physical layout,
And the relative relationship of physical arrangement is made point-symmetric.

As in this embodiment, the two processor modules 1 and 2 are arranged point-symmetrically with respect to the center point in the same manner as described above, except that the signal propagation time from the processor module 1 and the processor module 2 are arranged. This is to match the signal propagation time of. As a result, in the comparison circuit, it is possible to perform a matching operation of matching / mismatching of signals that change rapidly in a machine cycle in real time.

When two processor modules are arranged in line symmetry or point symmetry as described above, a layout design of one processor module is performed, and based on the layout design, in a memory of a computer or the like for automatically designing a semiconductor integrated circuit. The other processor module having line symmetry can be formed by mirror inversion, and the other processor module having point symmetry can be formed by performing 180 ° rotation or the mirror inversion (horizontal inversion) and vertical inversion. . Then, by arranging the comparison circuit on the symmetry line or the center point portion which is the reference of the symmetry, the layout of one semiconductor chip can be performed.

FIG. 5 shows an operation diagram for explaining an example of the output signal of the comparison circuit and the operation of the two processor modules 1 and 2 corresponding thereto. Processing 1
Each of process 3 to process 3 corresponds to one instruction. During execution of the instruction of the process 2, if any one of the plurality of signals corresponding to the two processor modules 1 and 2 does not match, the comparison circuit outputs a high-level re-execution instruction signal. . When the high-level re-execution instruction signal is supplied, the respective control units of the processor modules 1 and 2 move to the control of the re-execution process of redoing the instruction of the process 2 from the beginning.

In general, one instruction is composed of a plurality of micro program steps, and comparison and collation are performed in units of each micro instruction. Therefore, if there is a mismatch, the processing is once cleared. The instruction corresponding to process 2 is redone from the first microprogram step. If the comparison circuits match in the re-execution of the process 2, the process proceeds to the process 3. When the operation is performed properly by re-execution as described above, it is considered that the cause of the non-coincidence is caused by external noise or the like, and the comparison / coincidence signal is continuously output to the outside. This makes the processor appear to operate normally from the outside.

FIG. 6 shows an operation diagram for explaining another example of the operation of the output signal of the comparison circuit and the corresponding two processor modules 1 and 2. Each of processing 1 to processing 3 corresponds to one instruction. During the execution of the instruction of the processing 2, among the signals composed of a plurality of corresponding two processor modules 1 and 2,
If any one of them does not match, the re-execution process of re-executing the instruction of the process 2 from the beginning is performed. The process up to this point is the same as that in FIG. 5, but when a failure occurs in one of the processor modules, the comparison circuit outputs an internal comparison signal indicating a mismatch each time it is reexecuted. When such a mismatch signal is continuously output n times, it is determined that an unrecoverable failure has occurred, and the comparison circuit outputs the comparison output signal and the re-execution instruction signal indicating the mismatch signal to the outside. The internal configuration of this comparison circuit will be described in detail with reference to FIG.

If it is immediately determined that the processor has failed due to the mismatch output of the comparison circuit as described above, it is determined that the failure has occurred even when a temporary operation occurs due to external noise or the like, and thereafter the system is disconnected from the system. I will be destroyed. On the other hand, by providing the re-execution function as described above, it is possible to output the mismatch signal only for the unrecoverable failure.

In order to construct a system for which high reliability is required, such as for space use or for financial use, when the processor according to the present invention, which can be seen as only one processor from the outside, is used as a multiple structure, When a re-execution process of an instruction accompanying a mismatch occurs in one processor, the process is delayed in that processor by the re-execution. Therefore, when the re-execution is started, an inconsistency signal is output to wait for the other processors performing the simultaneous operation, and wait for the end of the process 2 of the re-executing processor to perform the process. Synchronization is attempted by entering 3. In this case, the output signal of the comparison circuit is constantly output. Then, a failure in one processor may be detected by another processor by the overflow of the wait time, and the failed processor may be disconnected from the system.

FIG. 24 shows an internal block diagram of an embodiment of the above-mentioned comparison circuit. The comparison circuit compares the data supplied from the processor modules 1 and 2,
It comprises a comparator for outputting the result as an internal comparison signal and a judging section for receiving the internal comparison signal and making a judgment. The determination unit has a flip-flop circuit FF, a set circuit STC, a counter circuit COUNT, and a result signal output circuit OC.

The flip-flop circuit FF inputs an internal comparison signal according to the clock signal CLK and outputs it to the set circuit STC and the result signal output circuit OC. If the signal supplied from the flip-flop circuit FF indicates a mismatch, the set circuit STC determines the counter circuit COUNT.
A signal that decrements (-1) the value of T is output. Further, the set circuit STC outputs a signal for setting the value in the counter circuit COUNT to a predetermined value if the signal supplied from the flip-flop circuit FF indicates a match.

The result signal output circuit OC receives the outputs of the flip-flop circuit FF and the counter circuit COUNT. The result signal output circuit OC is a flip-flop circuit F.
If the signal indicating the coincidence is supplied from F, the comparison output signal indicating the coincidence and the low-level re-execution instruction signal are output regardless of the output from the counter circuit COUNT. Further, the result signal output circuit OC includes the flip-flop circuit F.
If a signal indicating disagreement is supplied from F, a high-level re-execution instruction signal is output, and the counter circuit COUNT
A comparison output signal indicating coincidence is output until the value of 0 becomes 0 (zero). The result signal output circuit OC is a counter circuit CO.
Even if the value of UNT becomes 0, if the signal indicating the mismatch is supplied from the flip-flop circuit FF, the comparison output signal indicating the mismatch is output. Flip-flop circuit F
F and the counter circuit COUNT are reset signal RSE.
The inside is reset by T.

FIG. 7 is a schematic block diagram of an embodiment of the processor according to the present invention. Each circuit block in the figure is drawn according to the above-described line-symmetrical or point-symmetrical arrangement based on the comparison circuit.

The processors 1 and 2 each have three internal buses S1, S2 and D, and the arithmetic units have buses S1 and S.
The data input from 2 is operated and the operation result is output to the bus D. In the data holding circuit such as a register, the data of the address designated by the control circuit is stored in the bus S
1 and S2 and are input to the arithmetic unit and the like. The information on the bus D from which the above operation result is obtained is taken into a designated register of the data holding circuit as needed. The arithmetic unit outputs a flag indicating an operation state or the like to the flag register. The control circuit designates a register of the data holding circuit and gives an operation mode to the arithmetic unit according to the instruction.

Similarly to the processor 1, the processor 2 also has a three-bus system including buses S1, S2, and D, and has a data holding circuit, a computing unit, and a flag register. These buses S1, S2 and D, the data holding circuit and the arithmetic unit are arranged symmetrically with respect to the comparison circuit. As a signal to be compared, the comparison circuit performs a match / mismatch comparison operation of the write data of the buses D in the processors 1 and 2, the address signal output from the control circuit, and the corresponding operation flag output from the operation unit. .

Although the specific configuration of the comparison circuit is omitted, a plurality of exclusive OR circuits provided corresponding to the number of respective comparison signals and a logical OR receiving the outputs of these exclusive OR circuits. Composed of circuits. As a result, if there is a mismatch in even one bit among the above-described write data consisting of a plurality of bits, an address signal consisting of a plurality of bits, and an operation flag consisting of a plurality of bits, a mismatch signal is output through the OR circuit. It

FIG. 8 is a block diagram of another embodiment of the processor according to the present invention. In the figure, one of the two processors provided on one semiconductor chip as described above and a comparison circuit are shown as representatives.

In this embodiment, using a specific command word,
It is intended to detect a match / mismatch of the data in advance by designating a specific register among the registers forming the data holding circuit. That is, this instruction does not perform specific data processing by itself, but is used exclusively for testing whether or not there is an error in the contents of the register to be processed.

The decoder decodes the instruction word stored in the instruction register, the control circuit selects a specific register in the data holding circuit, and outputs the data to the internal bus S2. Since the same instruction is executed in the two processors, the comparison circuit compares the contents of the same registers in the two processors 1 and 2 and makes a match / mismatch determination.
This determination result is output to the outside, and if necessary, the processors 1 and 2 read it out, and if there is a match, the data stored in the register is used for processing, and if there is no match, the data is formed anew. Shift to processing for.

By using such a self-check function, a data error can be detected prior to data processing, so that highly reliable data processing can be performed. Such a pre-check function is effective, for example, when it is too late to find an error in the above-mentioned status setting after the result is known, when a series of status settings are performed to obtain one result.

FIG. 9 is a block diagram of still another embodiment of the processor according to the present invention. In the figure, one of the two processors provided on one semiconductor chip as described above and a comparison circuit are shown as representatives.

In this embodiment, using a specific command word,
It is intended to specify a specific data (address) stored in a built-in cache memory and detect match / mismatch of the data in advance. That is, this instruction does not perform specific data processing by itself, but is used exclusively for testing whether or not there is an error in the contents of the cache memory to be processed.

The decoder decodes the instruction word stored in the instruction register, the control circuit designates a specific address in the cache memory, and the data is output to the internal bus S2. Since the same instruction is executed in the two processors, the comparison circuit compares the data at the same address in the cache memory built in each of the two processors 1 and 2 and determines the match / mismatch. This determination result is output to the outside, and if necessary, the processors 1 and 2 read it out, and if there is a match, the data stored in the cache memory is used for processing. Transfer the data or move to a process such as creating the data again.

By using such a self-check function, it is possible to detect an error in data prior to data processing, so that highly reliable data processing can be executed. Such a pre-check function is effective, for example, when performing a series of state settings to obtain one result, and when it is too late to find an error in the above state settings after the result is known.

FIG. 10 is a block diagram showing still another embodiment of the processor according to the present invention. In the figure, one of the two processors provided in one semiconductor chip as described above is exemplarily shown as a representative.

In this embodiment, the data handled by the processor is composed of data bits DATA and error detecting party bits ECC. Therefore, the data holding circuit includes a data bit storage portion DATA and a parity bit storage portion ECC. Correspondingly, the internal buses S1, S2 and D also include a bus for data bit DATA indicated by a thick line and a bus for parity bit ECC indicated by a thin line.

With respect to the signals read to the internal buses S1 and S2, the error detection and correction decoder ECCDEC detects and corrects the error of the data bit by using the parity bit, and if there is an error, the correctly corrected data is calculated. Is input to the vessel. The arithmetic unit calculates the above data and outputs the result. At this time, the output section is provided with an error detection / correction encoder ECCENC, and a parity bit ECC is generated based on the data DATA and is output to the D bus. The data bit DATA and the parity bit ECC of this D bus are stored in a designated register of the data holding circuit or written in a cache memory or the like.

Two processors as described above are provided,
It is compared by the comparison circuit. In this case, as shown in FIG. 7, as the write data, the data bit DATA and the parity bit ECC are input to the comparison circuit, and the match / mismatch is determined. By adding such an error correction function, the data error in a certain range is corrected, so that the reliability can be further improved.

FIG. 11 is a block diagram showing still another embodiment of the processor according to the present invention. In the figure, a schematic block diagram of a data processing system is shown in addition to a processor configured by a large-scale integrated circuit. In this embodiment, the processor has multiple functions. The two processors 1 and 2 are used not only for high reliability but also as a multiprocessor. Such a function change is performed by setting a mode in the mode register.

The processors 1 and 2 each have a cache memory and are connected to the internal common bus through the logic circuits LOG1 and LOG2 for acquiring the internal bus. In order to arbitrate the internal common bus when the two processors 1 and 2 are operated independently, an arbiter is provided to control the logic circuits LOG1 and LOG2 to perform bus acquisition adjustment. .

The mode register enables the operation of the comparison circuit when the high-reliability processor mode is set, but the operations of the arbiter and the logic circuits LOG1 and LOG2 are disabled, and the two processors 1 and 2 are connected to the internal common bus. Are connected in parallel with each other and simultaneously perform the same data processing operation.

The mode register disables the operation of the comparator circuit when placed in the multiprocessor mode, and instead enables the operations of the arbiter and logic circuits LOG1 and LOG2. When the processor 1 wants to acquire the internal common bus, it outputs a bus request signal to the arbiter via the logic circuit LOG1. Arbiter is the other processor 2
When the bus is not used, the processor 1 acquires the internal common bus because it outputs the enable signal. If the bus request signals conflict, the arbiter outputs a permission signal to one of the processors according to a predetermined priority order, and the other goes into a waiting state.

The mode register may be set by hardware. That is, when used as a multiprocessor by the user,
When the processor is mounted on the mounting board, wiring is performed so as to supply a high level to a specific terminal. When setting the mode register by software,
The mode register may be set in the initial setting.

FIG. 12 is a block diagram showing still another embodiment of the processor according to the present invention. In this embodiment, the two processors 1 and 2 are arranged asymmetrically on the semiconductor chip. That is, two processors 1
2 and 2 are provided side by side with the same arrangement on the left and right sides and the top and bottom sides. A comparison circuit is provided between the two processors 1 and 2.

In this case, the distance between the general-purpose register of the processor 2 on the right side and the comparison circuit becomes longer than the distance between the general-purpose register of the processor 1 on the left side and the comparison circuit. Therefore, in order to correct the delay time of signal propagation due to the length of this distance, a transmission delay correction part is provided between the comparison circuit and the processor 1. This transmission delay correction part is
Propagation delay is caused by routing the signal line, or propagation delay is caused by using a delay element such as a dummy transmission gate MOSFET. With this configuration, the circuit pattern of one processor module can be copied as it is to form the other processor module.

FIG. 13 shows a block diagram of still another embodiment of the processor according to the present invention. In this embodiment, the two processors 1 and 2 are arranged line-symmetrically, but the comparison circuit is arranged at a position on the extension of the line of symmetry. That is, the signals to be compared by the two processors 1 and 2 extend downward along the line of symmetry and are guided to the comparison circuit. Even in this configuration, the comparison circuit has 2
The two signal transmission paths can be made substantially equal to each other, and the influence of signal delay can be reduced.

FIG. 14 is a block diagram showing still another embodiment of the processor according to the present invention. In this embodiment, the clock generation circuit CPG is mounted on the semiconductor chip as described above. The clock generation circuit CPG is arranged on the line of symmetry in which the comparison circuit is provided, and transmits the clock pulse CK to the two processors 1 and 2 with the same wiring length. As a result, in the circuit block in which the signal transmission path of the clock pulse is also symmetrical and has a symmetrical relationship,
The clock pulse CK is supplied with almost the same delay time.

A latch circuit FF is provided in the comparison circuit. The latch circuit FF receives the latch clock LCK formed by the clock generation circuit CPG and takes in the comparison output in synchronization with the clock edge. This makes it possible to obtain a stable comparison output signal without outputting a whisker-like pulse due to a delay time difference of signals compared in the comparison circuit.

The output signal of the latch circuit FF is transmitted to the processors 1 and 2 as the re-execution signal RT as shown in FIG. 5 or 6. Although not shown in the figure, a counter circuit for detecting that the re-execution signal RT of the latch circuit FF is continuously output a plurality of times (n times) is provided. A comparison output signal is formed. That is, this counter circuit
It counts the RT signals and is reset by the comparison match signal. As a result, when the RT signal is continuously output n times, the comparison output signal is output as a mismatch signal such as a high level.

FIG. 15 shows a timing chart for explaining the comparison operation. The register address and write data are output in synchronization with the rising edge of the clock to the high level. A write operation is performed on the register designated by the write enable signal generated at a timing delayed by a half cycle with respect to the clock, and the output of the register changes to the written data. The calculation result is changed with a delay of the calculation time by the calculation unit.

A latch clock is generated in synchronism with the write enable signal and at a timing slightly later than that, and the comparison output that has passed through the exclusive OR circuit and the OR circuit is fetched. When the comparison results do not match, the high-level re-execution instruction signal RT is output. If the comparison results match, a low level is output. In this way, since the comparison result is fetched in synchronization with the latch clock, even if there is some deviation in the register address, write data, or the signal to be compared with the register output or flag, it is not affected and stable comparison output can be obtained. Obtainable.

By performing coincidence detection on a clock-by-clock basis in this way, the time interval from failure occurrence to detection can be made smaller. Further, since it is possible to detect a failure in clock units, it is possible to add the re-execution processing function as described above, and it is possible to obtain a processor that is robust against a temporary failure.

FIG. 16 is a schematic layout diagram of still another embodiment of the processor according to the present invention.
In a semiconductor integrated circuit such as a CMOS circuit, it is necessary to take measures against latch-up caused by operation of a parasitic thyristor element in addition to malfunction of a logic circuit due to noise or the like. Conventionally, a current flowing in a circuit is sensed, and when an excess current flows, a power supply protection circuit or the like shuts off the power to prevent element destruction. With this configuration, there is an inconvenience that the power supply is shut down even in another semiconductor integrated circuit device that is normally operating. In particular, in the case of a system such as space use or financial system where temporary suspension of the system is not allowed, it is necessary to make a multiple system including the power supply device, so that the scale of the entire system becomes large.

In this embodiment, a latch-up countermeasure interface region is provided on the semiconductor chip so as to surround the processors 1 and 2 and the comparison circuit formed therein. A latch-up recovery control circuit is provided outside the latch-up countermeasure interface area. The latch-up recovery control circuit is composed of an element or a circuit in which a layout rule is relaxed so that the latch-up recovery control circuit does not latch up. The latch-up countermeasure interface area may be a constant buffer area in which the latch-up recovery control circuit is not affected by the latch-up that has occurred in the processors 1 and 2 or the comparison circuit.

A block diagram of one embodiment of the processor of FIG. 16 is shown in FIG. The power supply voltage VCC supplied from the outside is supplied to the internal processors 1 and 2 and the comparison circuit via the switch a and the overcurrent detection resistor. The signal input to the processors 1 and 2 is supplied via the switch b. The latch-up recovery control circuit monitors the voltage drop Vr of the detection resistor, and as shown in the waveform diagram of FIG. 18, detects a voltage Vr corresponding to an overcurrent that is considered to be latch-up, Immediately turn off switches a and b. As a result, element destruction of the internal circuit due to latch-up can be prevented.

The latch-up recovery control circuit turns on the switch a after a certain period of time to re-input the power supply voltage VCC to the internal circuit. Then, after a delay, the switch b is turned on to start supplying the input signal. This enables the internal processors 1 and 2 and the comparison circuit to operate again.

With this configuration, in a plurality of semiconductor integrated circuit devices having a common power supply device, the power supply is cut off by itself only in the semiconductor integrated circuit device in which the latch-up has occurred to prevent element destruction. Therefore, the operation can be continued in other semiconductor integrated circuit devices that share the above power supply device. By thus incorporating the latch-up countermeasure circuit in the semiconductor integrated circuit device, the power supply device can be used in common even in the case of configuring a multiple system, so that the entire system can be simplified.

FIG. 19 is a mounting layout diagram of an embodiment of the processor according to the present invention. In this embodiment, a plurality of semiconductor chips are mounted in one semiconductor integrated circuit device. That is, three semiconductor chips are mounted on a wiring board made of ceramic or the like, and can be handled from the outside like one semiconductor integrated circuit device.

The semiconductor chips constituting the processor modules 1 and 2 have exactly the same logical function and physical constituent elements, and the two processor modules 1 and 2 are left and right with respect to the symmetry line on the mounting board. Arranged symmetrically. That is, when these processor modules 1 are used as a reference, the processor module 2 is a semiconductor chip that is laid out in a left-right reversed manner. On the symmetry line on the mounting substrate that divides the processor modules 1 and 2 as the semiconductor chips into the left and right, a comparison circuit including one semiconductor chip is provided.

The processor modules 1 and 2 composed of the two semiconductor chips have the same relationship as the two processor modules formed in the one semiconductor chip shown in the above item 3. That is, the general-purpose register exemplarily shown as a representative is arranged at a position symmetrical with respect to the line of symmetry in which the comparison circuit is provided. For example, based on the processor module 1, the processor module 2 is a semiconductor chip having a mirror-inverted circuit pattern. As described above, the two processor modules 1 and 2 have the same logical function, physical constituent elements, and physical arrangement on a mounting board such as a ceramic board, and the relative physical arrangement is line-symmetric. .

The reason for arranging the two processor modules 1 and 2 symmetrically with respect to the line of symmetry as in this embodiment is as follows. The comparison circuit compares the corresponding signals of the two processor modules 1 and 2. In this case, in the comparison circuit, the signal propagation time from the processor module 1 and the signal propagation time from the processor module 2 are omitted in order to perform a comparison operation in real time for a signal that changes at high speed in a machine cycle. This is because it is necessary to match them.

In FIG. 19, these semiconductor chips are configured as one semiconductor integrated circuit device by a known packaging technique, and the same input signal is supplied from the external input terminal to the two processor modules 1 and 2. The two processor modules 1 and 2 are made to perform exactly the same operation. The signal of one of the processor modules is output to the external output terminal of the semiconductor integrated circuit device. As a result, the semiconductor integrated circuit device can be seen only as one processor module from the outside, but is different from the conventional one processor in that the comparison output signal is output from the comparison circuit. .

When the processor modules 1 and 2 are operated by the clock pulse supplied from the outside, the external terminal to which the clock pulse is supplied is arranged close to the symmetry line. As a result, the two processor modules 1 and 2 can be operated at substantially the same clock timing.

When the processor modules 1 and 2 are operated by the clock pulse formed by one clock pulse generating circuit formed on the mounting board as described above, the clock pulse generating circuit is the same as the comparison circuit. Are arranged on the line of symmetry on the mounting board. As a result, the clock pulse generation circuit and the clock pulse supply wiring to the two processor modules 1 and 2 are made to have substantially the same length. Instead of this configuration, each of the processor modules 1 and 2 may have a built-in clock pulse generation circuit. In this case, in the processor modules 1 and 2 each made of a semiconductor chip, the positions where the clock pulse generation circuits are provided are arranged symmetrically with respect to the line of symmetry so that clock pulses synchronized with each other are formed. .

FIG. 20 shows the mounting layout of an embodiment of the processor according to the present invention. Also in this embodiment, a plurality of semiconductor chips are mounted in one semiconductor integrated circuit device as in the above. That is, three semiconductor chips are mounted on a wiring board made of ceramic or the like, and can be handled from the outside like one semiconductor integrated circuit device.

For the semiconductor chip, two processor modules 1 and 2 having the same logical function, physical components and physical layout are used. The semiconductor chips constituting these processor modules 1 and 2 are arranged point-symmetrically with respect to the substantially center point of the mounting board. That is, when the processor module 1 is rotated 180 ° with respect to the center, it becomes equivalent to the processor module 2. A semiconductor chip forming a comparison circuit is provided on the center point.

In this structure, the identical semiconductor chips can be formed by arranging point-symmetrically with respect to a mounting substrate such as a ceramic substrate. As a result, since the processor modules 1 and 2 can be exactly the same, it is possible to use two types of semiconductor chips formed so that the internal circuits are symmetrical as in the embodiment of FIG. It will be easier than that.

FIG. 21 is a block diagram showing an embodiment of a multiple voting system using a processor according to the present invention. In this embodiment, a plurality of information processing systems that can be operated simultaneously with the same function are configured.
The processor is one in which two processor modules and a comparison circuit, or two processor chips and a comparison chip are mounted in one package as in the above-described embodiment, and is treated as one processor on the mounting board as shown in FIG. Be seen.

The error detection circuit detects an error due to the processing of the processor and is a check circuit used in the conventionally known fault tolerant system. In the self-diagnosis circuit of this embodiment, in addition to the conventional error detection as described above, the comparison result determined by the processor itself is input.

In the self-diagnosis, when an error is detected, the switch is controlled by itself and the board is disconnected as a defective board. A majority operation is executed on the remaining boards excluding such defective boards, and the processed data is output.

FIG. 22 is a block diagram showing an embodiment of one system in the multiple voting system in which the processor according to the present invention is used. In this example,
A board recovery function is added when a failure occurs.

When a failure is detected by the self-diagnosis as described above, the switch SW is immediately cut off to disconnect the own board from the system. In this disconnected state, the self-diagnosis circuit resets the peripheral function and the processor. In the entire system, the management program monitors the failure status for each fixed break.
If there is a faulty board, check the memory contents,
Restore the system after performing recovery processing such as resetting data. At this time, since the processor has the comparison circuit, it is possible to easily grasp whether or not the processor itself has a cause of failure by executing the test program. That is, when there is no such failure of the processor itself, the contents of the memory and the resetting of the data as described above are performed to restore the failed board to the system. This makes it possible to recover a failed board with high reliability.

The monitoring of the board in which the above failure has occurred may be professionally performed by a management processor provided separately. That is, the communication function may be used to connect to the management processor to determine the failure of the processor inside the board, confirm the contents of the memory, and reset the data. When such a management processor is provided, the failed board can be immediately restored again at a certain processing interval, so that the processing efficiency of the system is not sacrificed.

Since the processor according to the present invention itself determines a failure, even in a dual system having two processors, the processor side in which the failure has occurred can be easily identified and masked. The system can be simplified. It should be noted that a system of one system is prepared with a spare processor, and when the processor which has failed due to self-diagnosis of the processor is disconnected from the system by itself, the spare processor is connected to the system. Good.

FIG. 23 is a block diagram showing another embodiment of the multiple voting system using the processor according to the present invention. In this embodiment, a plurality of information processing systems that can be operated simultaneously with the same function are configured. As shown in FIGS. 5 and 6, the processor has two processor modules PM1 and PM2 having a re-execution function and a comparison circuit, or two processor chips and a comparison chip mounted in one package. Thus, it is treated as one processor on the mounting board.

By the re-execution function as described above, the re-execution process is performed in the processor in which the mismatch signal is detected in the comparison circuit. At this time, the wait timing control circuit receives a high-level re-execution instruction signal from the processor on each board and issues a wait signal to the processor on another board. As a result, the other processors are kept in a wait state and synchronized with each other during the re-execution. As described above, if the re-execution instruction signal is issued from any of the processors, a wait signal having a length corresponding to the period is issued to each processor to establish synchronization.

With the addition of such a comparison re-execution function,
When an error due to noise or the like occurs in one processor on the board, the board is not immediately judged to be broken and the board is not separated, so that a highly reliable fault-tolerant system can be obtained.

The operational effects obtained from the above embodiment are as follows. That is, (1) two processors whose logical functions, physical components, and physical arrangements are substantially the same, and a comparison circuit for detecting a match / mismatch of corresponding signals of the two processors. By forming them in the same semiconductor chip or in the same package and outputting the output signal of the comparison circuit to the outside, it can be handled as one processor from the outside, and the signal comparison in the semiconductor chip or package can be performed. Since this is performed, it is possible to obtain the effect of providing a failure diagnosis function in the machine cycle.

(2) Since two processors and a comparison circuit are apparently mounted on one semiconductor integrated circuit device, it is possible to obtain the effect of reducing the size and weight of the system.

(3) By arranging two processor modules symmetrically with respect to the comparison circuit on the semiconductor chip or the mounting board, or by using delay means for making the propagation delay times of both signals equal, the comparison circuit Since the signal propagation delay times with respect to are set to be substantially equal to each other, it is possible to obtain an effect of being able to operate with a clock pulse at a higher frequency.

(4) Of the circuit blocks in the two processor modules, the block for sending a signal to the comparison circuit is arranged close to the comparison circuit and the signal transmission path is shortened. The effect that the frequency of can be made higher can be obtained.

(5) In the detection operation of the comparison circuit, the same information processing operation is repeated and re-executed by the two processor modules up to the number of times determined in advance by the mismatch output, and even if the number of times is exceeded. In addition, by providing the function of sending the non-coincidence output to the outside when the non-coincidence occurs, it is possible to obtain an effect that it is possible to obtain a processor that is strong against a disturbance due to noise or the like.

(6) By providing the two processor modules with the data error detection and correction functions, the effect that higher reliability can be obtained can be obtained.

(7) The two processor modules are
An effect that a data error or the like can be detected in advance by having a specific command function of designating specific data stored in the data holding circuit or the built-in cache memory and sending it to the comparison circuit Is obtained.

(8) By providing a latch-up recovery control circuit, detecting an overcurrent in the internal circuit, shutting off the power supply voltage VCC and the input signal supplied from the outside, and turning them on again after a fixed period, In a plurality of semiconductor integrated circuit devices having a common power supply device, only the semiconductor integrated circuit device in which latch-up has occurred shuts down the power supply itself to prevent element destruction. The effect is that they can be shared.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the processor may be a general-purpose processor that performs data processing according to a predetermined program, or a special processor that performs specialized data processing such as multiplication and division. The signals compared in the comparison circuit are appropriately selected according to the function of the processor. INDUSTRIAL APPLICABILITY The present invention can be widely used for an information processing device that is formed by a single semiconductor integrated circuit device in appearance.

[0097]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, two processors whose logical functions, physical components and physical arrangements are substantially the same, and corresponding signals of the two processors are matched / matched.
By forming a comparison circuit for detecting a mismatch in the same semiconductor chip or in the same package and outputting the output signal of the comparison circuit to the outside, it can be handled as one processor from the outside and the semiconductor chip or Since the signal comparison is performed within the package, it is possible to provide a fault diagnosis function in the machine cycle.

[Brief description of drawings]

FIG. 1 is a schematic layout diagram showing an embodiment of a processor according to the present invention.

FIG. 2 is a schematic layout diagram showing another embodiment of the processor according to the present invention.

FIG. 3 is an internal block diagram showing an embodiment of processor modules 1 and 2 which are line-symmetrical to each other as shown in FIG.

FIG. 4 is an internal block diagram showing an embodiment of the processor modules 1 and 2 which are point-symmetrical as shown in FIG.

FIG. 5 is an operation diagram for explaining an example of an output signal of a comparison circuit and an operation of two processor modules 1 and 2 corresponding to the output signal.

FIG. 6 is an operation diagram for explaining another example of the output signal of the comparison circuit and the operation of the two processor modules 1 and 2 corresponding thereto.

FIG. 7 is a schematic block diagram showing an embodiment of a processor according to the present invention.

FIG. 8 is a block diagram showing another embodiment of the processor according to the present invention.

FIG. 9 is a block diagram showing another embodiment of the processor according to the present invention.

FIG. 10 is a block diagram showing still another embodiment of the processor according to the present invention.

FIG. 11 is a block diagram showing still another embodiment of the processor according to the present invention.

FIG. 12 is a block diagram showing still another embodiment of the processor according to the present invention.

FIG. 13 is a block diagram showing still another embodiment of the processor according to the present invention.

FIG. 14 is a block diagram showing still another embodiment of the processor according to the present invention.

15 is a timing chart for explaining an example of a comparison operation of the comparison circuit of FIG.

FIG. 16 is a schematic layout diagram showing still another embodiment of the processor according to the present invention.

17 is a block diagram illustrating an embodiment of the processor of FIG.

FIG. 18 is a waveform chart for explaining an example of the operation of the circuit of FIG.

FIG. 19 is a layout view showing an embodiment of a processor according to the present invention.

FIG. 20 is a layout view showing another embodiment of the processor according to the present invention.

FIG. 21 is a block diagram showing an embodiment of a multiple voting system in which the processor according to the present invention is used.

FIG. 22 is a block diagram showing an example of one system in a multiple voting system in which a processor according to the present invention is used.

FIG. 23 is a block diagram showing another embodiment of the multiple voting system in which the processor according to the present invention is used.

FIG. 24 is an internal configuration diagram showing an embodiment of the comparison circuit.

[Explanation of symbols]

S1, S2, D ... Internal bus, ECCDEC ... Error detection / correction decoder, ECCENC ... Error detection / correction encoder, DATA ... Data bit, ECC ... Error detection / correction bit, CPG ... Clock generation circuit, CK ... Clock pulse, LCK ... Latch clock, RT ... Re-execution signal,
LOG1, LOG2 ... Logic circuit, PM1, PM2 ... Processor module.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuhiro Nosue 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Information Technology Division (72) Inventor Nokeikei Takahashi Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa 216 Incorporated company Hitachi, Ltd. Information & Communication Division (72) Inventor Seiji Kubo 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi, Ltd. Musashi Factory

Claims (12)

[Claims] Claim: What is claimed is: 1. Two processor modules whose logical functions, physical components and physical arrangements are made substantially the same, and a match / mismatch of corresponding signals in the two processor modules are detected. An information processing device, characterized in that the comparator circuit to be output to the outside is formed on the same semiconductor chip. 2. The two processor modules are arranged symmetrically with respect to the comparison circuit so that the signal propagation delay times with respect to the comparison circuit are made substantially equal to each other. Information processing equipment. 3. A signal propagation delay time difference between the other processor module and the comparison circuit is provided in a signal path on the side of one of the two processor modules, which is provided close to the comparison circuit. The information processing apparatus according to claim 1, further comprising delay means for compensating. 4. Of the circuit blocks in the two processor modules, a block for sending a signal to a comparison circuit is arranged so as to be close to the comparison circuit, and a signal transmission path is shortened. The information processing apparatus according to claim 1 or 2, characterized in that. 5. The detection operation of the comparison circuit causes the two processor modules to repeatedly execute the same information processing operation up to a predetermined number of times due to the mismatch output, and even if the number of times is exceeded. The information processing apparatus according to claim 1, claim 2, claim 3, or claim 4, wherein the mismatch output is sent to the outside when the mismatch occurs. 6. The two processor modules have a data error detecting and correcting function, and the comparator circuit is supplied with the corrected data. The information processing apparatus according to claim 2, claim 3, claim 4, or claim 5. 7. The comparison circuit comprises data for a data holding circuit, an address signal, and an operation flag, claim 1, claim 2, claim 3, claim 4, claim 5, or claim 5. 6. The information processing device of 6. 8. The two processor modules have a specific command function of designating specific data stored in a data holding circuit and sending it to a comparison circuit. The information processing apparatus according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7. 9. The two processor modules have a cache memory, and have a specific instruction function of designating specific data stored in each cache memory and sending it to a comparison circuit. The information processing apparatus according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7. 10. The semiconductor chip on which the two processor modules and the comparison circuit are formed is provided with a latch-up recovery control circuit at a position electrically separated from them.
A switch for disconnecting a power supply voltage and an input signal supplied to an internal circuit including two processor modules and a comparison circuit by a latch-up detection signal formed by the latch-up recovery control circuit is provided. The information processing apparatus according to claim 1. 11. Detecting a match / mismatch between two processor chips whose logical functions, physical components and physical arrangements are substantially the same, and corresponding signals in the two processor chips. An information processing device, wherein a comparison circuit chip to be output to the outside is mounted in the same package of a semiconductor integrated circuit device. 12. The two processor chips are arranged symmetrically with respect to the comparison circuit chip so that the signal propagation delay times with respect to the comparison circuit chip are made substantially equal to each other. 11 information processing device.