JP2020064937A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2020064937A JP2020064937A JP2018195176A JP2018195176A JP2020064937A JP 2020064937 A JP2020064937 A JP 2020064937A JP 2018195176 A JP2018195176 A JP 2018195176A JP 2018195176 A JP2018195176 A JP 2018195176A JP 2020064937 A JP2020064937 A JP 2020064937A
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- Prior art keywords
- solder
- semiconductor device
- pressure
- reflow
- void
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
Description
10:半導体素子
20:封止体
22:上側導体板
24:上側導体板
26:導体スペーサ
28:信号端子
30:ボンディングワイヤ
42、44、46:はんだ層
42a、44a:はんだ膜
Vo:ボイド
Claims (1)
- 半導体装置の製造方法であって、
大気圧よりも低い第1圧力下においてはんだ材を溶融及び再凝固させることにより、第1部品上にはんだ膜を形成する第1リフロー工程と、
前記第1圧力以下である第2圧力下において、前記はんだ膜を溶融及び再凝固させることにより、前記第1部品を第2部品にはんだ接合する第2リフロー工程と、
を備える製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018195176A JP2020064937A (ja) | 2018-10-16 | 2018-10-16 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018195176A JP2020064937A (ja) | 2018-10-16 | 2018-10-16 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2020064937A true JP2020064937A (ja) | 2020-04-23 |
Family
ID=70387550
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018195176A Pending JP2020064937A (ja) | 2018-10-16 | 2018-10-16 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP2020064937A (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5368571A (en) * | 1976-11-30 | 1978-06-19 | Nec Home Electronics Ltd | Production of semiconductor device |
JP2001058259A (ja) * | 1999-06-18 | 2001-03-06 | Shinko Seiki Co Ltd | 半田付け方法及び半田付け装置 |
JP2006281309A (ja) * | 2005-04-05 | 2006-10-19 | Toyota Motor Corp | 接合構造体の製造方法 |
JP2007000915A (ja) * | 2005-06-27 | 2007-01-11 | Shinko Seiki Co Ltd | 半田付け方法及び半田付け装置 |
JP2010000513A (ja) * | 2008-06-18 | 2010-01-07 | Sharp Corp | 接合構造体の製造方法 |
-
2018
- 2018-10-16 JP JP2018195176A patent/JP2020064937A/ja active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5368571A (en) * | 1976-11-30 | 1978-06-19 | Nec Home Electronics Ltd | Production of semiconductor device |
JP2001058259A (ja) * | 1999-06-18 | 2001-03-06 | Shinko Seiki Co Ltd | 半田付け方法及び半田付け装置 |
JP2006281309A (ja) * | 2005-04-05 | 2006-10-19 | Toyota Motor Corp | 接合構造体の製造方法 |
JP2007000915A (ja) * | 2005-06-27 | 2007-01-11 | Shinko Seiki Co Ltd | 半田付け方法及び半田付け装置 |
JP2010000513A (ja) * | 2008-06-18 | 2010-01-07 | Sharp Corp | 接合構造体の製造方法 |
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