JP2019533909A - 電子デバイス製造用のロードポートの機器、システム、及び方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
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- 238000007906 compression Methods 0.000 description 12
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- 238000007789 sealing Methods 0.000 description 4
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67772—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving removal of lid, door, cover
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67766—Mechanical parts of transfer devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67775—Docking arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
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Abstract
Description
本出願は、2016年11月10日に出願された、「ELECTRONIC DEVICE MANUFACTURING LOAD PORT APPARATUS, SYSTEMS, AND METHODS」と題する米国特許通常出願第15/348,961号(代理人整理番号24538‐03/米国)に対する優先権を主張する。当該通常出願は、すべての目的のために、その全体が参照により本明細書に援用される。
Claims (15)
- 電子デバイス製造システムの基板キャリアとファクトリインターフェースとのインターフェースとなるように構成されたロードポートであって、
前記ファクトリインターフェースのハウジングの前面に連結するように構成されたパネルであって、前記パネルが前記ハウジングの前記前面に面する後表面を有し、前記後表面が前記パネルの外側部分に沿って延びる溝を有し、前記溝が頸部と広がった基部とを備え、前記頸部が前記広がった基部内へと延びる長方形の断面を有する、パネルと、
前記溝内に嵌め込まれたシールであって、前記パネルが前記ハウジングの前記前面と連結されているときに、前記前面と係合するように構成された、シールとを備える、ロードポート。 - 前記溝が、前記パネルの外側外縁に沿って延びる、請求項1に記載のロードポート。
- 前記溝の頸部に対する深さの幅の比の値が約1.1‐1.3の範囲であるか、または前記溝が、約3.8mm‐4.6mmの範囲である深さと、約3.2mm‐3.8mmの範囲である頸部の幅と、約1.8mm‐2.2mmの範囲である頸部の深さとを有している、請求項1に記載のロードポート。
- 前記広がった基部が、約30°〜約35°の範囲の側壁角を有する、請求項1に記載のロードポート。
- 前記シールが長方形の断面を有し、前記シールが前記溝内に嵌め込まれているときに、前記頸部が前記シールの前記長方形の断面を約27%‐33%圧縮するように構成されている、
請求項1に記載のロードポート。 - 前記シールが、長方形の断面を有し、前記シールの幅に対する高さの比の値が約2.0‐2.4の範囲であるか、または前記シールが、高さを有し、最高で該高さの約35%‐40%が前記溝内に嵌め込まれている、
請求項1に記載のロードポート。 - 前記シールが、前記溝内に嵌め込まれているときに、溝を超えて出ている長さを有し、前記パネルが前記前面に連結されているときに、前記シールの前記溝を超えて出ている長さが約50%‐60%圧縮されるように構成されている、請求項1に記載のロードポート。
- 前記シールが、EPDM(エチレンプロピレンジエンモノマー)発泡材料から構成されているか、FKM(フルオロエラストマー)の押出成形された保持フィンガ付きバルブシールを含んでいる、請求項1に記載のロードポート。
- 電子デバイス製造システムのファクトリインターフェースであって、
請求項1に記載のロードポートと、
前面及び後面を有するハウジングであって、前記前面は前記ロードポートに連結されており、前記後面は基板処理ツールに連結されるように構成されている、ハウジングとを備える、ファクトリインターフェース。 - 基板処理ツールと、
ファクトリインターフェースであって、
前面及び後面を有するハウジングであって、前記前面は前面開口を有し前記後面は前記基板処理ツールに連結されているハウジングと、
基板キャリアとのインターフェースとなるように構成されたロードポートと
を備えるファクトリインターフェースと、
を備える電子デバイス製造システムであって、
前記ロードポートが、
前記ハウジングの前記前面開口で前記前面に連結されたパネルであって、前記パネルが前記ハウジングの前記前面に面している後表面を有し、前記後表面が前記パネルの外側部分に沿って延びる溝を有し、前記溝が頸部と広がった基部とを有し、前記頸部が前記広がった基部へと延びる長方形の断面を有する、パネルと、
前記溝内に嵌め込まれたシールであって、前記シールは、前記パネルが前記ハウジングの前記前面に連結されているときに前記前面と係合するように構成されている、シールと、を備える、電子デバイス製造システム。 - 前記溝の頸部に対する深さの幅の比の値が約1.1‐1.3の範囲であるか、または、前記広がった基部が、約30°〜35°の範囲である側壁角を有している、請求項10に記載の電子デバイス製造システム。
- 前記シールが長方形の断面を有し、前記シールが前記溝内に嵌め込まれているときに、前記頸部が前記シールの前記長方形の前記断面を約27%‐33%圧縮するように構成されている、
請求項10に記載の電子デバイス製造システム。 - 前記シールが長方形の断面を有し、前記シールの幅に対する高さの比の値が約2.0‐2.4の範囲である、請求項10に記載の電子デバイス製造システム。
- 電子デバイス製造システムのファクトリインターフェースを組み立てる方法であって、前記方法が、
基板キャリアとのインターフェースになるように構成されたロードポートであって、後表面を有するパネルを備えるロードポートを設けることと、
前記パネルの前記後表面に、前記パネルの外側部分に沿って延びる溝を設けることであって、前記溝が、頸部と広がった基部とを有しており、前記頸部が前記広がった基部へと延びる長方形の断面を有する、溝を設けることと、
前記溝内にシールを嵌め込むことと、を含む方法。 - 前記溝の頸部に対する深さの幅の比の値を約1.1‐1.3にすること、または前記シールの断面を長方形にし、前記シールの幅に対する高さの比の値を約2.0‐2.4にすることをさらに含む、請求項14に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/348,961 US10453727B2 (en) | 2016-11-10 | 2016-11-10 | Electronic device manufacturing load port apparatus, systems, and methods |
US15/348,961 | 2016-11-10 | ||
PCT/US2017/060966 WO2018089711A1 (en) | 2016-11-10 | 2017-11-09 | Electronic device manufacturing load port apparatus, systems, and methods |
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JP2021032445A Division JP7061707B2 (ja) | 2016-11-10 | 2021-03-02 | 電子デバイス製造用のロードポートの機器、システム、及び方法 |
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JP2019533909A true JP2019533909A (ja) | 2019-11-21 |
JP6847215B2 JP6847215B2 (ja) | 2021-03-24 |
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JP2019524217A Active JP6847215B2 (ja) | 2016-11-10 | 2017-11-09 | 電子デバイス製造用のロードポートの機器、システム、及び方法 |
JP2021032445A Active JP7061707B2 (ja) | 2016-11-10 | 2021-03-02 | 電子デバイス製造用のロードポートの機器、システム、及び方法 |
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US (2) | US10453727B2 (ja) |
JP (2) | JP6847215B2 (ja) |
KR (2) | KR102479460B1 (ja) |
CN (2) | CN109906502B (ja) |
TW (1) | TWI743246B (ja) |
WO (1) | WO2018089711A1 (ja) |
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US10453727B2 (en) | 2019-10-22 |
US10950476B2 (en) | 2021-03-16 |
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KR20190064684A (ko) | 2019-06-10 |
US20180130687A1 (en) | 2018-05-10 |
CN109906502A (zh) | 2019-06-18 |
JP2021106273A (ja) | 2021-07-26 |
CN109906502B (zh) | 2023-10-17 |
CN117276157A (zh) | 2023-12-22 |
JP7061707B2 (ja) | 2022-04-28 |
KR102479460B1 (ko) | 2022-12-19 |
KR20210123394A (ko) | 2021-10-13 |
TW201818495A (zh) | 2018-05-16 |
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JP6847215B2 (ja) | 2021-03-24 |
US20200043769A1 (en) | 2020-02-06 |
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