JP2019101863A - 演算装置 - Google Patents
演算装置 Download PDFInfo
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- JP2019101863A JP2019101863A JP2017233477A JP2017233477A JP2019101863A JP 2019101863 A JP2019101863 A JP 2019101863A JP 2017233477 A JP2017233477 A JP 2017233477A JP 2017233477 A JP2017233477 A JP 2017233477A JP 2019101863 A JP2019101863 A JP 2019101863A
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- Prior art keywords
- input processing
- switch
- processing logic
- arithmetic
- logic
- Prior art date
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- 238000001514 detection method Methods 0.000 claims description 12
- 238000004891 communication Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8076—Details on data register access
- G06F15/8084—Special arrangements thereof, e.g. mask or switch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Human Computer Interaction (AREA)
- Stored Programmes (AREA)
- Electronic Switches (AREA)
- Microcomputers (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
Abstract
Description
2A CPU(選択部、演算部)
2B ROM(記憶部)
SW スイッチ
SW11 オルタネートスイッチ
SW12 モメンタリスイッチ
SW13 パルスを出力するスイッチ
Claims (6)
- スイッチの入力処理を行う演算装置であって、
複数種類の入力処理ロジックが記憶されている記憶部と、
複数種類の入力処理ロジックの1つを選択する選択部と、
前記選択部により選択された入力処理ロジックに従って前記スイッチの入力処理を実行する演算部と、を備えたことを特徴とする演算装置。 - 外部機器と通信する通信部をさらに備え、
前記選択部は、前記外部機器との通信により、前記外部機器から指定された入力処理ロジックを選択することを特徴とする請求項1に記載の演算装置。 - 前記記憶部には、オルタネートスイッチのオン、オフを検出する入力処理ロジックと、前記オルタネートスイッチのオン、オフの検出及び前記オルタネートスイッチのオンからオフの切り替え間隔又はオフからオンの切り替え間隔を検出する入力処理ロジックと、が記憶されていることを特徴とする請求項1又は2に記載の演算装置。
- 前記記憶部には、モメンタリスイッチのオンからオフの切り替え又はオフからオンの切り替えを検出する入力処理ロジックと、前記モメンタリスイッチのオンからオフの切り替え又はオフからオンの切り替えの検出及び前記モメンタリスイッチの規定時間以上のオンを検出する入力処理ロジックと、が記憶されていることを特徴とする請求項1〜3何れか1項に記載の演算装置。
- 前記記憶部には、オルタネートスイッチ用の入力処理ロジック、モメンタリスイッチ用の入力処理ロジック、及び、操作量に応じた数のパルスを出力するスイッチ用の入力処理ロジック、の少なくとも1以上が記憶されていることを特徴とする請求項1又は2に記載の演算装置。
- 演算装置に、スイッチの入力処理を実行させるための入力処理プログラムであって、
前記演算装置に、
記憶部に記憶された複数種類の入力処理ロジックの1つを選択する選択部と、
前記選択部により選択された入力処理ロジックに従って前記スイッチの入力処理を実行する演算部と、して機能させるための入力処理プログラム。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017233477A JP6725482B2 (ja) | 2017-12-05 | 2017-12-05 | 演算装置 |
US16/209,464 US10983598B2 (en) | 2017-12-05 | 2018-12-04 | Arithmetic unit |
DE102018220924.3A DE102018220924A1 (de) | 2017-12-05 | 2018-12-04 | Arithmetikeinheit |
CN201811481392.2A CN109947009B (zh) | 2017-12-05 | 2018-12-05 | 运算装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017233477A JP6725482B2 (ja) | 2017-12-05 | 2017-12-05 | 演算装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019101863A true JP2019101863A (ja) | 2019-06-24 |
JP6725482B2 JP6725482B2 (ja) | 2020-07-22 |
Family
ID=66548438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017233477A Active JP6725482B2 (ja) | 2017-12-05 | 2017-12-05 | 演算装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10983598B2 (ja) |
JP (1) | JP6725482B2 (ja) |
CN (1) | CN109947009B (ja) |
DE (1) | DE102018220924A1 (ja) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02118701A (ja) * | 1988-10-27 | 1990-05-07 | Fanuc Ltd | Pcの入力信号制御方式 |
JP2004287475A (ja) * | 2003-01-27 | 2004-10-14 | Fujitsu Ten Ltd | 電子制御装置および電子駆動装置 |
US20040217649A1 (en) * | 2003-05-02 | 2004-11-04 | Rouleau James E. | Switch system capable of automatic configuration |
US20110037323A1 (en) * | 2009-08-11 | 2011-02-17 | Leviton Manufacturing Co., Inc. | Automatic switch configuration |
JP2012136950A (ja) * | 2010-12-24 | 2012-07-19 | Mitsubishi Motors Corp | 車両の制御装置 |
JP2015105056A (ja) * | 2013-12-02 | 2015-06-08 | 株式会社デンソー | 車両用制御装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4379973A (en) * | 1981-05-20 | 1983-04-12 | C & K Components, Inc. | Universal logic switch |
US5382791A (en) * | 1994-03-15 | 1995-01-17 | Leff; Ruth B. | Dual mode switch for handicapped |
CN100552622C (zh) * | 2005-03-31 | 2009-10-21 | 松下电器产业株式会社 | 运算处理装置 |
JP4453697B2 (ja) * | 2006-12-15 | 2010-04-21 | ソニー株式会社 | 演算処理装置、および演算処理制御方法、並びにコンピュータ・プログラム |
JP6417129B2 (ja) | 2014-07-02 | 2018-10-31 | 株式会社東芝 | インクジェットヘッドユニット、及びインクジェットヘッドの制御方法 |
US9860445B2 (en) * | 2015-06-15 | 2018-01-02 | Bendix Commercial Vehicle Systems Llc | Dual node composite image system architecture |
JP2017091123A (ja) * | 2015-11-09 | 2017-05-25 | アズビル株式会社 | 調節計 |
JP6383348B2 (ja) | 2015-12-22 | 2018-08-29 | 矢崎総業株式会社 | 制御装置および制御システム |
CN106448729B (zh) * | 2016-09-19 | 2019-09-27 | 华中科技大学 | 一种基于相变存储器实现双向数字运算的电路及方法 |
-
2017
- 2017-12-05 JP JP2017233477A patent/JP6725482B2/ja active Active
-
2018
- 2018-12-04 DE DE102018220924.3A patent/DE102018220924A1/de active Pending
- 2018-12-04 US US16/209,464 patent/US10983598B2/en active Active
- 2018-12-05 CN CN201811481392.2A patent/CN109947009B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02118701A (ja) * | 1988-10-27 | 1990-05-07 | Fanuc Ltd | Pcの入力信号制御方式 |
JP2004287475A (ja) * | 2003-01-27 | 2004-10-14 | Fujitsu Ten Ltd | 電子制御装置および電子駆動装置 |
US20040217649A1 (en) * | 2003-05-02 | 2004-11-04 | Rouleau James E. | Switch system capable of automatic configuration |
US20110037323A1 (en) * | 2009-08-11 | 2011-02-17 | Leviton Manufacturing Co., Inc. | Automatic switch configuration |
JP2012136950A (ja) * | 2010-12-24 | 2012-07-19 | Mitsubishi Motors Corp | 車両の制御装置 |
JP2015105056A (ja) * | 2013-12-02 | 2015-06-08 | 株式会社デンソー | 車両用制御装置 |
Non-Patent Citations (2)
Title |
---|
みついわゆきお: "GCC組み込みプログラミングpart5", SOFTWARE DESIGN, vol. 通巻217号(発刊151号), JPN6019046058, 18 May 2003 (2003-05-18), JP, pages 236 - 243, ISSN: 0004267730 * |
石澤太祥,中西泰人,小檜山賢二: "実空間コンテンツ・アプリケーション開発を支援する組み込みコンピューティング環境", 電子情報通信学会技術研究報告, vol. Vol.106,No.44,(MoMuC2006-1〜25), JPN6019046056, 11 May 2006 (2006-05-11), JP, pages 7 - 12, ISSN: 0004267729 * |
Also Published As
Publication number | Publication date |
---|---|
DE102018220924A1 (de) | 2019-06-06 |
CN109947009A (zh) | 2019-06-28 |
US10983598B2 (en) | 2021-04-20 |
CN109947009B (zh) | 2022-03-29 |
JP6725482B2 (ja) | 2020-07-22 |
US20190171614A1 (en) | 2019-06-06 |
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