JP2019085631A - Method for manufacturing electronic component, and electronic component - Google Patents

Abstract

To provide a method for manufacturing an electronic component, capable of suppressing the diffusion of nickel at high temperature in a bonding portion having a member bonded with solder, suppressing the occurrence of voids and maintaining excellent bonding reliability even in high temperature environment, and the electronic component.SOLUTION: A method for manufacturing an electronic component, capable of bonding a support 4 and a body 1 to be bonded having a metal layer, respectively, using a solder material including tin comprises: performing nickel plating or nickel-phosphorus plating on the metal layer 9 of the support 4 to form a first plating layer 5; performing nickel-copper-phosphorus plating on the first plating layer 5 to form a second plating layer 8; performing substitution gold plating on the second plating layer 8 to form a third plating layer 11; arranging a solder material 31 between the third plating layer 11 and the metal layer of the body 1 to be bonded; and melting a solder material 31 by heating and coagulating the solder material to form a bonding portion 34 having an alloy layer including (Cu,Ni)Snon the side of the first plating layer 5.SELECTED DRAWING: Figure 3

Description

  In the present invention, a nickel plating layer or a nickel-phosphorus plating layer is provided on a metal layer of a support, and a solder material is disposed between the nickel plating layer or the nickel-phosphorus plating layer and an adherend facing the support. The present invention relates to a method of manufacturing an electronic component for forming a solder joint portion and an electronic component.

A power module as an electronic component is a power semiconductor element used for power control in a power converter such as a converter or inverter, and drives a power device such as a MOSFET (MOS field effect transistor) or an IGBT (insulated gate bipolar transistor) It incorporates circuitry and self protection structure.
As the power converter, those provided in photovoltaic devices, power generators such as wind power generators, air conditioners, household appliances such as washing machines and refrigerators, and vehicles such as HV cars, electric cars, trains, etc. It can be mentioned.

  As a power module, the Cu wiring of the insulating substrate having a Cu wiring on one side and a metal layer formed on the lower surface of the power device by sputtering or the like are joined through a joint portion including a solder layer and housed in a case. After that, the case is filled with a sealing resin, and a cooler is disposed on the bottom of the case to dissipate heat from the power device.

The joint portion is formed, for example, as follows.
A Ni-P plating layer and an Au plating layer are sequentially formed on the surface of the Cu wiring of the insulating substrate using an electroless Ni-P plating solution and a substitution Au plating solution using hypophosphorous acid as a reducing agent. Then, a solder material is disposed between the metal layer of the power device and the Au plating layer, and reflow processing is performed, whereby the solder material is melted and an alloy layer is formed at the interface between the solder material and the Ni-P plating layer. Then, the solder material solidifies to form a joint.

Conventionally, the material of the power device is Si, but in recent years, a wide band gap semiconductor such as SiC or GaN having a band gap of 2.2 eV or more from the viewpoint that power loss is small and power density can be improved. It is considered to use a power device having
Since Si power devices can operate at 150 ° C. or higher and power devices with wide band gap semiconductor can operate at 200 ° C. or higher, the power module cooler can be made smaller and the entire power module can be made smaller. . And when a power module is used for a car, it can be connected to weight reduction of a car body.
Since the power device is operated at a high temperature, the temperature of the joint portion becomes 150 ° C. or more, Ni of the Ni—P plating layer diffuses to the solder layer side, and the alloy layer grows. As a result, a void is generated in the lower portion of the alloy layer, a crack is generated starting from the void, and the joint portion is easily peeled off from the portion where the crack is generated, and there is a problem that the joint reliability is lowered.

  In Patent Document 1, a power device is soldered to a lead frame formed by sequentially forming a Ni plating layer and an Au plating layer on the surface, and a first step of manufacturing an intermediate, a primer is applied to the surface of the intermediate Heat treatment in the first step of the power module manufacturing method including the second step of drying and forming the primer layer, and the third step of forming the sealing resin body on the surface of the primer layer and manufacturing the power module An invention is disclosed which is applied to form an Au plating layer in which Ni is diffused. In the present invention, it is intended to secure good wettability between the lead frame and the solder by the Au plating layer, and to improve the adhesion between the Au plating layer and the primer by diffusion of Ni.

JP, 2016-122719, A

  However, in the case of Patent Document 1, there is a possibility that the junction reliability may be reduced as described above by the diffusion of Ni.

  In electronic components other than power modules, a support having a metal layer and an adherend are often connected by a bonding portion formed using a solder material containing tin. The bonding portion is formed by arranging a solder material on the surface after subjecting the Cu wiring of the support to an OSP treatment or after forming a Ni-P plating layer and an Au plating layer on the Cu wiring. Electronic components are required to be further miniaturized and thinned, and higher junction reliability is required.

  The present invention has been made in view of such circumstances, and the diffusion of nickel at high temperature in the joint portion where the members are joined by the solder is suppressed, and the generation of the void is suppressed, which includes the high temperature environment and is favorable. Component and a method of manufacturing the same, and an electronic component capable of maintaining high joint reliability.

A method of manufacturing an electronic component according to the present invention is a method of manufacturing an electronic component in which a support having a metal layer and an adherend are each connected using a solder material containing tin, the metal being formed on the metal layer of the support. Nickel plating or nickel-phosphorus plating is performed to form a first plating layer, nickel-copper-phosphorus plating is performed on the first plating layer to form a second plating layer, and the second plating layer is formed on the second plating layer Substitution gold plating is performed to form a third plating layer, the solder material is disposed between the third plating layer and the metal layer of the adherend, the solder material is melted by heating, and then The method is characterized in that it is solidified to form a joint portion having an alloy layer containing (Cu, Ni) ₆ Sn ₅ on the first plating layer side.

  Here, the metal layer may be provided on the surface of the support or adherend, or the support or adherend may be made of metal and point to the metal surface . The same applies below.

As in the conventional case, when a gold plating layer is formed on a nickel-phosphorus plating layer and solder bonding is performed, a (Cu, Ni) ₆ Sn ₅ alloy layer is initially formed, and (Cu, Ni) ₆ Sn ₅ Along with the growth of the alloy layer, a (Ni, Cu) ₃ Sn ₄ alloy layer is formed below the alloy layer. In the (Ni, Cu) ₃ Sn ₄ alloy layer, nickel is likely to diffuse and grow, and a void is likely to occur to cause a crack.
In the present invention, after the second plating layer is provided on the first plating layer, the gold plating layer is formed, and the solder material is arranged to form the bonding portion, so copper is supplied from the second plating layer. The (Cu, Ni) ₆ Sn ₅ alloy layer is rapidly formed. Copper is supplied with time, and a predetermined amount of copper is contained in the bonding portion, so the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed, and the diffusion of nickel in the bonding portion under high temperature is suppressed. Since nickel does not diffuse, the formation of a P-rich layer is suppressed. Therefore, the formation of a void in the lower portion of the alloy layer and the occurrence of a crack are suppressed.
The presence of the gold plating layer prevents the oxidation of nickel and copper.
As described above, the bonding strength between the first plating layer and the solder layer does not decrease, and the electronic component can maintain good bonding reliability even when used under high temperature.

  The method of manufacturing an electronic component according to the present invention is characterized in that the content of copper in the second plating layer is 1% by mass or more and 98% by mass or less.

In the present invention, copper is favorably supplied from the second plating layer, the (Cu, Ni) ₆ Sn ₅ alloy layer is maintained, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed.

  In the method of manufacturing an electronic component according to the present invention, the nickel-copper-phosphorus plating includes a copper salt of an inorganic acid and a nickel salt of the inorganic acid selected from the group consisting of sulfuric acid, nitric acid, hydrochloric acid and acetic acid. -Conducting using a copper-phosphorus plating solution, adjusting the content of the copper salt and the nickel salt, pH, and bath temperature to control the content of copper in the second plating layer .

  In the present invention, copper is supplied favorably from the second plating layer, and the gold plating layer is oxidized by the diffusion of copper, thereby suppressing discoloration.

  The method of manufacturing an electronic component according to the present invention is characterized in that the content of phosphorus in the second plating layer is 0.1% by mass or more and 14% by mass or less.

  In the present invention, formation of a P-rich layer is suppressed.

  The method of manufacturing an electronic component according to the present invention is characterized in that the second plating layer is formed to have a thickness of 0.03 μm to 10 μm.

In the present invention, copper is continuously supplied even at high temperature to maintain the (Cu, Ni) ₆ Sn ₅ alloy layer, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed.

  The method of manufacturing an electronic component according to the present invention is characterized in that a nickel-phosphorus plating layer is formed by electroless nickel-phosphorus plating, and the nickel-copper-phosphorus plating is electroless nickel-copper-phosphorus plating. Do.

  In the present invention, since electroless nickel-copper-phosphorus plating is performed after electroless nickel-phosphorus plating, it is not necessary to supply electricity, and the workability is good. Since the pH of the electroless nickel-copper-phosphorus plating solution can be made neutral rather than the strong alkali side, peeling of the insulating film or the like of the electronic component device such as a power device can be suppressed.

  In the method of manufacturing an electronic component according to the present invention, the electronic component is a power module including one or two heat dissipating plates each having a metal layer, an insulating substrate or a metal plate, and a power device. The nickel plating or nickel-phosphorus plating is performed on a metal layer of a substrate or a metal plate and at least one member of the power device.

  In the present invention, the junction reliability of the power module used under high temperature is maintained for a long time.

An electronic component according to the present invention is an electronic component in which a support having a metal layer and an adherend are connected by a solder material containing tin, provided on the metal layer of the support, nickel plated Layer or nickel-phosphorus plating layer, nickel-copper-phosphorus plating layer provided on the nickel plating layer or nickel-phosphorus plating layer, provided on the nickel-copper-phosphorus plating layer (Cu, Ni And ₆ ) an alloy layer containing ₆ Sn ₅ and a solder layer containing tin, and a bonding portion bonding the metal layer of the adherend.

In the present invention, copper is supplied for a long time to maintain the (Cu, Ni) ₆ Sn ₅ alloy layer, suppress the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer, and suppress the generation of voids. . Therefore, good bonding reliability can be maintained, including when used at high temperatures.

  The electronic component according to the present invention is characterized in that the reduction rate of the thickness of the nickel plating layer or the nickel-phosphorus plating layer is 0% or more and 50% or less after being left at 200 ° C. for 50 hours.

Here, the reduction rate of thickness is the ratio of the amount of reduced thickness to the thickness of the initial nickel plating layer or nickel-phosphorus plating layer.
In the present invention, the diffusion of nickel is suppressed and the junction reliability is better.

According to the present invention, after the second plating layer is provided on the first plating layer, the gold plating layer is formed, and the solder material is disposed to form the joint portion. Therefore, copper is supplied from the second plating layer The (Cu, Ni) ₆ Sn ₅ alloy layer is rapidly formed. Copper is supplied with time, and a predetermined amount of copper is contained in the bonding portion, so the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed, and the diffusion of nickel in the bonding portion under high temperature is suppressed. Since nickel does not diffuse, the formation of a P-rich layer is suppressed. Therefore, the formation of a void in the lower portion of the alloy layer and the occurrence of a crack are suppressed.
Therefore, the bonding strength between the first plating layer and the solder layer does not decrease, and the electronic component can maintain good bonding reliability even when used under high temperature.

FIG. 1 is a schematic cross-sectional view showing a power module according to Embodiment 1. It is a schematic cross section which shows the bonded structure of an insulated substrate and a heat sink. It is a typical sectional view showing the junction structure of a power device and an insulating substrate. It is a flowchart in the case of performing a Ni-P plating process and an electroless Ni-Cu-P plating process, and forming a Ni-P plating layer and a Ni-Cu-P plating layer. FIG. 7 is a schematic cross-sectional view showing a power module according to a second embodiment. FIG. 10 is a schematic cross-sectional view showing a power module according to a third embodiment. FIG. 14 is a schematic cross-sectional view showing a power module according to a fourth embodiment. FIG. 18 is a schematic cross-sectional view showing before and after bonding of the electronic component according to the fifth embodiment. It is explanatory drawing for demonstrating the evaluation test method of joining reliability. It is a SEM photograph of the cross section of the junction part when the test board | substrate of Example 1 is left to stand at 200 degreeC for 50 hours. It is a SEM photograph of the cross section of the junction part when the test board | substrate of Example 2 is left to stand at 200 degreeC for 50 hours. It is a SEM photograph of the cross section of the junction part when the test board | substrate of the comparative example 1 is left to stand at 200 degreeC for 50 hours. It is a SEM photograph of the cross section of the junction part after reflow of the test substrate of the comparative example 2. FIG. It is a SEM photograph of the cross section of the junction part when the test board | substrate of the comparative example 3 is left to stand at 200 degreeC for 1000 hours. It is a SEM photograph of the cross section of the junction part when the test board | substrate of Comparative Example 4 is left to stand at 200 degreeC for 1000 hours. It is a SEM photograph of the cross section of the junction part when the test substrate of the comparative example 5 is left to stand at 200 degreeC for 1000 hours. It is a SEM photograph of the cross section of the junction part when the test board | substrate of the comparative example 1 is left to stand at 200 degreeC and 1000 hours. It is a graph which shows the relationship between the elapsed time at the time of leaving it to stand at 200 degreeC, and the reduction amount of the thickness of a Ni-P plating layer about the test substrate of Comparative Example 1, Comparative Example 4, and Comparative Example 5.

Hereinafter, the present invention will be specifically described based on the drawings showing the embodiments thereof.
Embodiment 1
FIG. 1 is a schematic sectional view showing a power module 20 according to the first embodiment, FIG. 2 is a schematic sectional view showing a bonding structure of an insulating substrate 4 and a heat sink 6, and FIG. 3 is a power device 1 and an insulating substrate 4 It is a typical sectional view showing the junction structure with.
The power module 20 includes power devices 1 and 1, an insulating substrate 4, a heat sink 6, a cooler 7, a case 10, terminals 12 and 12, wires 13 and 14, a resin layer 15, and an insulating substrate 19.

The heat sink 6 is made of copper. The insulating substrate 4 is made of, for example, ceramic, and a Cu pad 9 (see FIG. 2) is provided on the lower surface of the insulating substrate 4. The heat sink 6 and the lower Cu pad 9 in FIG. 2 of the insulating substrate 4 are soldered together. As shown in FIG. 2B, the Ni-P plating layer (or Ni plating layer) 5 is provided on the upper surface of the heat sink 6 and the lower surface of the Cu pad 9 below the insulating substrate 4. , 5 are provided with a joint 3. As shown in FIG. 2, the connection metal portion 2 is configured by the Cu pad 9 and the Ni—P plating layer 5.
In addition, in FIG. 1, the Ni-P plating layer 5 is continuously provided on the heat sink 6, and the state which the junction part 3 and the connection metal part 2 were provided on the Ni-P plating layer 5 is shown. However, the three-layered laminated structure of the Ni—P plating layer 5, the bonding portion 3, and the connection metal portion 2 may be intermittently provided on the heat dissipation plate 6.

The power device 1 is, for example, a semiconductor element such as a SiC system or a GaN system that performs conversion and control of electric power, conversion (rectification) of an AC power supply to a DC power supply, and the like.
As shown in FIG. 3, a Ni—P plating layer 5 is provided on the Cu pad 9 of the insulating substrate 4, and the Ni—P plating layer 5 and Ti, Ni, Au, etc. formed by sputtering of the power device 1. A junction 3 is provided between the metal wiring layer and the metal wiring layer.

As shown in FIG. 1, the cooler 7 is attached to the heat sink 6 via the insulating substrate 19.
The case 10 is in the form of a box having an opening in the bottom plate. The heat sink 6 is fitted to the bottom plate in a state where the cooler 7 protrudes from the opening, and the power device 1, the insulating substrate 4, and the heat sink 6 are accommodated in the case 10.
At the central portion in the height direction of the case 10, a step which protrudes inward is provided, and terminals 12, 12 are provided at the step.
The two electrodes on the power device 1 are connected to the terminals 12 and 12 by wires 13 and 14 made of aluminum.
Then, the inside of the case 10 is filled with an insulating resin, and a resin layer 15 is formed.

Hereinafter, bonding of the insulating substrate 4 and the heat sink 6 will be described.
As shown in FIG. 2A, first, Ni-P plating layers 5 and 5 are provided on the surface of the heat sink 6 and the Cu pad 9 under the insulating substrate 4, and Ni on the surfaces of the Ni-P plating layers 5 and 5. -Providing Cu-P plating layers 8 and 8;

Formation of the Ni-P plating layer 5 and the Ni-Cu-P plating layer 8 is performed as follows.
FIG. 4 is a flowchart in the case of forming the Ni-P plating layer 5 and the Ni-Cu-P plating layer 8 by applying the electroless Ni-P plating treatment and the electroless Ni-Cu-P plating treatment.
An acid degreasing agent is used for each of the heat sink 6 and the insulating substrate 4, and degreasing is performed at 50 ° C. for 5 minutes (S1).
A soft etching process is performed using 100 g / L of sodium persulfate and 10 ml / L of sulfuric acid (S2). The retention time is 1 minute.
An acid treatment is performed using 50 g / L of sulfuric acid (S3). The retention time is 0.5 minutes.
Pre-dip treatment is performed using 28.7 g / L of sulfuric acid (S4). The retention time is 0.5 minutes.
The activator treatment solution is used to activate (S5). The retention time is 1 minute. The activator process is a process of applying Pd as a catalyst so that the reducing agent in the reduction deposition-type electroless Ni-P plating solution releases electrons only on the heat sink 6 and the Cu pad 9.
A post-dip treatment is performed to remove the catalyst residue after the activator treatment with the catalyst residue removal solution (S6). The holding time is 2 minutes.
Thereafter, electroless Ni-P plating treatment is performed using an electroless Ni-P plating solution containing hypophosphorous acid as a reducing agent, and the Ni-P plating layer 5 is used as the heat sink 6 and the Cu pad 9 of the insulating substrate 4. It forms on the surface (S7). The target thickness is 5 μm as an example, and is not limited to this thickness.

Next, electroless Ni-Cu-P plating treatment is performed under the following electroless Ni-Cu-P plating solution composition and plating conditions to form Ni-Cu-P plating layer 8 on Ni-P plating layer 5 (S8).
<Electroless Ni-Cu-P plating solution composition>
Copper sulfate pentahydrate: 0.00004-0.15 mol / L
Nickel sulfate hexahydrate: 0.000038-0.15 mol / L
Sodium hypophosphite: 0.095 to 0.47 mol / L
Trisodium citrate dihydrate: 0.034-0.2 mol / L
Borax: 0.013-0.078 mol / L
Surfactant: Appropriate amount <Ni-Cu-P plating conditions>
Bath temperature: 65-95 ° C
pH: 4-10

  Then, a substitution Au plating process is performed to form an Au plating layer 11 on the Ni-Cu-P plating layer 8 (S9). The target thickness is 0.03 μm.

  A solder material 31 is disposed between the Au plating layers 11 and 11 (FIG. 2A). As the solder material 31, for example, Sn-0.7Cu solder sheet, Sn-3.0Ag-0.5Cu solder sheet, etc. may be mentioned.

Then, reflow processing is performed.
As a reflow apparatus, a stationary reflow apparatus (manufactured by Malcom: "RDT 250C") was used. The reflow atmosphere is the atmosphere.
As an example, the temperature is raised to 150 ° C. at a temperature rising rate of 3.0 ° C./sec, then to 120 ° C. over 120 seconds, and raised to 250 ° C. at a temperature rising rate of 1.5 ° C./sec, There is a case of holding for 10 seconds.

By performing the reflow process, the solder material 31 is melted, and as shown in FIG. 2B, the alloy layer 32 mainly containing (Cu, Ni) ₆ Sn ₅ between the solder material 31 and the Ni—P plating layer 5. The solder material 31 solidifies in a state in which is formed, and the joint portion 3 having the alloy layer 32, the remaining Ni-Cu-P plated layer 8, and the solder layer 33 is formed. A joint portion 34 according to claim 1 of the present application is formed by one alloy layer 32 and the solder layer 33.

In step S8 described above, it is preferable to form the Ni-Cu-P plating layer 8 so that the content of Cu in the Ni-Cu-P plating layer 8 is 1% by mass or more and 98% by mass or less. In this case, copper is satisfactorily supplied from the Ni-Cu-P plating layer 8 and a (Cu, Ni) ₆ Sn ₅ alloy layer is formed and maintained. The upper limit value of the content of Cu is more preferably 95% by mass, and still more preferably 90% by mass. The lower limit value of the content of Cu is more preferably 10% by mass, and further preferably 20% by mass.
The electroless Ni-Cu-P plating solution is not limited to the above-mentioned composition, and may contain a copper salt of an inorganic acid and a nickel salt of the inorganic acid selected from the group consisting of sulfuric acid, nitric acid, hydrochloric acid and acetic acid. The contents of copper and nickel salts, the pH, and the bath temperature are adjusted to control the content of Cu in the Ni-Cu-P plating layer 8.

  It is preferable to form the Ni-Cu-P plating layer 8 so that the content of P in the Ni-Cu-P plating layer 8 becomes 0.1 mass% or more and 14 mass% or less. In this case, formation of the P-rich layer is suppressed. The upper limit of the content of P is more preferably 13% by mass. The lower limit value of the content of P is more preferably 0.2% by mass.

Moreover, it is preferable to form Ni-Cu-P plating layer 8 so that thickness may be set to 0.03 micrometer or more and 10 micrometers or less. In this case, even under high temperature, copper is continuously supplied to maintain the (Cu, Ni) ₆ Sn ₅ alloy layer, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed. The upper limit of the thickness of the Ni-Cu-P plating layer 8 is more preferably 5 μm. The lower limit of the thickness is more preferably 0.1 μm.

The content of Cu in the Ni-Cu-P plating layer 8 and the thickness of the Ni-Cu-P plating layer 8 are Ni plating layers after left to stand at 200 ° C. for 50 hours in a bonding reliability evaluation test described later. It is preferable to set so that the reduction rate of the thickness of 5 or Ni-P plating layer 5 may be 0% or more and 50% or less. In this case, Cu is supplied for a long time, the (Cu, Ni) ₆ Sn ₅ alloy layer is maintained, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed. The upper limit value of the reduction rate is more preferably 40%, further preferably 30%.

In the case of the present embodiment, the (Cu, Ni) ₆ Sn ₅ alloy layer is initially formed, but the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed. Accordingly, generation of a void and generation of a crack is suppressed, and the bonding reliability between the insulating substrate 4 and the heat sink 6 is good.

Hereinafter, bonding of the power device 1 and the insulating substrate 4 will be described.
As shown in FIG. 3A, the Ni-P plating layer 5 is provided on the Cu pad 9 of the insulating substrate 4 in the same manner as described above before the solder reflow treatment, and the Ni-Cu-P plating layer is formed on the Ni-P plating layer 5. 8 is provided, and the Au plating layer 11 is provided on the Ni-Cu-P plating layer 8. By arranging the solder material 31 between the Au plating layer 11 and the metal wiring layer of the power device 1 and performing the reflow process, as shown in FIG. 3B, the solder material 31 melts, and the solder material 31 and Ni The solder material 31 is solidified in a state in which the alloy layer 32 mainly containing (Cu, Ni) ₆ Sn ₅ is formed between it and the P plating layer 5, and the alloy layer 32 remains, and the remaining Ni—Cu—P plating A joint 3 having a layer 8 and a solder layer 33 is formed. The bonding portion 3 differs from the bonding portion 3 provided between the insulating substrate 4 and the heat dissipation plate 6 described above, and the alloy layer 32 is provided only at one interface.

The Ni-P plating layer 5 and the Ni-Cu-P plating layer 8 are not limited in the case where they are formed by the above-described electroless Ni-P plating treatment and electroless Ni-Cu-P plating treatment. When forming a Ni plating layer, it forms by electrolytic Ni plating process.
In the case where the Ni-P plating layer 5 is formed by electroless Ni-P plating and the Ni-Cu-P plating layer 8 is formed by electroless Ni-Cu-P plating, there is no need to supply a current, and it is smoothly and continuously It can be processed. In addition, when using an electroless Ni-Cu-P plating solution, the pH of the plating solution can be made neutral rather than the strong alkali side as compared to the case of using an electroless Cu plating solution. Peeling off of the insulating film or the like of the device of the electronic component is suppressed.

As described above, in the present embodiment, after Ni-Cu-P plating layer 8 is provided on Ni-P plating layer 5 (or Ni plating layer 5), Au plating is performed to form joint 3. Therefore, the diffusion of Ni in the joint 3 under high temperature is suppressed, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed.
Therefore, the formation of a void in the lower part of the alloy layer 32 and the generation of a crack can be suppressed, and the power module 20 can maintain a good bonding reliability when used under high temperature.

An OSP process may be performed on the surface of the Ni-Cu-P plated layer 8 formed as described above. A commonly used preflux solution can be used as the OSP treatment solution. For example, "Tough Ace F2 (LX)" manufactured by Shikoku Kasei Kogyo Co., Ltd. can be used.
In the case where the surface treatment is not performed on the Ni-Cu-P plating layer 8, the surface may be oxidized when stored for a long period of time, and a wetting failure of the solder material 31 may occur. The wettability is better if the Au plating process is performed than the OSP process.

Second Embodiment
FIG. 5 is a schematic cross-sectional view showing a power module 21 according to a second embodiment. In the figure, the same parts as those in FIG.
Unlike the power module 20, the power module 21 has a double-sided heat radiation structure.
The power module 21 includes the power device 1, the heat radiation plates 6 and 6, the coolers 7 and 7, the metal plate 16, the terminals 12, the wires 13, and the resin layer 15.
A Ni-P plating layer 5 is provided on a predetermined portion of the surface of the lower heat sink 6 in FIG. 5 in the same manner as described above, and a metal wiring layer formed by sputtering or the like on the back surface of the power device 1. Is provided. The metal wiring layer and the Ni—P plated layer 5 of the heat sink 6 are joined by the joint portion 3.
Before the reflow process, a Ni-Cu-P plating layer and an Au plating layer are provided on the Ni-P plating layer 5 as in FIG. 3A. After arranging the solder material between the Au plating layer and the metal wiring layer, the solder material is melted by performing the reflow process, and between the solder material and the Ni-P plating layer 5 (Cu, Ni) _The solder material solidifies in a state where the alloy layer mainly containing ₆ Sn ₅ is formed, and the joint portion 3 having the alloy layer, the remaining Ni-Cu-P plating layer, and the solder layer is formed.

The connection metal portion 2 is provided on the surface of the power device 1 by laminating the Ni-P plating layer on the metal wiring layer, and similarly, the Ni-P plating layer 5 is formed on both surfaces of the metal plate 16 made of Cu. Is provided. The connection metal portion 2 of the power device 1 and the Ni—P plated layer 5 on the back surface of the metal plate 16 are bonded by a bonding portion 3. Before the reflow process, as in FIG. 2A, the Ni—P plated layer of the connection metal portion 2 and the Ni—P plated layer 5 are respectively provided with a Ni—Cu—P plated layer and an Au plated layer.
As in FIG. 2A, after the solder material is disposed between the Au-plated layers, the solder material is melted by performing the reflow process, and (Cu, Ni) ₆ between the solder material and each Ni-P plated layer The solder material solidifies in a state where the alloy layer mainly containing Sn ₅ is formed, and the joint portion 3 having the alloy layer, the remaining Ni—Cu—P plated layer, and the solder layer is formed.

The Ni-P plating layer 5 is provided on a predetermined portion of the back surface of the upper heat radiation plate 6 in FIG. 5, and the Ni-P plating layer 5 is joined to the Ni-P plating layer 5 on the surface of the metal plate 16. It is joined by three.
Before the reflow process, as in FIG. 2A, the Ni—P—P plating layer and the Au plating layer are provided on the respective Ni—P plating layers 5.
After arranging the solder material between the Au-plated layers, the solder material is melted by reflow treatment, and (Cu, Ni) ₆ Sn ₅ is mainly formed between the solder material and each Ni-P plated layer 5 The solder material solidifies in a state in which the alloy layer containing the alloy layer is formed, and the joint portion 3 having the alloy layer, the remaining Ni—Cu—P plated layer, and the solder layer is formed.

The heat sinks 6 and 6 are disposed to face each other, and the coolers 7 and 7 are attached to the opposite surfaces of the heat sinks 6 and 6 via the insulating substrates 19 and 19, respectively.
A resin layer 15 filled with an insulating resin is provided between the coolers 7 and 7.
A terminal 12 is inserted in the central portion in the height direction of the resin layer 15 and is connected to the electrode of the power device 1 by a wire 13. In the portion of the resin layer 15 opposite to the portion in which the terminal 12 is inserted, the end portions of the heat sinks 6, 6 are separately pulled out to the outside.

In the present embodiment, after the Ni-Cu-P plating layer 8 is provided on the Ni-P plating layer 5 (or the Ni plating layer 5), Au plating is performed to form the bonding portion 3. The diffusion of Ni in the joint portion 3 is suppressed, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed.
Therefore, the formation of a void in the lower part of the alloy layer 32 and the generation of a crack can be suppressed, and the power module 21 can maintain good bonding reliability when used under high temperature.

Third Embodiment
FIG. 6 is a schematic cross-sectional view showing a power module 22 according to a third embodiment. In the figure, the same parts as in FIG. 1 and FIG. 5 are assigned the same reference numerals and detailed explanations thereof will be omitted.
Similar to the power module 21, the power module 22 has a double-sided heat radiation structure.
The power module 22 includes the power device 1, the insulating substrates 4 and 4, the heat sinks 6 and 6, the coolers 7 and 7, the terminals 12 and 12, and a resin layer 15.
The Ni-P plating layer 5 and the Au plating layer are provided on a predetermined portion of the surface of the lower heat radiation plate 6 in FIG. 6 in the same manner as described above. The connection metal portion 2 described above is provided on both sides of the lower insulating substrate 4. A bonding portion 3 is provided between the Ni—P plating layer 5 and the Ni—P plating layer of the connection metal portion 2 on the back surface of the insulating substrate 4.
Before the reflow process, a Ni-Cu-P plated layer and an Au plated layer are provided on the Ni-P plated layer in the same manner as described above. As in FIG. 2A, after the solder material is disposed between the Au-plated layers, the solder material is melted by performing the reflow process, and (Cu, Ni) ₆ between the solder material and each Ni-P plated layer The solder material solidifies in a state where the alloy layer mainly containing Sn ₅ is formed, and the joint portion 3 having the alloy layer, the remaining Ni—Cu—P plated layer, and the solder layer is formed.

The connection metal portion 2 on the surface of the insulating substrate 4 and the metal wiring layer formed by sputtering or the like on the lower side of the power device 1 are bonded by a bonding portion 3.
On the surface of the power device 1, a Ni-P plating layer is stacked on the metal wiring layer to provide the connection metal portion 2, and on both sides of the upper insulating substrate 4, a Ni-P plating layer is formed on the Cu layer. It is laminated and the connection metal part 2 is provided.
The connection metal portion 2 on the back surface of the upper insulating substrate 4 and the connection metal portion 2 of the power device 1 are bonded by a bonding portion 3.
In any case, the Ni—P—P plating layer and the Au plating layer are provided on the Ni—P plating layer of the connection metal portion 2 before the reflow process. After arranging the solder material between the Au-plated layers, the solder material is melted by reflow treatment, and an alloy layer mainly containing (Cu, Ni) ₆ Sn ₅ between the solder material and the Ni-P plated layer The solder material solidifies in the state in which is formed, and the joint portion 3 having the alloy layer, the remaining Ni—Cu—P plated layer, and the solder layer is formed.

A Ni-P plating layer 5 is provided on a predetermined portion of the back surface of the upper heat sink 6. The Ni—P plating layer 5 and the connection metal portion 2 on the surface of the upper insulating substrate 4 are bonded by a bonding portion 3. Before the reflow process, a Ni-Cu-P plating layer and an Au plating layer are provided on the Ni-P plating layer 5 and the Ni-P plating layer of the connection metal portion 2. After the solder material is disposed between the Au-plated layers, the solder material is melted by reflow treatment, and an alloy layer mainly containing (Cu, Ni) ₆ Sn ₅ at the interface between the solder material and the Ni-P plated layer. The solder material solidifies in the state in which is formed, and the joint portion 3 having the alloy layer, the remaining Ni—Cu—P plated layer, and the solder layer is formed.

The coolers 7 and 7 are attached to the surface on the opposite side of the opposing surface of the heat sinks 6 and 6 via the insulating substrates 19 and 19, respectively.
A resin layer 15 filled with an insulating resin is provided between the coolers 7 and 7.
Terminals 12 and 12 are inserted in central portions in the height direction on both side surfaces of the resin layer 15. The terminal 12 on the left side in FIG. 6 is connected to the connecting metal portion 2 of the upper insulating substrate 4 via the bonding portion 3, and the terminal 12 on the right side is connected to the connecting metal portion 2 on the lower insulating substrate 4 It is connected via part 3.

In the present embodiment, after the Ni-Cu-P plating layer 8 is provided on the Ni-P plating layer 5 (or the Ni plating layer 5), Au plating is performed to form the bonding portion 3. The diffusion of Ni in the joint portion 3 is suppressed, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed.
Therefore, the formation of a void in the lower part of the alloy layer and the occurrence of a crack can be suppressed, and the power module 22 can maintain good bonding reliability when used under high temperature.
Since the power module 22 according to the present embodiment does not have a wire, parasitic capacitance can be reduced.

Embodiment 4
FIG. 7 is a schematic cross-sectional view showing a power module 37 according to a fourth embodiment. In the figure, the same parts as in FIG. 1 and FIG. 5 are assigned the same reference numerals and detailed explanations thereof will be omitted.
Similar to the power module 21, the power module 37 has a double-sided heat dissipation structure.
The power module 37 includes a power device 1 such as an IGBT / diode, a heat sink 6, a Cu terminal 40, a resin layer 15, and a case 10.
The power module 37 has a 2 in 1 structure in which the upper arm circuit on the positive electrode side and the lower arm circuit on the negative electrode side are packaged.
The Ni-P plating layer 5 is provided on a predetermined portion of the lower surface of the heat sink 6 on the lower side of the lower arm circuit in the same manner as described above, and the metal formed on the back surface of the power device 1 by sputtering or the like. A wiring layer is provided. The metal wiring layer and the Ni—P plated layer 5 of the heat sink 6 are joined by the joint portion 3.
Before the reflow process, a Ni-Cu-P plating layer and an Au plating layer are provided on the Ni-P plating layer 5 as in FIG. 3A. After arranging the solder material between the Au plating layer and the metal wiring layer, the solder material is melted by performing the reflow process, and the interface between the solder material and the Ni-P plating layer 5 is (Cu, Ni) _The solder material solidifies in a state where the alloy layer mainly containing ₆ Sn ₅ is formed, and the joint portion 3 having the alloy layer, the remaining Ni-Cu-P plating layer, and the solder layer is formed.

The connection metal portion 2 is provided on the surface of the power device 1 by laminating a Ni—P plating layer on the metal wiring layer, and the Ni plating layer 5 is provided on both surfaces of the Cu terminal 40. The Ni—P plated layer of the connection metal portion 2 of the power device 1 and the Ni plated layer 5 on the back surface of the Cu terminal 40 are joined by the joining portion 3.
Before the reflow process, as in FIG. 2A, the Ni—P plated layer of the connection metal portion 2 and the Ni plated layer 5 are respectively provided with a Ni—Cu—P plated layer and an Au plated layer.
As in FIG. 2A, after the solder material is disposed between the Au-plated layers, the solder material is melted by performing the reflow process, and the solder material and the Ni-P plated layer or the Ni plated layer (Cu, The solder material solidifies in the state where the alloy layer mainly containing Ni) ₆ Sn ₅ is formed, and the joint portion 3 having the alloy layer, the remaining Ni—Cu—P plating layer, and the solder layer is formed.

The Ni-P plating layer 5 is provided on a predetermined portion of the back surface of the upper heat radiation plate 6 in FIG. 7, and the Ni-P plating layer 5 is bonded to the Ni plating layer 5 on the surface of the Cu terminal 40. It is joined.
Before the reflow process, as in FIG. 2A, the Ni—P plated layer 5 and the Ni plated layer 5 are respectively provided with a Ni—Cu—P plated layer and an Au plated layer.
After the solder material is disposed between the Au-plated layers, the solder material is melted by reflow treatment, and (Cu, Ni) ₆ Sn is formed between the solder material and the Ni-P plated layer 5 or the Ni plated layer 5 _The solder material solidifies in the state where the alloy layer mainly containing ₅ is formed, and the joint portion 3 having the alloy layer, the remaining Ni-Cu-P plating layer, and the solder layer is formed.
The heat sinks 6 and 6 are disposed to face each other.
In the case 10, a resin layer 15 filled with an insulating resin is provided.

The upper arm circuit also has the same configuration as the lower arm circuit.
As shown in FIG. 7, a lower arm 61 extending obliquely upward is provided at an end of the lower arm circuit on the upper arm circuit side of the lower side of the lower arm circuit, and a tip end of the lower arm 61 has a horizontal direction The connection 62 extends to the
A connecting portion 63 extending in the horizontal direction is provided at an end of the upper arm circuit on the lower arm circuit side of the heat dissipation plate 6 on the upper side.

The Ni—P plating layer 5 is provided on the surface of the connection portion 62 and the back surface of the connection portion 63, respectively.
Before the reflow process, as in FIG. 2A, each Ni-P plating layer is provided with a Ni-Cu-P plating layer and an Au plating layer.
As in FIG. 2A, after the solder material is disposed between the Au-plated layers, the solder material is melted by performing the reflow process, and the interface between the solder material and the Ni-P plated layer or the Ni plated layer (Cu, The solder material solidifies in the state where the alloy layer mainly containing Ni) ₆ Sn ₅ is formed, and the joint portion 3 having the alloy layer, the remaining Ni—Cu—P plating layer, and the solder layer is formed.

In the present embodiment, after the Ni-Cu-P plating layer 8 is provided on the Ni-P plating layer 5 (or the Ni plating layer 5), Au plating is performed to form the bonding portion 3. The diffusion of Ni in the joint portion 3 is suppressed, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed.
Therefore, the formation of a void in the lower part of the alloy layer 32 and the generation of a crack can be suppressed, and the power module 37 can maintain good bonding reliability when used under high temperature.

Fifth Embodiment
FIGS. 8A and 8B are schematic cross-sectional views showing before and after bonding of the electronic component 23 according to the fifth embodiment.
Cu wirings 26 and 26 are formed on the surface of the substrate 24 of the electronic component 23.
The Ni—P plating layer 5 (or the Ni plating layer 5) is formed on the surface and the side surface of the Cu wiring 26 in the same manner as described above.
The Ni-Cu-P plating layer 8 is formed on the surface of the Ni-P plating layer 5 in the same manner as described above.
An Au plating layer 11 is formed on the surface of the Ni-Cu-P plating layer 8 in the same manner as described above.
The chip component 25 is mounted on the substrate 24 by connecting the electrodes 251 and 251 made of, for example, Sn alloy or the like provided at both ends of the chip component 25 to the Cu wires 26 and 26 by solder bonding.

When manufacturing the electronic component 23, as shown in A, the electrodes 251 and 251 of the chip component 25 are disposed above the Cu wires 26 and 26 of the substrate 24, and the electrodes 251 and 251 and the Au plating layers 11 and 11 are provided. Place the solder material between
By performing the reflow process, the solder material is melted, and as shown in B, an alloy layer mainly containing (Cu, Ni) ₆ Sn ₅ at the interface between the solder material and the Ni—P plating layer or Ni plating layer The solder material solidifies in a state in which 32 is formed, and a joint 3 having the alloy layer 32, the remaining Ni-Cu-P plated layer 8, and the solder layer 33 is formed.

In the present embodiment, similarly to the first to fourth embodiments, after the Ni-Cu-P plating layer 8 is provided on the Ni-P plating layer 5 (or the Ni plating layer 5), Au plating is performed, Since the bonding portion 3 is formed, the diffusion of Ni in the bonding portion 3 at high temperature is suppressed, and the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed. That is, formation of a void in the lower portion of the alloy layer 32 and generation of a crack are suppressed, and the electronic component 23 can maintain good bonding reliability including use under high temperature.
The electronic component 23 can be miniaturized and thinned, and can maintain good bonding reliability, including the case where the bonding portion 3 is easily affected by the heat generation of the chip component 25.

Examples of the present invention will be specifically described below, but the present invention is not limited to these examples.
[Evaluation test of joint reliability]
FIG. 9 is an explanatory view for explaining an evaluation test method of bonding reliability. 9A is a schematic cross-sectional view of the test substrate 43, FIG. 9B is an enlarged cross-sectional view of a portion where the dummy chip 41 is not mounted, and FIG. 9C is an enlarged cross-sectional view of a portion where the dummy chip 41 is mounted.
The test substrate 43 is formed by bonding the dummy chip 41 to the Cu plate 42 by the solder layer 33.
The dummy chip 41 is made of SiC, and a metal layer such as Ti, Ni, Au or the like is provided by sputtering so as to be solderable.
In FIG. 9B, a Ni-P plating layer 5 formed by electroless Ni-P plating and a Ni-Cu-P plating layer 8 formed by electroless Ni-Cu-P plating on a Cu plate 42 in this order. And an Au plating layer 11 formed by substitution Au plating.

As shown in FIG. 9C, the alloy layer 32 and the solder layer 33 are formed by the reflow process. By being left at high temperature, as described above, Ni diffuses from the Ni-P plating layer. As shown in FIG. 9B and FIG. 9C, the thickness of the Ni-P plating layer 5 is reduced, a P-rich layer 35 is generated, a void is generated, and a crack is easily generated.
The present inventors considered that it is possible to determine the bonding reliability by leaving the test substrate 43 at high temperature and determining the reduction rate of the thickness of the Ni-P plating layer 5 with time by SEM photograph.

Example 1
An oxygen free copper plate was used as the Cu plate 42, and SiC was used as the dummy chip 41.
The Ni-P plating layer 5 and the Ni-Cu-P plating layer 8 were formed on the Cu plate 42 in accordance with the flow charts of the electroless Ni-P plating process and the electroless Ni-Cu-P plating process of FIG. The target thickness of the Ni-P plating layer 5 is 5 μm. The target thickness of the Ni-Cu-P plating layer 8 is 2 μm, and the target content of Cu is 50% by mass. The composition of the electroless Ni-Cu-P plating solution is as follows.
<Electroless Ni-Cu-P plating solution composition>
Copper sulfate pentahydrate: 0.00004-0.15 mol / L
Nickel sulfate hexahydrate: 0.000038-0.15 mol / L
Sodium hypophosphite: 0.3 mol / L
Trisodium citrate dihydrate: 0.2 mol / L
Borax: 0.05 mol / L
Surfactant: Appropriate amount <Ni-Cu-P plating conditions>
Bath temperature: 65-95 ° C
pH: 4-10

The Au plating layer 11 was formed on the Ni-Cu-P plating layer 8 according to the flowchart of FIG.
A solder sheet made of Sn-0.7Cu was placed on the Au plating layer 11, and reflow processing was performed under the above-mentioned conditions, to obtain a test substrate 43 of Example 1.

Example 2
A test substrate 43 of Example 2 was produced in the same manner as Example 1, except that the target thickness of the Ni-Cu-P plated layer 8 was 2.8 μm.

Comparative Example 1
The Cu plate 42 was subjected to the degreasing, soft etching, acid treatment, pre-dip, activator, post-dip treatment, and electroless Ni-P plating treatment in the flowchart of FIG. 4. And substitution Au plating processing was implemented and Au plating layer was formed on Ni-P plating layer. The target thickness of the Ni-P plating layer is 5 μm, and the target thickness of the Au plating layer is 0.03 μm.
The said solder sheet was mounted on Au plating layer, reflow was performed on the above-mentioned conditions, and the test substrate of the comparative example 1 was obtained.

Comparative Example 2
A test substrate of Comparative Example 2 is obtained in the same manner as in Example 1 except that a Cu plating layer is formed by electrolytic Cu plating instead of the Ni-Cu-P plating layer 8 on the Ni-P plating layer. The The target thickness of the Cu plating layer is 0.5 μm.
Comparative Example 3
A test substrate of Comparative Example 3 was obtained in the same manner as Comparative Example 2 except that the target thickness of the Cu plating layer was 0.1 μm.
Comparative Example 4
A test substrate of Comparative Example 4 was obtained in the same manner as Comparative Example 2 except that the target thickness of the Cu plating layer was 1 μm.
Comparative Example 5
The test substrate of Comparative Example 5 was obtained in the same manner as Comparative Example 2 except that the target thickness of the Cu plating layer was 2 μm.

FIG. 10 is a SEM photograph of the cross section of the bonding portion when the test substrate of Example 1 is left at 200 ° C. for 50 hours, and FIG. 11 is the bonding portion when the test substrate of Example 2 is left at 200 ° C. for 50 hours It is a SEM photograph of the cross section of.
FIG. 12 is an SEM photograph of a cross section of a bonded part when the test substrate of Comparative Example 1 is left at 200 ° C. for 50 hours.
In the case of Comparative Example 1, it is understood that Ni diffuses from the Ni-P plating layer, a (Ni, Cu) ₃ Sn ₄ alloy layer is formed, and a void is generated in the P-rich layer. Therefore, cracks are likely to occur.
In the case of Examples 1 and 2, Cu is supplied to the solder from the Ni-Cu-P plating layer to form and maintain the (Cu, Ni) ₆ Sn ₅ alloy layer, and Ni is diffused from the Ni-P plating layer Since it does not form and a P-rich layer is not formed, it turns out that the void has not arisen under the alloy layer. In the case of Example 2, the remaining amount of the Ni-Cu-P plating layer is larger than the above-mentioned remaining amount of Example 1.

FIG. 13 is an SEM photograph of a cross section of a joint after reflow of the test substrate in Comparative Example 2.
As shown in FIG. 13, when the thickness of the Cu plating layer is 0.5 μm, the Cu plating layer completely disappears after reflow, and Cu is supplied to the solder (Cu, Ni) ₆ Sn ₅ alloy It can be seen that a layer is formed.

  FIG. 14 is a SEM photograph of the cross section of the bonding portion when the test substrate of Comparative Example 3 is left at 200 ° C. for 1000 hours, and FIG. 15 is the cross section of the bonding portion when the test substrate of Comparative Example 4 is left at 200 ° C. for 1000 hours 16 is a SEM photograph of the cross section of the bonding portion when the test substrate of Comparative Example 5 is left at 200 ° C. for 1000 hours, and FIG. 17 is when the test substrate of Comparative Example 1 is left at 200 ° C. for 1000 hours It is a SEM photograph of the cross section of a junction part.

From FIG. 17, in the case of Comparative Example 1, it is understood that Ni diffuses to reduce the thickness of the Ni-P plating layer, a (Ni, Cu) ₃ Sn ₄ alloy layer is formed, and a P-rich layer is generated. . Voids are generated in the P-rich layer below the (Ni, Cu) ₃ Sn ₄ alloy layer, and the bonding reliability is poor.
From FIG. 14 to FIG. 16, as the thickness of the Cu plating layer increases, Cu is supplied from the Cu plating layer, the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer is suppressed, and (Cu, Ni) ₆ Sn It can be seen that ₅ alloy layers are maintained. In the case of Comparative Example 5 having a Cu plating layer with a thickness of 2 μm, the (Ni, Cu) ₃ Sn ₄ alloy layer did not occur after 1000 hours. Then, the diffusion of Ni from the Ni-P plating layer is suppressed, the generation of the P-rich layer is suppressed, and the generation of the void is also suppressed.

FIG. 18 is a graph showing the relationship between the elapsed time and the amount of decrease in the thickness of the Ni-P plating layer when left at 200 ° C. for the test substrates of Comparative Example 1, Comparative Example 4 and Comparative Example 5 is there. The horizontal axis in FIG. 18 is the elapsed time (h), and the vertical axis is the reduction in thickness (μm).
According to FIG. 18, in the case of Comparative Example 1 having no Cu plating layer, the thickness of the Ni—P plating layer decreases greatly in 250 hours, and in the case of Comparative Example 4 having a Cu plating layer having a thickness of 1 μm, the elapsed time is 500 It can be seen that the thickness starts to decrease when the time is exceeded. In the case of Comparative Example 5 having a Cu plating layer with a thickness of 2 μm, the reduction in thickness after 1000 hours is only 1 μm.

It can be seen from FIGS. 14 to 18 that by controlling the thickness of the Cu plating layer, it is possible to suppress the formation of the (Ni, Cu) ₃ Sn ₄ alloy layer and the formation of the P-rich layer and to suppress the generation of voids.
Also in the bonding portion of the electronic component according to the present embodiment, as shown in FIG. 13, a predetermined amount of Cu plating layer is consumed after reflow, and according to the Cu content and thickness of the Ni-Cu-P plating layer. Generation of voids by setting the composition of the electroless Ni-Cu-P plating solution and the thickness of the Ni-Cu-P plating layer taking into consideration that the thickness corresponding to the case of plating a pure Cu layer is determined. Can be suppressed to improve the bonding reliability.

The embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is not the meaning described above, and is intended to include meanings equivalent to the claims and all modifications within the scope of the claims.
The electronic components are not limited to those used under high temperature such as power modules, and the configuration of this embodiment can be applied to various electronic components such as sensors including IoT sensors, MEMS, etc. .
Since the junction reliability is good, the electronic component can be miniaturized and thinned. Good bonding reliability can be maintained, including the case where the bonding portion is susceptible to heat generation of chip components and the like.

DESCRIPTION OF SYMBOLS 1 Power device 2 connection metal part 3 junction part 31 solder material 32 alloy layer 33 solder layer 34 junction part 4, 19 insulating substrate 5 Ni-P plating layer (or Ni plating layer: first plating layer)
6 heat sink 7 cooler 8 Ni-Cu-P plated layer (second plated layer)
9 Cu pad 10 case 11 Au plated layer (third plated layer)
12 terminal 13, 14 wire 15 resin layer 16 metal plate 18 OSP processing film 20, 21, 22, 37 power module 23 electronic component 24 substrate 25 chip component 26 Cu wiring

Claims (9)

In a method of manufacturing an electronic component in which a support having a metal layer and an adherend are connected using a solder material containing tin,
Nickel plating or nickel-phosphorus plating is performed on the metal layer of the support to form a first plating layer;
Nickel-copper-phosphorus plating is performed on the first plating layer to form a second plating layer,
Substitution gold plating is performed on the second plating layer to form a third plating layer,
The solder material is disposed between the third plating layer and the metal layer of the adherend,
The solder material is melted by heating and then solidified to form a joint portion having an alloy layer containing (Cu, Ni) ₆ Sn ₅ on the first plating layer side. Method.   The method of manufacturing an electronic component according to claim 1, wherein a content of copper in the second plating layer is 1% by mass or more and 98% by mass or less.   The nickel-copper-phosphorus plating is performed using a nickel-copper-phosphorus plating solution containing a copper salt of an inorganic acid and a nickel salt of the inorganic acid selected from the group consisting of sulfuric acid, nitric acid, hydrochloric acid and acetic acid, The method for manufacturing an electronic component according to claim 2, wherein the content of copper salt and nickel salt, pH, and bath temperature are adjusted to control the content of copper in the second plating layer. .   The method of manufacturing an electronic component according to any one of claims 1 to 3, wherein a content of phosphorus in the second plating layer is 0.1 mass% or more and 14 mass% or less.   The method of manufacturing an electronic component according to any one of claims 1 to 4, wherein the second plating layer is formed to have a thickness of 0.03 μm to 10 μm. Nickel-phosphorus plating layer is formed by electroless nickel-phosphorus plating,
The said nickel-copper- phosphorus plating is electroless nickel- copper- phosphorus plating, The manufacturing method of the electronic component of any one of Claim 1 to 5 characterized by the above-mentioned. The electronic component is a power module including one or two heat sinks each having a metal layer, an insulating substrate or a metal plate, and a power device,
The nickel plating or the nickel-phosphorus plating is performed on the metal layer of at least one member of the heat sink, the insulating substrate or the metal plate, and the power device. The manufacturing method of the electronic component of any one of-. In an electronic component in which a support having a metal layer and an adherend are connected by a solder material containing tin,
A nickel plating layer or a nickel-phosphorus plating layer provided on the metal layer of the support;
A nickel-copper-phosphorus plating layer provided on the nickel plating layer or on the nickel-phosphorus plating layer, an alloy layer containing (Cu, Ni) ₆ Sn ₅ formed on the nickel-copper-phosphorus plating layer, An electronic component comprising a solder layer containing tin and tin, and a bonding portion bonding the metal layer of the adherend.   9. The electronic component according to claim 8, wherein the reduction rate of the thickness of the nickel plating layer or the nickel-phosphorus plating layer is 0% or more and 50% or less after standing at 200 ° C. for 50 hours.