JP2005286274A - Soldering method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a soldering method for doing a die-bonding superior in heat resistance for a semiconductor chip such as transistors, IC, etc., especially, power transistors under easy temperature control. <P>SOLUTION: A solder having a Pb content of 75% or more and a sold-liquid phase line temperature difference of 20°C or higher is heated into a solid-liquid coexisting state to solder the interface in this state. The solder having the Pb content of 75% or more itself has a high heat resistance to heat cycles and, if the soldering temperature varies somewhat, surely can hold the solid-light coexistence state, this allowing a solder layer to be easily thick owing to a solid solution in the solid-liquid coexisting material. Thus the shearing strain γ applied to the solider layer under heat cycles, based on the difference between linear thermal expansion coefficients of works, is easily reduced and the heat resistance of the solder itself may be increased to satisfactorily prevent the breakdown (crack breakdown) of the solder layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a soldering method, and is particularly useful for die bonding of semiconductor chips.

In a series of semiconductor assembly processes in which wafer chips and semiconductor chips of integrated circuits are die-bonded to a substrate, electrodes and leads of the semiconductor chip are wire-bonded, and then packaged, the die bonding part is soldered to the printed wiring board of the semiconductor It must be able to withstand the temperature and wire bonding temperature, and gold-silicon eutectic method, conductive adhesive method, solder method and the like are used for the bonding.
In particular, in power transistors and power ICs, power consumption is large, and it is necessary to reduce the thermal resistance of the die bonding part in order to promote heat dissipation through the die bonding part and prevent overheating. The solder method is used because it is an electrode and it is necessary to reduce the electrical resistance. (Non-Patent Document 1)
The latest semiconductor assembly technology and its high reliability and full automation, 1990, pages 260-261, published by Applied Technology Publishing Company

  It is necessary to use a solder composition having a melting point higher than the soldering temperature of the semiconductor to the printed wiring board as the solder used for this soldering die bonding. Usually, a Sn-Pb alloy is used for soldering to the printed wiring board. Sn 40%, Pb 60% melting point of about 190 ° C. is used, so that the die bonding solder has a solidus temperature of 300 ° C. and a liquidus temperature of 314 ° C. Sn 5% − Pb 95% solder is used.

In power transistors, power ICs, etc., the power consumption at the pn junction is large, so when heat generation and natural cooling are repeated according to the intermittent operation of the mounted electronic device, it undergoes a thermal heat cycle and is bonded. If the linear thermal expansion coefficients of the two members, that is, the power transistor and the substrate are different, the solder layer at the joint interface is repeatedly exposed to shear stress.
That is, as shown in FIG. 1, the width of the die bonding portion is w, the thickness of the solder layer 3 is h, the linear thermal expansion coefficient of the power transistor 1 or the like is α, and the linear heat of the substrate 2 (for example, a copper lead frame). When the expansion coefficient is β (β> α) and the temperature rise is ΔT, the maximum shear strain γ applied to the solder layer by the thermal heat cycle is

γ = w · ΔT · (β−α) / h
The maximum shear stress τ is given by G as the shear modulus.

τ = γ / G
Given in.
In order to suppress fatigue failure at the die bonding interface due to the repetition of the maximum shear stress τ, it is effective to increase the fatigue resistance of the solder itself. In conventional Pb 95% and Pb 5% solder, the Pb content is low. Because of its large amount, it has better fatigue resistance than a Pb—Sn binary solder with less Pb.
However, with Pb95% -Sn5% solder, the difference between the solidus temperature and the liquidus temperature is small, and it is difficult to adjust the temperature to maintain the solder in a solid-liquid coexistence state. Since the liquid phase is completely changed to make the solder layer thickness h thinner, the above-described shear strain γ is increased, and the early fatigue fracture of the solder layer is unavoidable.

  An object of the present invention is to provide a soldering method capable of performing die bonding excellent in heat resistance of semiconductor chips such as transistors and ICs, particularly power transistors, under easy temperature control.

The soldering method according to claim 1 is to heat a solder having Pb of 75% or more and a solid-liquid phase temperature difference of 15 ° C. or more to be in a solid-liquid coexistence state, and solder the interface in this state. A characteristic soldering method.
The soldering method according to claim 2 is the soldering method according to claim 1, wherein one or more of Ag, Cu, Sb, Pd, Ni, Zn, Gd, and Pt is 0.1 to 25%. The soldering method according to claim 1, wherein the remaining solder is Pb.
The soldering method according to claim 3 is characterized in that in the soldering method according to claim 2, 0.1 to 10% of one or more of In, Bi, Sn, and Au is added to the solder. To do.
The soldering method according to claim 4 is the soldering method according to any one of claims 1 to 3, wherein 0.001 to 0.1% of one or more of P, Ga and Ge is added to the solder. It is characterized by that.
A soldering method according to a fifth aspect is characterized in that the soldering method according to any one of the first to fourth aspects is used for die bonding of a semiconductor chip.

Since the solder having a Pb content of 75% or more is used, the fatigue resistance (hereinafter referred to as heat resistance) of the solder itself against the thermal cycle can be increased.
Furthermore, the temperature range for maintaining the solid-liquid coexistence state (mixed state of solid solution and melt) is widened by setting the solid-liquid phase line temperature difference to 15 ° C or higher, so the soldering temperature varies somewhat during soldering. Even so, the solid-liquid coexistence state can be reliably maintained, and the thickness h of the solder layer can be easily increased due to the solid solution in the solid-liquid coexisting material. Therefore, the above-described shear strain γ applied to the solder layer can be satisfactorily reduced and the heat resistance of the solder itself can be increased under a thermal cycle based on the difference in coefficient of linear thermal expansion of the members to be joined. (Crack fracture) can be prevented well.
In particular, in claim 2, since a solder in which 0.1 to 25% of at least one of Ag, Cu, Sb, Pd, Ni, Zn, Gd, and Pt is added to Pb is used, the Pb content is 75. %, The liquidus temperature can be increased while maintaining excellent heat resistance against the thermal cycle of the solder itself based on% or more, and a solid-liquidus temperature difference of 15 ° C. or more can be easily set.
In particular, the wettability of the solder can be improved by adding one or more of In, Bi, Sn, and Au, and the bonding strength at the interface can be increased.
In particular, in claim 4, one or more of P, Ga, and Ge are preferentially oxidized when the solder is melted to prevent oxidation of other elements, and oxides such as P, Ga, and Ge are molten solder. Since it is difficult to float and get caught on the surface, the heat resistance of the solder itself can be maintained well by suppressing the decrease in mechanical strength due to oxidation of the solder layer.

Hereinafter, embodiments of the present invention will be described by taking die bonding of a power transistor as an example.
In FIG. 1, reference numeral 1 denotes a power transistor, which is a transistor having a collector loss of 600 mw or more used for medium / high power amplification, large current switching, a power supply regulator, and the like. Is provided. Reference numeral 2 denotes a substrate, for example, a lead frame, and a pad 21 made of Ag plating or the like is provided on the die mount portion.
Reference numeral 3 denotes a solder layer. A solder foil is placed on the pad 21, the power transistor 1 is placed thereon, a load is applied with a weight or a spring, the solder foil is melted by heating, and then cooled to solidify the molten solder. .
Instead of the solder foil, solder balls, cream solder, or solder wires may be used.

  For the solder foil, etc., a solder having a Pb content of 75% or more and a solid-liquid phase temperature difference of 15 ° C. or more, preferably 50 ° C. or more, more preferably 100 ° C. or more is used. The heating reference temperature is set so that the solid-liquid coexistence state of the solder can be ensured even if the temperature varies somewhat.

FIG. 2 shows a phase diagram (description) of the binary eutectic alloy. In FIG. 2, S _α is an α solid solution, S _β is a β solid solution, (S _α + S _β ) is a mixture of both solid solutions, L is a melt, a is a solidus temperature, and b is a liquid phase. (S _α + L) indicates the mixture of the solid solution S _α and the melt L, and (S _β + L) indicates the mixture of the solid solution S _β and the melt L, respectively. Even if the heating temperature of the solder fluctuates by ± ΔT with respect to the reference temperature T0 with respect to the phase line temperature T _s and the liquidus temperature T ₁ , the solid-liquid phase temperature difference (T ₁ −T _s ) is sufficiently large. If so, the state of the solder can be kept in a solid-liquid coexistence state, and the solder in such a state is not easily crushed and deformed due to the mixed solid solution, and the thickness of the solder layer can be sufficiently increased.
Therefore, in the soldering method according to the present invention, the solid-liquidus temperature difference (T ₁ −T _s ) is set to 20 ° C. or more, so if the minimum (T _s + 10 ° C.) is set as the reference temperature, ± Even if there is a temperature fluctuation of 10 ° C., the solder can be reliably soldered while maintaining the solid-liquid coexistence state, and the thickness of the solder layer can be made sufficiently thick.

In FIG. 2, the weight ratio of the solid solution to the melt at the temperature T0 is given by the ratio of the distance (ao-o) :( bo-o), and the solid phase ratio is 5 to 90%, preferably 15 to The alloy composition (solidus temperature and liquidus temperature) and the reference heating temperature T0 are set so as to be 70%. The reason for setting the solid phase ratio to 5 to 90% is that if it is less than 5%, it is too soft and it is difficult to make the solder layer thick, and if it exceeds 90%, the wettability of the solder is too low to ensure workability.
The reason why the Pb content of the solder is set to 75% or more is to ensure excellent fatigue resistance against thermal cycling by making Pb have an appropriate ductility and setting the Pb content to 75% or more.
Inclusion of 0.1 to 25% of one or more of Ag, Cu, Sb, Pd, Ni, Zn, Gd, and Pt can increase the liquidus temperature and widen the solid-liquidus temperature difference. it can. The reason for limiting the addition amount to 0.1 to 25% is that if the amount is less than 0.1%, the increase in the liquidus temperature cannot be obtained satisfactorily. This is because it is difficult to maintain (excellent fatigue resistance) and the solidus temperature becomes too high, which hinders die bonding work.
When 0.1 to 10% of one or more of In, Bi, Sn, and Au is contained, the wettability is improved, and the workability of the joining work and the interface joining strength are improved. The reason for limiting the addition amount to 0.1 to 10% is that the wettability is not substantially changed if it is less than 0.1%, and if it exceeds 10%, the solidus temperature is too low and desired in the die bonding part. It is because it becomes difficult to provide the heat-resistant temperature.
If 0.001 to 0.1% of one or more of P, Ga, and Ge is added to the solder, P, Ga, and Ge are preferentially oxidized during the melting of the solder, and oxidation of other elements is prevented. The oxide of P, Ga, Ge, etc. floats on the surface of the molten solder, and the entrainment of the molten solder is suppressed. Can be maintained well. The reason for limiting the addition amount to 0.001 to 0.1% is that if the amount is 0.001% or less, the above-mentioned antioxidant cannot be obtained satisfactorily, and if it exceeds 0.1%, the above heat resistance is maintained. It is difficult.
As the solder, Ag 5 to 15%, the balance Pb, or 0.2 or more of In, Cu, Sb, Au, Pd, Ni, Bi, Zn, Sn, Gd, and Pt in 100 parts by weight of this composition. What added -7 weight part can be used conveniently.

After die bonding of the power transistor by the soldering method according to the present invention, wire bonding is performed between the internal lead of the lead frame and the aluminum electrode of the power transistor, and further resin packaging is performed by a transfer molding method. The outer portion of the lead frame is removed to finish the assembly of the power transistor.
The power transistor thus assembled is soldered to the printed wiring board by a reflow method or a flow method.
The solidus temperature of the solder used for die bonding is sufficiently higher than the reflow temperature and flow temperature, and the die bonding portion can be stably held against reflow soldering and flow soldering.

In the power transistor, the collector loss is as large as 600 mw or more, and the solder layer at the die bonding interface is exposed to thermal cycle stress by repeating heat generation and natural cooling at the pn junction according to the intermittent operation of the mounted electronic device. Is done.
The stress is such that the width of the die bonding interface is w, the thickness of the solder layer is h, the linear thermal expansion coefficient of the power transistor is α, the linear thermal expansion coefficient of the substrate (for example, a copper lead frame) is β (β> α), If the temperature rise is ΔT and the shear elastic modulus is G,

τ = w · ΔT · (β−α) / (Gh)
Given in.
Thus, according to the soldering method of the present invention, the heat resistance against repeated thermal stress of the solder itself can be increased, and the thickness h of the solder layer can be easily increased. (Of course, since die bonding is performed under a predetermined pressure by a weight or a spring, non-welded portions such as voids are generated at the interface between the solder layer and the power transistor and the interface between the solder layer and the lead frame. And can be well prevented by stress concentration).

The composition of the solder was Pb-Ag10% -Sn1%. The solder has a solidus temperature of 296 ° C., a liquidus temperature of 440 ° C., and a solid-liquid phase temperature difference of 144 ° C. The solid phase ratio at a temperature of 330 ° C. is 63%, the solid phase ratio at a temperature of 350 ° C. is 53%, and the solid phase ratio at a temperature of 370 ° C. is 44%.
When this solder was used, the heating reference temperature was set to 350 ° C., and the heating temperature was varied in the range of ± 10 ° C., and the power transistor was die-bonded to the copper lead frame, the thickness of the solder layer was 50 ± 3 μm.

The composition of the solder was Pb-Ag 10%. The solder has a solidus temperature of 304 ° C., a liquidus temperature of 450 ° C., and a solid-liquid phase temperature difference of 146 ° C. The solid phase ratio at a temperature of 330 ° C. is 63%, the solid phase ratio at a temperature of 350 ° C. is 53%, and the solid phase ratio at a temperature of 370 ° C. is 44%.
When this solder was used, the heating reference temperature was set to 350 ° C., and the heating temperature was varied in the range of ± 10 ° C., and the power transistor was die-bonded to the copper lead frame, the thickness of the solder layer was 54 ± 3 μm.

The composition of the solder was Pb—Ag 10% —In 5%. The solder has a solidus temperature of 420 ° C., a liquidus temperature of 290 ° C., and a solid-liquid phase temperature difference of 130 ° C. The solid phase ratio at a temperature of 330 ° C. is 55%, the solid phase ratio at a temperature of 350 ° C. is 45%, and the solid phase ratio at a temperature of 370 ° C. is 44%.
When this solder was used, the heating reference temperature was set to 350 ° C., and the heating temperature was varied in the range of ± 10 ° C., and the power transistor was die-bonded to the copper lead frame, the thickness of the solder layer was 45 ± 3 μm.

The composition of the solder was Pb-Ag 10% -Ni 0.5%. The solder has a solidus temperature of 304 ° C., a liquidus temperature of 450 ° C., and a solid-liquid phase temperature difference of 100 ° C. The solid phase ratio at a temperature of 330 ° C. is 64%, the solid phase ratio at a temperature of 350 ° C. is 54%, and the solid phase ratio at a temperature of 370 ° C. is 45%.
Using this solder, the heating reference temperature was set to 350 ° C., the heating temperature was varied in the range of ± 10 ° C., and the power transistor was die-bonded to the copper lead frame. The thickness of the solder layer was 49 ± 3 μm.

[Comparative example]
The composition of the solder is a Pb—Sn 5% -Ag 1.5% eutectic alloy, and the eutectic temperature is 296 ° C.
When this solder was used, the heating reference temperature was set to 350 ° C., and the heating temperature was varied within a range of ± 10 ° C., and the power transistor was die-bonded to the copper lead frame, the thickness of the solder layer was 20 ± 1 μm.

  The power transistors assembled in these examples and comparative examples were mounted on a printed wiring board using normal Pb-Sn 60% solder, and a surfer fatigue test (1 minute on / 2 minutes off, the temperature difference between them was measured. When the number of cycles at which the die bonding part breaks was measured so that the temperature became approximately 100 ° C.), all of the products of the examples had 10 k cycles or more, which was superior to the comparative example.

  The soldering method according to the present invention includes bonding between the semiconductor chip such as a power transistor and the lead frame, bonding between the semiconductor chip and the bottom of the package container, and further, the assembled semiconductor and printed wiring. It can also be used for joining with plates.

It is drawing which shows the die bonding part of the semiconductor chip using the soldering method which concerns on this invention. It is a state figure of the alloy used in order to explain the heating temperature in the soldering method concerning the present invention.

Explanation of symbols

1 Semiconductor chip 2 Substrate 3 Solder layer a Solidus temperature b Liquidus temperature T0 Reference heating temperature

Claims (5)

A soldering method comprising heating a solder having a Pb of 75% or more and a solid-liquid phase temperature difference of 15 ° C. or more to be in a solid-liquid coexistence state, and soldering the interface in this state. The solder according to claim 1, wherein one or more of Ag, Cu, Sb, Pd, Ni, Zn, Gd, and Pt is 0.1 to 25%, and the balance is Pb. Attaching method. 3. The soldering method according to 2, wherein 0.1 to 10% of one or more of In, Bi, Sn, and Au is added to the solder. The soldering method according to any one of claims 1 to 3, wherein 0.001 to 0.1% of one or more of P, Ga, and Ge is added to the solder. The soldering method according to claim 1, wherein the soldering method is used for die bonding of a semiconductor chip.

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