JP2019085631A5 - - Google Patents
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- JP2019085631A5 JP2019085631A5 JP2017216616A JP2017216616A JP2019085631A5 JP 2019085631 A5 JP2019085631 A5 JP 2019085631A5 JP 2017216616 A JP2017216616 A JP 2017216616A JP 2017216616 A JP2017216616 A JP 2017216616A JP 2019085631 A5 JP2019085631 A5 JP 2019085631A5
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- JP
- Japan
- Prior art keywords
- plating
- nickel
- layer
- plating layer
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000007747 plating Methods 0.000 claims 54
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 20
- -1 nickel-phosphorus Chemical compound 0.000 claims 16
- 229910000679 solder Inorganic materials 0.000 claims 11
- 229910052759 nickel Inorganic materials 0.000 claims 10
- 239000002184 metal Substances 0.000 claims 8
- 229910052751 metal Inorganic materials 0.000 claims 8
- 229910052802 copper Inorganic materials 0.000 claims 7
- 239000010949 copper Substances 0.000 claims 7
- 238000004519 manufacturing process Methods 0.000 claims 7
- 239000000463 material Substances 0.000 claims 6
- 239000004065 semiconductor Substances 0.000 claims 6
- 229910045601 alloy Inorganic materials 0.000 claims 5
- 239000000956 alloy Substances 0.000 claims 5
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical class [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims 5
- 239000000758 substrate Substances 0.000 claims 4
- 229910052718 tin Inorganic materials 0.000 claims 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N tin hydride Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N HCl Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims 2
- 150000001879 copper Chemical class 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 150000007522 mineralic acids Chemical class 0.000 claims 2
- 150000002815 nickel Chemical class 0.000 claims 2
- 239000011347 resin Substances 0.000 claims 2
- 229920005989 resin Polymers 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims 1
Claims (9)
前記第１の金属層上に、ニッケル（Ｎｉ）めっき又はニッケル−リン（Ｎｉ−Ｐ）めっきにより第１めっき層を形成し、 A first plating layer is formed on the first metal layer by nickel (Ni) plating or nickel-phosphorus (Ni-P) plating.
前記第１めっき層上に、ニッケル−銅−リン（Ｎｉ−Ｃｕ−Ｐ）めっきにより第２めっき層を形成し、 A second plating layer is formed on the first plating layer by nickel-copper-phosphorus (Ni-Cu-P) plating.
前記第２めっき層と、前記第２の金属層との間に、前記半田材料を配置し、 The solder material is arranged between the second plating layer and the second metal layer.
前記半田材料を溶融させ、前記第１めっき層側に（Ｃｕ，Ｎｉ） The solder material is melted and placed on the first plating layer side (Cu, Ni). 6 6 ＳｎSn 5 Five を含む合金層を有する接合部分を形成することを特徴とする電子部品の製造方法。A method for manufacturing an electronic component, which comprises forming a joint portion having an alloy layer containing.
前記第１の金属層上に、ニッケル（Ｎｉ）めっき又はニッケル−リン（Ｎｉ−Ｐ）めっきにより第１めっき層を形成し、 A first plating layer is formed on the first metal layer by nickel (Ni) plating or nickel-phosphorus (Ni-P) plating.
前記第１めっき層上に、ニッケル−銅−リン（Ｎｉ−Ｃｕ−Ｐ）めっきにより第２めっき層を形成し、 A second plating layer is formed on the first plating layer by nickel-copper-phosphorus (Ni-Cu-P) plating.
前記第２めっき層上に、金（Ａｕ）めっきにより第３めっき層を形成し、 A third plating layer is formed on the second plating layer by gold (Au) plating.
前記第３めっき層と、前記第２の金属層との間に、前記半田材料を配置し、 The solder material is arranged between the third plating layer and the second metal layer.
前記半田材料を溶融させ、前記第１めっき層側に（Ｃｕ，Ｎｉ） The solder material is melted and placed on the first plating layer side (Cu, Ni). 6 6 ＳｎSn 5 Five を含む合金層を有する接合部分を形成し、Forming a junction with an alloy layer containing
前記第２めっき層は、厚みが０．０３μｍ以上１０μｍ以下であり、 The second plating layer has a thickness of 0.03 μm or more and 10 μm or less.
前記第２めっき層中の銅の含有量は、１質量％以上９８質量％以下であることを特徴とする電子部品の製造方法。 A method for manufacturing an electronic component, wherein the content of copper in the second plating layer is 1% by mass or more and 98% by mass or less.
前記銅塩及びニッケル塩の含有量、ｐＨ、浴温を調整して、前記第２めっき層中の銅の含有量を制御することを特徴とする請求項１又は請求項２記載の電子部品の製造方法。 The electronic component according to claim 1 or 2, wherein the content, pH, and bath temperature of the copper salt and nickel salt are adjusted to control the copper content in the second plating layer. Production method.
前記ニッケル−銅−リン（Ｎｉ−Ｃｕ−Ｐ）めっきは、無電解ニッケル−銅−リン（Ｎｉ−Ｃｕ−Ｐ）めっきであることを特徴とする請求項１又は請求項２記載の電子部品の製造方法。 The electronic component according to claim 1 or 2, wherein the nickel-copper-phosphorus (Ni-Cu-P) plating is electroless nickel-copper-phosphorus (Ni-Cu-P) plating. Production method.
前記半導体素子と前記放熱板間に、前記第１めっき層が形成され、 The first plating layer is formed between the semiconductor element and the heat radiating plate.
２００℃で５０時間放置した後に、前記第１めっき層の厚みの減少率が０％以上５０％以下であることを特徴とする請求項１又は請求項２記載の電子部品の製造方法。 The method for manufacturing an electronic component according to claim 1 or 2, wherein the reduction rate of the thickness of the first plating layer is 0% or more and 50% or less after being left at 200 ° C. for 50 hours.
ニッケル（Ｎｉ）めっき又はニッケル−リン（Ｎｉ−Ｐ）めっきにより、前記配線上に形成された第１めっき層と、 A first plating layer formed on the wiring by nickel (Ni) plating or nickel-phosphorus (Ni-P) plating,
ニッケル−銅−リン（Ｎｉ−Ｃｕ−Ｐ）めっきにより、前記第１めっき層上に形成された第２めっき層と、 A second plating layer formed on the first plating layer by nickel-copper-phosphorus (Ni-Cu-P) plating, and
前記電極と前記第２めっき層間に、すずを含む半田層が形成され、 A solder layer containing tin is formed between the electrode and the second plating layer.
前記半田層の前記第２めっき層側に、（Ｃｕ，Ｎｉ） On the second plating layer side of the solder layer, (Cu, Ni) 6 6 ＳｎSn 5 Five を含む合金層が形成されていることを特徴とする電子部品。An electronic component characterized in that an alloy layer containing the above is formed.
ニッケル（Ｎｉ）めっき又はニッケル−リン（Ｎｉ−Ｐ）めっきにより、前記放熱部材に形成された第１めっき層と、 A first plating layer formed on the heat radiating member by nickel (Ni) plating or nickel-phosphorus (Ni-P) plating, and
ニッケル−銅−リン（Ｎｉ−Ｃｕ−Ｐ）めっきにより、前記第１めっき層上に形成された第２めっき層と、 A second plating layer formed on the first plating layer by nickel-copper-phosphorus (Ni-Cu-P) plating, and
ニッケル（Ｎｉ）めっき又はニッケル−リン（Ｎｉ−Ｐ）めっきにより、前記配線上に形成された第３めっき層と、 A third plating layer formed on the wiring by nickel (Ni) plating or nickel-phosphorus (Ni-P) plating,
ニッケル−銅−リン（Ｎｉ−Ｃｕ−Ｐ）めっきにより、前記第３めっき層上に形成された第４めっき層と、 A fourth plating layer formed on the third plating layer by nickel-copper-phosphorus (Ni-Cu-P) plating, and
前記第２めっき層と前記第４めっき層間に、すずを含む半田層が形成され、 A solder layer containing tin is formed between the second plating layer and the fourth plating layer.
前記半田層の前記第２めっき層側に、（Ｃｕ，Ｎｉ） On the second plating layer side of the solder layer, (Cu, Ni) 6 6 ＳｎSn 5 Five を含む第１の合金層が形成され、A first alloy layer containing
前記半田層の前記第４めっき層側に、（Ｃｕ，Ｎｉ） On the fourth plating layer side of the solder layer, (Cu, Ni) 6 6 ＳｎSn 5 Five を含む第２の合金層が形成されていることを特徴とする電子部品。An electronic component characterized in that a second alloy layer containing the above is formed.
前記半導体素子と、前記基板は、前記ケースに収容され、 The semiconductor element and the substrate are housed in the case.
前記ケースの内部に、絶縁樹脂が充填されていることを特徴とする請求項６又は請求項７記載の電子部品。 The electronic component according to claim 6 or 7, wherein the inside of the case is filled with an insulating resin.
前記半導体素子と、前記基板は、前記ケースに収容され、 The semiconductor element and the substrate are housed in the case.
前記ケースの内部に、絶縁樹脂が充填され、 The inside of the case is filled with an insulating resin.
前記ケースの内側に突出した段部が設けられており、前記段部に端子が設けられ、 A step portion protruding inside the case is provided, and a terminal is provided on the step portion.
前記端子と前記電極間が、ワイヤにより接続されていることを特徴とする請求項６又は請求項７記載の電子部品。 The electronic component according to claim 6 or 7, wherein the terminal and the electrode are connected by a wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017216616A JP6967252B2 (en) | 2017-11-09 | 2017-11-09 | Manufacturing method of electronic parts and electronic parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017216616A JP6967252B2 (en) | 2017-11-09 | 2017-11-09 | Manufacturing method of electronic parts and electronic parts |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019085631A JP2019085631A (en) | 2019-06-06 |
| JP2019085631A5 true JP2019085631A5 (en) | 2020-11-26 |
| JP6967252B2 JP6967252B2 (en) | 2021-11-17 |
Family
ID=66763946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017216616A Active JP6967252B2 (en) | 2017-11-09 | 2017-11-09 | Manufacturing method of electronic parts and electronic parts |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6967252B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7306712B2 (en) * | 2019-07-26 | 2023-07-11 | 株式会社クオルテック | Heater chip and bonding layer evaluation device |
| CN112259383B (en) * | 2020-10-19 | 2022-02-22 | 南京工程学院 | In-situ preparation method of electrode coated with nickel molybdate copper composite film |
| JP2023079124A (en) | 2021-11-26 | 2023-06-07 | 国立大学法人東北大学 | Power semiconductor element and power semiconductor module |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3910363B2 (en) * | 2000-12-28 | 2007-04-25 | 富士通株式会社 | External connection terminal |
| JP5099644B2 (en) * | 2006-05-29 | 2012-12-19 | 日本電気株式会社 | Electronic components, semiconductor packages and electronic equipment |
| JP5450192B2 (en) * | 2010-03-24 | 2014-03-26 | 日立オートモティブシステムズ株式会社 | Power module and manufacturing method thereof |
| JP6569511B2 (en) * | 2015-12-17 | 2019-09-04 | 三菱マテリアル株式会社 | Bonded body, power module substrate with cooler, and method for manufacturing power module substrate with cooler |
-
2017
- 2017-11-09 JP JP2017216616A patent/JP6967252B2/en active Active
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