JP2007063042A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2007063042A5 JP2007063042A5 JP2005248594A JP2005248594A JP2007063042A5 JP 2007063042 A5 JP2007063042 A5 JP 2007063042A5 JP 2005248594 A JP2005248594 A JP 2005248594A JP 2005248594 A JP2005248594 A JP 2005248594A JP 2007063042 A5 JP2007063042 A5 JP 2007063042A5
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- film
- alloy film
- film containing
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910045601 alloy Inorganic materials 0.000 claims description 22
- 239000000956 alloy Substances 0.000 claims description 22
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical class [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- 229910052737 gold Inorganic materials 0.000 claims description 21
- 239000000919 ceramic Substances 0.000 claims description 19
- 229910052763 palladium Inorganic materials 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 229910018104 Ni-P Inorganic materials 0.000 claims description 2
- 229910018536 Ni—P Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 description 18
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 229910002710 Au-Pd Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 210000001503 Joints Anatomy 0.000 description 1
- BFDHFSHZJLFAMC-UHFFFAOYSA-L Nickel(II) hydroxide Chemical compound [OH-].[OH-].[Ni+2] BFDHFSHZJLFAMC-UHFFFAOYSA-L 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Description
第１の発明は、セラミクス基体に複数の外部電極を有する基板であって、前記外部電極はセラミクス基体に形成されるＡｇもしくはＣｕを主体とする下地層と、当該下地層の表面にＮｉを主体とする皮膜と、その表面にＰｄを主体とする皮膜と、その表面にＡｕとＰｄを含む合金皮膜を有することを特徴とするセラミクス基板である。
Ｎｉを主体とする膜とＡｕとＰｄを含む合金膜の間にＰｄ層を設けることにより、置換金のＮｉへの腐食、ピンホールを抑えることができる。パラジュームめっきは還元法によってＮｉを主体とする膜に析出されるため、ニッケルを主体とする層を腐食しない。腐食によるピンホールが少ないため、金層を薄くしても、最表面が水酸化ニッケルで汚染されることが無くなる。
本発明では、前記Ｎｉを主体とする皮膜がＮｉとＢを含む合金皮膜又はＮｉとＰを含む合金皮膜であり、前記Ｐｄを主体とする皮膜が純Ｐｄ膜又はＰｄとＰを含む合金皮膜であるのも好ましい。
A first invention is a substrate having a plurality of external electrodes on a ceramic substrate, wherein the external electrodes are mainly composed of Ag or Cu formed on the ceramic substrate, and Ni is mainly formed on the surface of the substrate. and the film to be a film composed mainly of Pd on the surface thereof, a ceramic substrate, characterized in that it comprises an alloy film comprising Au and Pd on the surface thereof.
By providing a Pd layer between a film mainly composed of Ni and an alloy film containing Au and Pd , corrosion of the substitution gold to Ni and pinholes can be suppressed. Palladium plating is deposited on a film mainly composed of Ni by a reduction method, and therefore does not corrode a layer mainly composed of nickel. Since there are few pinholes due to corrosion, the outermost surface is not contaminated with nickel hydroxide even if the gold layer is thinned.
In the present invention, the Ni-based film is an alloy film containing Ni and B or an Ni-P alloy film, and the Pd-based film is a pure Pd film or an alloy film containing Pd and P. It is also preferable.
また前記ＡｕとＰｄを含む合金皮膜が、厚みが０．０５μｍ超２μｍ未満でＰｄを主体とする皮膜と、その表面に形成された厚みが０．０２μｍ超０．１μｍ未満のＡｕを主体とする皮膜との相互拡散によって形成されるのが好ましい。
Ａｕ膜が０．０２μｍ以下の膜厚であると、ＡｕとＰｄを含む合金皮膜とした後、ボンディングの際に金線とのなじみが悪く、十分な強度がでない。また、半田づけの際に半田への拡散が悪く、半田濡れ性が良くない。金膜が０．１μｍ以上の膜厚であると、金は高価な金属であるため、製造コストの増加を招く。
ＡｕとＰｄを含む合金皮膜は、２５０℃超４００℃未満でセラミクス基板を加熱することで形成するのが好ましい。
The alloy film containing Au and Pd has a thickness of more than 0.05 μm and less than 2 μm and mainly Pd, and a thickness formed on the surface thereof is mainly 0.02 μm and less than 0.1 μm of Au. It is preferably formed by mutual diffusion with the film.
When the Au film has a film thickness of 0.02 μm or less, after forming an alloy film containing Au and Pd, the bonding with the gold wire is poor at the time of bonding and the strength is not sufficient. Also, the solder does not diffuse well during soldering, and the solder wettability is not good. When the gold film has a film thickness of 0.1 μm or more, gold is an expensive metal, which increases the manufacturing cost.
The alloy film containing Au and Pd is preferably formed by heating the ceramic substrate at a temperature higher than 250 ° C. and lower than 400 ° C.
第２の発明は、第１の発明のセラミクス基体に半導体やリアクタンス素子を実装素子として搭載し、表面がＡｕとＰｄを含む合金皮膜の外部電極と半導体とを１００μｍ以下のＡｕ線で結線したことを特徴とする電子部品である。
前記ＡｕとＰｄを含む合金皮膜を、実装素子をセラミクス基板へリフローはんだ付けする際の加熱により形成しても良い。
また前記セラミクス基体を予め加熱し、前記外部電極の最表層金属膜をＡｕ−Ｐｄ合金としても良い。
パラジュウム膜は、はんだへの拡散速度が遅く半田濡れが悪いため、電子部品をプリント基板等に実装する際にはんだ接合不良の不具合を起こすリスクが大きくなる。そこで最表層金属膜を均一なＡｕ−Ｐｄ合金膜とすることにより、速やかに半田中に拡散し、強固な接着強度が得られる。ボンディングの際にも、薄いＡｕ膜は金線とのなじみが悪く、十分な接着強度が得られない場合もあるが、均一なＡｕ−Ｐｄ合金では、金線と強い接着強度をもたらす。
In the second invention , a semiconductor or a reactance element is mounted as a mounting element on the ceramic substrate of the first invention, and the external electrode of the alloy film containing Au and Pd on the surface and the semiconductor are connected by an Au wire of 100 μm or less. Is an electronic component characterized by
The alloy film containing Au and Pd may be formed by heating when reflow soldering the mounting element to the ceramic substrate.
The ceramic substrate may be preheated and the outermost metal film of the external electrode may be made of an Au—Pd alloy.
The palladium film has a low diffusion rate into the solder and poor solder wettability, so that there is a high risk of causing defective solder joints when mounting electronic components on a printed circuit board or the like. Therefore, by making the outermost layer metal film a uniform Au—Pd alloy film, it diffuses quickly into the solder, and a strong adhesive strength is obtained. Even during bonding, a thin Au film does not fit well with a gold wire, and sufficient adhesive strength may not be obtained. However, a uniform Au—Pd alloy provides strong adhesive strength with a gold wire.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005248594A JP4817043B2 (en) | 2005-08-30 | 2005-08-30 | Ceramic substrate, electronic component using ceramic substrate, and method for manufacturing ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005248594A JP4817043B2 (en) | 2005-08-30 | 2005-08-30 | Ceramic substrate, electronic component using ceramic substrate, and method for manufacturing ceramic substrate |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007063042A JP2007063042A (en) | 2007-03-15 |
| JP2007063042A5 true JP2007063042A5 (en) | 2008-08-28 |
| JP4817043B2 JP4817043B2 (en) | 2011-11-16 |
Family
ID=37925651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005248594A Active JP4817043B2 (en) | 2005-08-30 | 2005-08-30 | Ceramic substrate, electronic component using ceramic substrate, and method for manufacturing ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4817043B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6024242B2 (en) | 2012-07-02 | 2016-11-09 | セイコーエプソン株式会社 | Manufacturing method of electronic device |
| JP2014146652A (en) | 2013-01-28 | 2014-08-14 | Toppan Printing Co Ltd | Wiring board and method of manufacturing the same |
| JP5906264B2 (en) * | 2014-02-12 | 2016-04-20 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
| JPWO2022030637A1 (en) | 2020-08-07 | 2022-02-10 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2543619B2 (en) * | 1990-09-05 | 1996-10-16 | 新光電気工業株式会社 | Lead frame for semiconductor device |
| JPH06260577A (en) * | 1993-03-08 | 1994-09-16 | Nec Corp | Coating structure of wiring electrode |
| JPH1050915A (en) * | 1996-08-06 | 1998-02-20 | Hitachi Ltd | Semiconductor device and its manufacture |
| JP3728572B2 (en) * | 1996-10-31 | 2005-12-21 | 株式会社日立製作所 | Wiring board manufacturing method |
| JPH10284666A (en) * | 1997-04-01 | 1998-10-23 | Furukawa Electric Co Ltd:The | Electronic component device |
| JPH10287994A (en) * | 1997-04-14 | 1998-10-27 | World Metal:Kk | Plating structure of bonding part |
| JPH10289973A (en) * | 1997-04-16 | 1998-10-27 | Sony Corp | Surface treatment method of lead frame |
| JP2004055624A (en) * | 2002-07-16 | 2004-02-19 | Murata Mfg Co Ltd | Process for producing substrate |
| JP2005158771A (en) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JPWO2005116300A1 (en) * | 2004-05-25 | 2008-04-03 | 新光電気工業株式会社 | Semiconductor component exterior palladium plating structure and method for manufacturing semiconductor device |
-
2005
- 2005-08-30 JP JP2005248594A patent/JP4817043B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2007123883A (en) | Method of forming plating layer of print circuit board and print circuit board manufactured by the method | |
| JP3760075B2 (en) | Lead frame for semiconductor packages | |
| JP4674120B2 (en) | Wiring board and manufacturing method thereof | |
| JP5293185B2 (en) | Manufacturing method of electronic parts | |
| MY138109A (en) | Electronic part and surface treatment method of the same | |
| JP2007063042A5 (en) | ||
| TWI228309B (en) | Semiconductor device | |
| JP2002167676A (en) | Electroless gold plating method | |
| JP2001274539A (en) | Electrode joining method for printed wiring board loaded with electronic device | |
| JP2017525140A (en) | Film assembly manufacturing method and corresponding film assembly | |
| KR101184875B1 (en) | Electric joint structure, and method for preparing the same | |
| JP4817043B2 (en) | Ceramic substrate, electronic component using ceramic substrate, and method for manufacturing ceramic substrate | |
| JP3660798B2 (en) | Circuit board | |
| JP2000077593A (en) | Lead frame for semiconductor | |
| TWI576933B (en) | Method of forming package structure | |
| JP2002289653A (en) | Semiconductor device tape carrier and its manufacturing method | |
| JP5680342B2 (en) | Plating film, printed wiring board and module substrate | |
| JP2004055624A (en) | Process for producing substrate | |
| JPH04144190A (en) | Circuit board and manufacture thereof | |
| JP4012527B2 (en) | Manufacturing method of electronic parts | |
| JP2008028069A (en) | Substrate with externally bonded electrode, and method for manufacturing the same | |
| JP5625510B2 (en) | Terminal structure, printed wiring board, module substrate, and electronic device | |
| JP3757539B2 (en) | Stem for semiconductor device | |
| KR101167650B1 (en) | Lead frame for semiconductor device | |
| KR100691337B1 (en) | A Leadframe for Fabricating Semiconductor Device Using Spot Plating |