JP2019067985A - Semiconductor device and display device - Google Patents

Abstract

To provide a semiconductor device that is able to improve contact stability and maintain the characteristic of a thin film transistor, and to provide a display device using this semiconductor device.SOLUTION: A semiconductor device comprises: a substrate 11 on which a first region 10-1, a second region 10-2, and a third region 10-3 are provided adjacent to one another in that order along a predetermined direction; first wiring provided in the first region, second region, and third region on the substrate; a semiconductor film 15 having a channel region 15a for a transistor Tr and low resistance regions 15b-1, 15b-2 provided between the channel region and the first region, the semiconductor film being provided between the first wiring and the substrate in the first region and being provided in contact with the first wiring in the second region; second wiring 17W provided closer to the substrate than to the semiconductor film and in contact with the first wiring in the third region; and an insulation film 14 provided between the first wiring in the first region and the semiconductor film. In the semiconductor film, the thickness of the low resistance region is less than the thickness of the second region.SELECTED DRAWING: Figure 2

Description

  The present technology relates to, for example, a semiconductor device and a display device having a contact portion for connecting a thin film transistor (TFT) and a storage capacitor.

  2. Description of the Related Art In recent years, development of thin film transistors using an oxide semiconductor film as a channel has been actively performed along with the increase in screen size and increase in speed of an active matrix drive type display (for example, Patent Document 1). For example, in a semiconductor device for driving a display device or the like, a storage capacitor is provided together with such a thin film transistor, and the thin film transistor and the storage capacitor are electrically connected.

JP, 2015-108731, A

  In semiconductor devices, it is desirable to maintain the characteristics of thin film transistors while improving the stability of such contacts (connections).

  Therefore, it is desirable to provide a semiconductor device capable of maintaining the characteristics of the thin film transistor while enhancing the stability of the contact, and a display device using the semiconductor device.

  A semiconductor device according to an embodiment of the present technology includes a substrate in which a first region, a second region, and a third region are provided adjacent in this order along a predetermined direction, a first region on the substrate, A first wiring provided in the second region and the third region, a channel region of the transistor, and a low resistance region provided between the channel region and the first region; A semiconductor film provided between the first wiring and the substrate, and in the second region, a semiconductor film in contact with the first wiring and a position closer to the substrate than the semiconductor film, and in contact with the first wiring in the third region In the semiconductor film, the thickness of the low resistance region is smaller than the thickness of the second region, and the semiconductor film includes the two wirings and the insulating film provided between the first wiring in the first region and the semiconductor film. is there.

  A display device according to an embodiment of the present technology includes a display element and a semiconductor device for driving the display element, and the semiconductor device includes a first region, a second region, and a third region along a predetermined direction. A substrate provided in order adjacently to each other, a first wiring provided in a first region, a second region and a third region on the substrate, a channel region of a transistor, and a channel region and a first region And a semiconductor film which is provided between the first wiring and the substrate in the first region and which is in contact with the first wiring in the second region, and the semiconductor film And a second wiring in contact with the first wiring in the third region, and an insulating film provided between the first wiring and the semiconductor film in the first region, and the semiconductor film has a low resistance The thickness of the area is smaller than the thickness of the second area .

  In the semiconductor device and the display device according to the embodiment of the present technology, the contact between the semiconductor film and the second wiring is formed via the first wiring in the second region and the third region. Here, in the semiconductor film, since the thickness of the low resistance region is smaller than the thickness of the second region, the diffusion distance of carriers from the low resistance region is shorter than the diffusion distance of carriers from the second region. .

  According to the semiconductor device, the display device, and the electronic device according to the embodiment of the present technology, the thickness of the semiconductor film in the low resistance region is smaller than the thickness of the semiconductor film in the second region. Carriers can be sufficiently diffused from the second region to the first region, and diffusion of carriers from the low resistance region to the channel region can be suppressed. Thus, the stability of the contact can be enhanced, and the characteristics of the thin film transistor can be maintained. In addition, the effect described here is not necessarily limited, and may be any effect described in the present disclosure.

1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present technology. (A) is a top view showing the structure of the transistor and contact part which were shown in FIG. 1, (B) is the sectional drawing. (A) is a top view showing the other structure of the contact part shown in FIG. 2, (B) is the sectional drawing. FIG. 7 is a schematic cross sectional view showing a process of manufacturing the semiconductor device shown in FIG. 1. It is a cross-sectional schematic diagram showing the process of following FIG. 4A. It is a cross-sectional schematic diagram showing the process of following FIG. 4B. It is a cross-sectional schematic diagram showing the process of following FIG. 4C. It is a cross-sectional schematic diagram showing the process of following FIG. 5A. FIG. 2 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Comparative Example 1. FIG. 7 is a schematic cross sectional view showing a process of manufacturing the semiconductor device shown in FIG. 6. It is a cross-sectional schematic diagram showing the process of following FIG. 7A. It is a cross-sectional schematic diagram showing the process of following FIG. 7B. (A) is a top view showing the structure of the contact part formed through FIGS. 7A-7C, (B) is the sectional drawing. It is a cross-sectional schematic diagram for demonstrating the magnitude | size of the connection hole shown in FIG. It is a cross-sectional schematic diagram for demonstrating the magnitude | size of the connection hole shown in FIG. FIG. 6 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Comparative Example 2. FIG. 11 is a schematic cross sectional view showing a process of manufacturing the semiconductor device shown in FIG. 10. It is a cross-sectional schematic diagram for demonstrating the diffusion distance of the carrier of the semiconductor film shown in FIG. It is a cross-sectional schematic diagram showing schematic structure of the contact part which concerns on a modification. FIG. 2 is a block diagram showing a functional configuration of a display device to which the semiconductor device shown in FIG. 1 and the like is applied. It is a block diagram showing the structure of the imaging device to which the semiconductor device shown in FIG. 1 etc. is applied. It is a block diagram showing the composition of electronic equipment.

  Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings.

Embodiment
[Constitution]
FIG. 1 schematically shows a cross-sectional configuration of a semiconductor device (semiconductor device 1) according to an embodiment of the present technology. The semiconductor device 1 is used in, for example, a drive circuit of a display device and an imaging device (a display device 2A of FIG. 14 described later and an imaging device 2B of FIG. 15). The semiconductor device 1 is provided with a top gate type thin film transistor (transistor Tr) and a storage capacitance (storage capacitance Cs), and the transistor Tr and the storage capacitance Cs are electrically connected by the contact portion 10.

  The transistor Tr has a semiconductor film 15 (first semiconductor film), a second insulating film 16 and a gate electrode 17 in this order on the substrate 11 via an UC (Under Coat) film 12 and a first insulating film 14. There is. The source / drain electrode 21 is electrically connected to the semiconductor film 15 (low resistance region 15 b described later).

  The storage capacitor Cs has the lower electrode 13 (second wiring) and the upper electrode 15C on the substrate 11 via the UC film 12, and a first insulating film between the lower electrode 13 and the upper electrode 15C. 14 is provided. The contact portion 10 is provided with a gate wiring 17W, and the semiconductor film 15 and the lower electrode 13 are electrically connected via the gate wiring 17W (first wiring). The semiconductor device 1 has a metal oxide film 18 and an interlayer insulating film 19 in this order on the gate electrode 17 and the gate wiring 17W. The source / drain electrode 21 is provided on the interlayer insulating film 19 and is connected to the semiconductor film 15 through a connection hole penetrating the interlayer insulating film 19 and the metal oxide film 18.

  In the semiconductor film 15, a region facing the gate electrode 17 is a channel region 15a of the transistor Tr, and a low resistance region 15b having a lower electrical resistance than the channel region 15a is provided adjacent to the channel region 15a. .

  The substrate 11 is made of, for example, glass, quartz and silicon. Alternatively, the substrate 11 may be made of, for example, a resin material such as PET (polyethylene terephthalate), PI (polyimide), PC (polycarbonate) or PEN (polyethylene naphthalate). Besides, a substrate obtained by forming an insulating material on a metal plate such as stainless steel (SUS) can also be used.

  The UC film 12 is for preventing migration of a substance such as sodium ion from the substrate 11 to the upper layer, and is made of an insulating material such as a silicon nitride (SiN) film and a silicon oxide (SiO) film. There is. For example, in the UC film 12, the UC film 12A and the UC film 12B may be sequentially stacked in this order from the position close to the substrate 11. For example, the UC film 12A is formed of a silicon nitride (SiN) film, and the UC film 12B is formed of a silicon oxide (SiO) film. The UC film 12 is provided over the entire surface of the substrate 11.

(Retention capacity Cs)
The lower electrode 13 is provided in a selective region on the UC film 12. A portion of the lower electrode 13 is exposed from the upper electrode 15 C and extends to the contact portion 10. The lower electrode 13 includes, for example, a metal such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti). The lower electrode 13 may be made of an alloy, or may be made of a laminated film including a plurality of metal films. The lower electrode 13 may be made of a conductive material other than metal.

  The first insulating film 14 is interposed between the lower electrode 13 and the upper electrode 15C. The first insulating film 14 is made of, for example, an inorganic insulating film such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), a silicon oxynitride (SiON), and an aluminum oxide film (AlOx).

  The upper electrode 15C faces the lower electrode 13 with the first insulating film 14 therebetween. As described later, the upper electrode 15C is formed, for example, in the same step as the semiconductor film 15, includes the same constituent material as the semiconductor film 15, and has the same thickness as the low resistance region 15b of the semiconductor film 15. have. For example, a low-resistance oxide semiconductor material can be used for the upper electrode 15C.

(Transistor Tr)
The semiconductor film 15 is provided in a selective region on the first insulating film 14. The semiconductor film 15 contains, for example, an oxide of at least one element of indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), and niobium (Nb). And an oxide semiconductor. Specifically, for the semiconductor film 15, indium tin oxide zinc (ITZO), indium gallium zinc oxide (IGZO: InGaZnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium tin oxide (ITO) and indium oxide (InO) can be used. The semiconductor film 15 may be configured using other semiconductor materials such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, or an organic semiconductor. The thickness of the semiconductor film 15 is, for example, 10 nm to 300 nm, and preferably 60 nm or less. By reducing the thickness of the semiconductor film 15, the absolute amount of defects contained in the semiconductor is reduced, and the negative shift of the threshold voltage can be suppressed. Therefore, excellent transistor characteristics with a high on / off ratio can be realized. Further, since the time required for forming the semiconductor film 15 is shortened, productivity can be improved.

  The low resistance regions 15b of the semiconductor film 15 are provided on both sides of the channel region 15a. The source / drain electrode 21 is connected to one low resistance region 15 b. The other low resistance region 15b (low resistance regions 15b-1 and 15b-2 in FIG. 2 described later) extends to the contact portion 10 and is connected to the lower electrode 13 of the storage capacitance Cs via the gate wiring 17W. There is.

The second insulating film 16 provided between the semiconductor film 15 and the gate electrode 17 functions as a gate insulating film. The second insulating film 16 has the same shape as the gate electrode 17 in plan view. That is, the transistor Tr is a thin film transistor having a self-aligned structure. The second insulating film 16 is, for example, a single layer film made of one of a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), a silicon nitride oxide film (SiON) and an aluminum oxide film (AlO _x ). Or it is comprised by the laminated film which consists of 2 or more types in them.

  The gate electrode 17 on the second insulating film 16 controls the carrier density in the channel region 15a by the applied gate voltage (Vg), and has a function as a wiring for supplying a potential. The constituent material of the gate electrode 17 is, for example, titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd) and copper (Cu). And alloys and alloys containing one of the following. Alternatively, it may be a compound film containing at least one of them and a laminated film containing two or more kinds. Also, for example, a transparent conductive film such as ITO may be used.

The metal oxide film 18 is provided, for example, on the entire surface of the substrate 11, covers the gate electrode 17 and the gate wiring 17W, and is in contact with the low resistance region 15b of the semiconductor film 15. For example, an aluminum oxide (Al ₂ O ₃ ) film can be used as the metal oxide film 18. By providing the metal oxide film 18 in contact with such a low resistance region 15b, the electrical resistance of the low resistance region 15b can be stably maintained.

The interlayer insulating film 19 is provided, for example, on the entire surface of the substrate 11. The interlayer insulating film 19 is formed of, for example, a laminated film in which an interlayer insulating film 19A, an interlayer insulating film 19B, and an interlayer insulating film 19C are sequentially laminated in this order from the position near the metal oxide film 18. For example, a silicon oxide (SiO ₂ ) film can be used as the interlayer insulating film 19A. A silicon nitride (SiN) film, a silicon oxynitride (SiON) film, or the like may be used as the interlayer insulating film 19A. For example, an aluminum oxide (Al ₂ O ₃ ) film can be used as the interlayer insulating film 19B. For example, a resin film having photosensitivity can be used for the interlayer insulating film 19C. Specifically, the interlayer insulating film 19C is made of, for example, a polyimide resin film. The interlayer insulating film 19C may be made of novolac resin, acrylic resin, or the like.

  The source / drain electrode 21 functions as a source or drain of the transistor Tr, and includes, for example, the same metal or transparent conductive film as those listed as constituent materials of the gate electrode 17. It is desirable that a material having good electrical conductivity be selected as the source and drain electrodes.

(Contact portion 10)
The configuration of the contact portion 10 will be described with reference to FIG. FIG. 2A shows a plan configuration of the contact portion 10, and FIG. 2B shows a cross-sectional configuration of the contact portion 10 together with the transistor Tr. In the contact portion 10, the first region 10-1 and the second region are sequentially arranged from the position near the transistor Tr along the extending direction of the wiring (the arrangement direction of the transistor Tr and the storage capacitance Cs, the X direction in FIG. 2). 10-2 and a third region 10-3 are provided adjacent to each other. A connection hole H is provided in the second region 10-2 and the third region 10-3. The semiconductor film 15 is in contact with the gate wiring 17W in the second region 10-2, and the lower electrode 13 is in contact with the gate wiring 17W in the third region 10-3. In FIG. 2, illustration of the UC film 12 is omitted.

  The first region 10-1 is a region in which the UC film 12, the first insulating film 14, the semiconductor film 15, the second insulating film 16 and the gate wiring 17 W are provided in this order on the substrate 11. That is, in the first region 10-1, the semiconductor film 15 is covered with the second insulating film 16. Although details will be described later, in the present embodiment, by providing such a first region 10-1, the influence on the semiconductor film 15 when forming a layer above the semiconductor film 15 is suppressed, and the contact It can improve stability.

  In the first region 10-1, the second insulating film 16 and the gate wiring 17W are provided on the semiconductor film 15, and it seems that the characteristics similar to those of the transistor are exhibited. However, the semiconductor of the first region 10-1 is The membrane 15 is adapted to function as a conductor. This is because the semiconductor film 15 is provided with low resistance regions (low resistance regions 15b-1 and 15b-2) adjacent to both sides of the first region 10-1, and the low resistance regions 15b-1 and 15b are provided. This is because the high concentration carrier of −2 is diffused to the first region 10-1 (diffusion distances ΔL1 and ΔL2 in FIG. 12 described later). The low resistance region 15b-1 is disposed between the channel region 15a and the first region 10-1, that is, on the transistor Tr side with respect to the first region 10-1. The low resistance region 15b-2 is disposed in the second region 10-2. The low resistance regions 15 b-1 and 15 b-2 are exposed from the second insulating film 16.

  Here, in the semiconductor film 15, the thickness (thickness t1) of the low resistance region 15b-1 on the transistor Tr side is smaller than the thickness (thickness t2) of the second region 10-2 (low resistance region 15b-2) ing. Although the details will be described later, the diffusion distance (diffusion distance ΔL1) of the carriers from the low resistance region 15b-1 is short while the diffusion distance (diffusion distance ΔL2) of the carriers from the low resistance region 15b-2 is maintained. Become. The semiconductor film 15 extends from the transistor Tr and has a low resistance region 15 b-1 between the transistor Tr and the contact portion 10 (first region 10-1), and the first region 10-of the contact portion 10 It is arrange | positioned at 1 and 2nd area | region 10-2. The thickness t1 of the semiconductor film 15 of the low resistance region 15b-1 is, for example, 10 nm to 40 nm, and the thickness t2 of the semiconductor film 15 of the second region 10-2 is, for example, 20 nm to 60 nm.

  The second insulating film 16 is provided only in the first region 10-1 of the contact portion 10. In other words, the region where the second insulating film 16 is provided is the first region 10-1. The second insulating film 16 in the first region 10-1 is formed in the same step as the second insulating film 16 of the transistor Tr. That is, it is made of the same material as the second insulating film 16 (gate insulating film) of the transistor Tr, and has the same thickness. In order to enhance the conductivity of the semiconductor film 15 in the first region 10-1, the length L1 in the X direction of the first region 10-1, that is, the length in the X direction of the second insulating film 16 is 2 μm or less Is preferred.

  The gate wiring 17W is provided over the first region 10-1, the second region 10-2, and the third region 10-3 of the contact portion 10. The end surface of the gate wiring 17W in the first region 10-1 is The second insulating film 16 is provided at the same position as the end surface of the second insulating film 16 in plan view. The gate wiring 17W is formed in the same step as the gate electrode 17 of the transistor Tr. That is, it is made of the same material as the gate electrode 17 of the transistor Tr, and has the same thickness.

  The second region 10-2 is a region in which the UC film 12, the first insulating film 14, the semiconductor film 15, and the gate wiring 17W are provided in this order on the substrate 11. That is, in the second region 10-2, the semiconductor film 15 and the gate wiring 17 W are in contact with each other by the connection hole H provided in the second insulating film 16.

  The third region 10-3 is a region in which the UC film 12, the lower electrode 13 and the gate wiring 17 W are provided in this order on the substrate 11. That is, in the third region 10-3, the lower electrode 13 and the gate wiring 17W are in contact with each other by the connection holes H provided in the first insulating film 14 and the second insulating film 16. The lower electrode 13 extends from, for example, the third region 10-3 to a part of the second region 10-2, but in the second region 10-2, the lower electrode 13 may An insulating film 14 is provided. The lower electrode 13 is disposed at a position closer to the substrate 11 than the semiconductor film 15.

The width (the size in the Y direction, the wiring width W ₁₀ ) of the lower electrode 13, the semiconductor film 15 and the gate wiring 17 W is, for example, 5 μm or less. Wire width W _10, the direction of the lower electrode 13 that is perpendicular to the flow of current, representative of the size of the semiconductor film 15 and the gate line 17W. The width (the size in the Y direction, the width W _H ) of the connection hole H is, for example, 3 μm. The length (the size in the X direction, the length L _{2 +3} ) of the connection hole H is, for example, 4 μm. The width W _H indicates the size of the connection hole H in the direction orthogonal to the current flow, and the length L _{2 +3} indicates the size of the connection hole H in the direction parallel to the current flow.

As shown in FIG. 3, the width W _H of the connection hole H may be larger than the wiring width W ₁₀ . As described later, in the semiconductor device 1, film reduction of the semiconductor film 15 in the contact portion 10 is suppressed, so the semiconductor can be stably stabilized even if the width W _H of the connection hole H is larger than the wiring width W _10. The film 15 and the lower electrode 13 can be connected. Accordingly, the present technique can be suitably used for a high-definition semiconductor device having a small wiring width W _10.

  For example, the gate wiring 17W may be provided in a region other than the contact portion 10. Between the gate wiring 17W and the first insulating film 14, a second insulating film 16 having the same shape as the gate wiring 17W in plan view is provided.

[Production method]
The semiconductor device 1 as described above can be manufactured, for example, as follows (FIGS. 4A to 5B).

  First, as shown in FIG. 4A, the UC film 12, the lower electrode 13, the first insulating film 14, the semiconductor film 15, and the second insulating film 16 are formed in this order on the substrate 11. Specifically, for example, it is formed as follows. First, the UC film 12 is formed on the entire surface of the substrate 11. Next, a metal film, for example, is formed on the UC film 12, and the metal film is patterned into a predetermined shape by dry etching to form the lower electrode 13. Subsequently, the first insulating film 14 is formed on the entire surface of the substrate 11 so as to cover the lower electrode 13. Next, an oxide semiconductor material, for example, is formed on the first insulating film 14 by sputtering, for example, and then patterned into a predetermined shape by, for example, photolithography and etching to form a semiconductor film 15. Thereafter, the second insulating film 16 is formed on the entire surface of the substrate 11 so as to cover the semiconductor film 15.

  After forming the second insulating film 16, as shown in FIG. 4B, the second insulating film 16 in the second region 10-2 and the third region 10-3 and the first insulating film in the third region 10-3 And 14 are selectively removed to form a connection hole H. The connection holes H are formed by using, for example, dry etching. At this time, the semiconductor film 15 in the second region 10-2 is exposed to dry etching, and the low resistance region 15b-2 is formed in the second region 10-2. The semiconductor film 15 of the low resistance region 15b-2 is formed to have a thickness t2.

  After the connection holes H are formed, a conductive film 17A made of, for example, a metal material is formed on the entire surface of the substrate 11. Subsequently, photoresists Pr1, Pr2 and Pr3 having a predetermined pattern are formed on the conductive film 17A (FIG. 4C). The photoresist Pr1 is for forming the gate electrode 17 and the second insulating film 16 of the transistor Tr. The photoresist Pr2 is for forming the gate wiring 17W of the contact portion 10 and the second insulating film 16 (first region 10-1). The photoresist Pr3 is for forming the gate wiring 17W and the second insulating film 16 in the region other than the contact portion 10.

  The conductive film 17A and the second insulating film 16 are continuously patterned using the photoresists Pr1, Pr2 and Pr3 (FIGS. 5A and 5B). As shown in FIG. 5A, first, the conductive film 17A is patterned by dry etching to form the gate electrode 17 and the gate wiring 17W. In this embodiment, at this time, since the semiconductor film 15 in the first region 10-1 is covered by the second insulating film 16, the semiconductor film 15 is not exposed to dry etching. Therefore, the semiconductor film 15 in the first region 10-1 is not reduced in thickness, and exists with a predetermined thickness.

  After forming the gate electrode 17 and the gate wiring 17W, patterning of the second insulating film 16 is subsequently performed (FIG. 5B). Thereby, the second insulating film 16 having the same shape as the gate electrode 17 in plan view, the second insulating film 16 of the first region 10-1 and the second insulating film 16 having the same shape as the gate wiring 17W in plan view Is formed. At this time, the region of the semiconductor film 15 exposed from the second insulating film 16 is reduced in resistance by dry etching, and the low resistance region 15b-1 and the upper electrode 15C of the storage capacitance Cs are formed. In this dry etching, over-etching is performed so that the thickness t1 of the semiconductor film 15 in the low resistance region 15b-1 is smaller than the thickness t2 of the semiconductor film 15 in the low resistance region 15b-2. Wet switching may be performed instead of dry etching.

  Thereafter, a metal oxide film 18 and an interlayer insulating film 19 are formed on the entire surface of the substrate 11. Finally, source / drain electrodes 21 are formed on the interlayer insulating film 19 to complete the semiconductor device 1 shown in FIG.

[Action, effect]
In the semiconductor device 1 of the present embodiment, when the on voltage higher than the threshold voltage is applied to the gate electrode 17, the channel region 15a of the semiconductor film 15 is activated. Thereby, a current flows between the pair of low resistance regions 15b. Accordingly, in the contact portion 10, a current flows from the semiconductor film 15 to the lower electrode 13 via the gate wiring 17W, and the charge is held in the holding capacitance Cs.

  In the semiconductor device 1 of the present embodiment, since the first region 10-1 having the second insulating film 16 is provided on the semiconductor film 15 in the contact portion 10, when forming the upper layer than the semiconductor film 15. Of the semiconductor film 15 is suppressed. Hereinafter, this will be described using Comparative Example 1.

  FIG. 6 illustrates a schematic cross-sectional configuration of the semiconductor device (semiconductor device 101) according to the first comparative example. The contact portion (contact portion 100) of the semiconductor device 101 has a second region (second region 100-2) and a third region (third region 100-3) adjacent to each other. In the second region 100-2, the gate wiring 17W and the semiconductor film 15 are in contact, and in the third region 100-3, the gate wiring 17W and the lower electrode 13 are in contact. In the region between the second region 100-2 and the gate electrode 17, the second insulating film 16 on the semiconductor film 15 is removed. That is, the first region (for example, the first region 10-1 in FIG. 2) is not provided in the contact portion 100.

  Such a semiconductor device 101 is formed, for example, as follows (FIGS. 7A to 7C).

  First, in the same manner as described in the semiconductor device 1, the UC film 12, the lower electrode 13, the first insulating film 14, the semiconductor film 15, the second insulating film 16 and the conductive film 17A are formed on the substrate 11.

  Next, on the conductive film 17A, photoresists Pr1, Pr102 and Pr3 having a predetermined pattern are formed (FIG. 7A). The photoresist Pr102 is for forming the gate wiring 17W of the contact portion 100. The conductive film 17A and the second insulating film 16 are patterned using the photoresists Pr1, Pr102 and Pr3 (FIGS. 7B and 7C).

  When the conductive film 17A is etched, in the semiconductor device 101 in which the first region is not provided, as shown in FIG. 7B, the region adjacent to the second region 100-2 (opposite to the third region 100-3) The semiconductor film 15 in the region adjacent to the side is exposed from the second insulating film 16 (exposed region 15d). The semiconductor film 15 in the exposed region 15 d is not protected by the second insulating film 16 and is exposed to etching.

  FIG. 8 shows the configuration in the vicinity of the contact portion 100 formed in this manner. FIG. 8A shows a plan configuration of the contact portion 100 and the exposed region 15d, and FIG. 8B shows a cross-sectional configuration thereof. As described above, the semiconductor film 15 in the exposed region 15 d may be reduced in thickness and may disappear. When the semiconductor film 15 in the exposed region 15d is reduced or disappears, a current flows while avoiding the exposed region 15d, so that the resistance of the semiconductor film 15 is increased and the connection between the semiconductor film 15 and the lower electrode 13 becomes unstable. Become.

  On the other hand, in the semiconductor device 1, since the first region 10-1 is provided in the contact portion 10, the exposed region (for example, the exposed region 15 d in FIG. 8) is not formed in the semiconductor film 15. Is protected by the second insulating film 16. As a result, film reduction and disappearance of the semiconductor film 15 are suppressed, and the in-plane uniformity of the semiconductor film 15 is maintained. As a result, the semiconductor film 15 and the lower electrode 13 are connected electrically stably. Therefore, the thin semiconductor film 15 can realize excellent transistor characteristics and high productivity, and electrically and stably connect the semiconductor film 15 and the lower electrode 13.

  Further, by providing the first region 10-1 in the contact portion 10, the connection hole H can be made smaller. This will be described below.

FIG. 9A shows one step of manufacturing the semiconductor device 1 (step of FIG. 5A), and FIG. 9B shows a step corresponding to FIG. 9A of manufacturing the semiconductor device 101. (Step of FIG. 7B). In this step, the end E100 (the end on the transistor Tr side) of the photoresist Pr102 is disposed away from the end E16 (the end on the holding capacitance Cs side) of the second insulating film 16 (FIG. 9B). Therefore, it is necessary to secure a certain distance between the end E16 of the second insulating film 16 and the end E100 of the photoresist Pr102, and it is difficult to reduce the length L2 _{+ 3} of the connection hole H. .

On the other hand, since the end E of the photoresist Pr2 is provided at a position overlapping the second insulating film 16 in plan view, the distance between the end E of the photoresist Pr2 and the end of the second insulating film 16 is secured. There is no need. Therefore, the length L _{2 +3} can be reduced and the connection hole H can be narrowed. As a result, the area occupied by the contact portion 10 can be reduced, and the definition can be increased.

  Furthermore, in the semiconductor film 15 of the semiconductor device 1, the thickness t1 of the low resistance region 15b-1 is smaller than the thickness t2 of the second region 10-2 (the low resistance region 15b-2). Carriers can be sufficiently diffused from 10-2 to the first region 10-1, and diffusion of carriers from the low resistance region 15b-1 to the channel region 15a can be suppressed. Hereinafter, this will be described using Comparative Example 2.

  FIG. 10 schematically illustrates the cross-sectional configuration of the main part of the semiconductor device (semiconductor device 102) according to the second comparative example. Since the first region 10-1 is provided in the semiconductor device 102, film reduction, disappearance, and the like of the semiconductor film 15 can be suppressed. The semiconductor film 15 has a low resistance region 15 b-1 between the channel region 15 a and the first region 10-1 and a low resistance region 15 b-2 disposed in the second region 10-2. Resistance regions 15b-1 and 15b-2 have the same thickness (thickness t).

  FIG. 11 shows one process of manufacturing the semiconductor device 102. The semiconductor device 102 may adjust the etching of the semiconductor film 15 (the low resistance region 15b-1) when patterning the second insulating film 16 using the photoresists Pr1, Pr2, and Pr3. By preventing excessive etching, the semiconductor film 15 of the low resistance region 15b-1 is formed with the same thickness t as the semiconductor film 15 of the second region 10-2 (low resistance region 15b-2). .

  The semiconductor film 15 in the first region 10-1 functions as a conductor by carrier diffusion from the low resistance region 15b-1 and the second region 10-2 adjacent to each other. In the semiconductor device 102, as described above, the semiconductor films 15 of the low resistance region 15b-1 and the second region 10-2 are formed to have the same thickness t. Therefore, if carriers spread from the second region 10-2 to the adjacent first region 10-1 with the diffusion distance ΔL, the low resistance region 15b-1 to the adjacent first region 10-1 and the channel region 15a. The carriers spread at the same diffusion distance (diffusion distance ΔL) (FIG. 10).

  As the carrier diffusion distance ΔL is larger, carriers are sufficiently spread from the low resistance region 15b-1 and the second region 10-2, and the semiconductor film 15 in the first region 10-1 stably functions as a conductor. However, since carriers are also diffused from the low resistance region 15b-1 to the channel region 15a, if the carrier diffusion distance ΔL is large, the TFT characteristics of the transistor Tr may be affected. For example, TFT characteristics tend to be unstable.

  On the other hand, in the present embodiment, the thickness t1 of the semiconductor film 15 in the low resistance region 15b-1 is smaller than the thickness t2 of the semiconductor film 15 in the second region 10-2 (the low resistance region 15b-2). ing. Therefore, as shown in FIG. 12, the low resistance region 15b-1 to the first region 10-1 and the channel region are lower than the diffusion distance ΔL2 of the carriers from the second region 10-2 to the first region 10-1. The diffusion distance (diffusion distance ΔL1) of carriers to 15a is shortened. Therefore, the conductivity of the semiconductor film 15 of the first region 10-1 is sufficiently ensured by the diffusion of the carriers from the second region 10-2 (diffusion distance ΔL2), and the low resistance region 15b-1 to the channel region 15a. Diffusion of carriers to the substrate (diffusion distance ΔL1) is suppressed. Therefore, the stability of the contact portion 10 can be enhanced, and the TFT characteristics of the transistor Tr can be stably maintained.

  Further, by suppressing the diffusion of carriers into the channel region 15a, even if the channel length of the transistor Tr is shortened, the TFT characteristics are stably maintained. Therefore, it is possible to increase the definition.

  As described above, in the present embodiment, since the second insulating film 16 is provided between the gate wiring 17W in the first region 10-1 and the semiconductor film 15, the reduction of the film thickness of the semiconductor film 15 or the like is suppressed. The semiconductor film 15 and the lower electrode 13 can be stably connected. Thus, the stability of the contact portion 10 can be enhanced.

  For example, when the semiconductor device 1 is applied to a display device (display device 2A in FIG. 14 described later), the increase in resistance of the contact portion 10 can be suppressed, so that voltage drop, signal writing failure to pixels, gradation failure, and the like can be prevented. Can. Thus, the display quality of the display device can be improved.

  Further, by providing the first region 10-1 in the contact portion 10, the connection hole H can be made smaller. As a result, the area occupied by the contact portion 10 can be reduced, and the definition can be increased.

  Furthermore, since the thickness t1 of the semiconductor film 15 in the low resistance region 15b-1 is made smaller than the thickness t2 of the semiconductor film 15 in the second region 10-2, the second region 10-2 to the first region 10-1 can sufficiently diffuse carriers and can suppress diffusion of carriers from the low resistance region 15b-1 to the channel region 15a. Thus, the stability of the contact portion 10 can be enhanced, and the characteristics of the transistor Tr can be maintained.

  Further, by suppressing the diffusion of carriers from the low resistance region 15b-1 to the channel region 15a, the channel length of the transistor Tr can be shortened. This makes it possible to further increase the definition.

<Modification>
FIG. 13 schematically illustrates the cross-sectional configuration of the contact portion 10 according to a modification of the above embodiment. As described above, another semiconductor film (semiconductor film 25, second semiconductor film) is provided between the semiconductor film 15 in the first region 10-1 and the second region 10-2 and the first insulating film 14. You may That is, semiconductor films 15 and 25 having a laminated structure may be provided in the first region 10-1 and the second region 10-2. The thickness t2 of the semiconductor film (semiconductor films 15 and 25) in the second region 10-2 is the sum of the thickness of the semiconductor film 15 and the thickness of the semiconductor film 25.

  The semiconductor film 25 may be laminated on part of the semiconductor film 15 in the low resistance region 15b-1. For the semiconductor film 25, the same material as the semiconductor film 15 can be used. For example, the semiconductor film 25 has an oxygen concentration lower than that of the semiconductor film 15 in the first region 10-1, and the electric resistance of the semiconductor film 25 is the same as that of the semiconductor film 15 in the first region 10-1. It is lower than the electrical resistance. Alternatively, the electrical resistance of the semiconductor film 25 may be approximately the same as the electrical resistance of the semiconductor film 15 in the first region 10-1.

  By providing the semiconductor films 15 and 25 having a stacked structure in the first region 10-1, the electrical resistance of the semiconductor films 15 and 25 in the first region 10-1 can be reduced. Thus, the stability of the contact portion 10 can be further enhanced.

Application Example 1
The semiconductor device 1 described in the above-described embodiment and modification can be used as a drive circuit of, for example, a display device (display device 2A of FIG. 14 described later) and an imaging device (imaging device 2B of FIG. .

  FIG. 14 shows a functional block configuration of the display device 2A. The display device 2A displays a video signal input from the outside or a video signal generated internally as a video, and is applied to, for example, a liquid crystal display as well as the organic EL display described above. The display device 2A includes, for example, a timing control unit 31, a signal processing unit 32, a drive unit 33, and a display pixel unit 34.

  The timing control unit 31 has a timing generator that generates various timing signals (control signals), and performs drive control of the signal processing unit 32 and the like based on these various timing signals. The signal processing unit 32 performs, for example, predetermined correction on a digital video signal input from the outside, and outputs a video signal obtained thereby to the driving unit 33. The drive unit 33 includes, for example, a scanning line drive circuit, a signal line drive circuit, and the like, and drives each pixel of the display pixel unit 34 via various control lines. The display pixel unit 34 includes, for example, a display element such as an organic EL element or a liquid crystal display element, and a pixel circuit for driving the display element pixel by pixel. Among them, for example, the above-described semiconductor device 1 is used for various circuits which constitute a part of the drive unit 33 or the display pixel unit 34.

  FIG. 15 shows a functional block configuration of the imaging device 2B. The imaging device 2B is, for example, a solid-state imaging device that acquires an image as an electric signal, and is configured of, for example, a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) image sensor. The imaging device 2B includes, for example, a timing control unit 35, a drive unit 36, an imaging pixel unit 37, and a signal processing unit 38.

  The timing control unit 35 has a timing generator that generates various timing signals (control signals), and performs drive control of the driving unit 36 based on these various timing signals. The driving unit 36 includes, for example, a row selection circuit, an AD conversion circuit, a horizontal transfer scanning circuit, and the like, and performs driving for reading out a signal from each pixel of the imaging pixel unit 37 via various control lines. The imaging pixel unit 37 includes, for example, an imaging device (photoelectric conversion device) such as a photodiode and a pixel circuit for reading out a signal. The signal processing unit 38 performs various signal processing on the signal obtained from the imaging pixel unit 37. Among them, for example, the above-described semiconductor device 1 is used for various circuits which constitute a part of the drive unit 36 or the imaging pixel unit 37.

<Example of electronic device>
The display device 2A, the imaging device 2B, etc. can be used for various types of electronic devices. FIG. 16 shows a functional block configuration of the electronic device 3. Examples of the electronic device 3 include a television device, a personal computer (PC), a smartphone, a tablet PC, a mobile phone, a digital still camera, a digital video camera, and the like.

  The electronic device 3 includes, for example, the display device 2A (or the imaging device 2B) described above and an interface unit 40. The interface unit 40 is an input unit to which various signals and power supplies are input from the outside. The interface unit 40 may also include a user interface such as, for example, a touch panel, a keyboard, or an operation button.

  As mentioned above, although an embodiment was mentioned and explained, this art is not limited to the above-mentioned embodiment, and various modification is possible. For example, the material and thickness of each layer described in the above embodiment are not limited to those listed, and other materials and thicknesses may be used.

  Further, in the above embodiment, the case where the contact portion 10 connects the transistor Tr and the storage capacitance Cs has been described as an example, but the contact portion 10 can also be applied between other elements. .

  Furthermore, although FIG. 2 etc. showed the case where thickness t1, t2 of semiconductor film 15 of low resistance field 15b-1 and the 2nd field 10-2 is constant, low resistance field 15b-1 and the 2nd field 10 The thicknesses t1 and t2 of the semiconductor film 15 of −2 may be changed. For example, the thickness t1 of the semiconductor film 15 of the low resistance region 15b-1 is larger at both ends than at the center. The thickness of at least a part of the semiconductor film 15 in the low resistance region 15b-1 may be smaller than the thickness of the semiconductor film 15 in the second region 10-2.

  The effects described in the above-described embodiment and the like are examples, and the effects of the present disclosure may be other effects or may further include other effects.

The present technology can also be configured as follows.
(1)
A substrate in which a first region, a second region, and a third region are provided in this order along a predetermined direction,
First wiring provided on the first area, the second area, and the third area on the substrate;
It has a channel region of a transistor and a low resistance region provided between the channel region and the first region, and is provided between the first wiring and the substrate in the first region. And a semiconductor film in contact with the first wiring in the second region,
A second wire provided at a position closer to the substrate than the semiconductor film and in contact with the first wire in the third region;
An insulating film provided between the first wiring of the first region and the semiconductor film;
In the semiconductor film, a thickness of the low resistance region is smaller than a thickness of the second region.
(2)
The semiconductor device according to (1), wherein the transistor includes the semiconductor film, a gate insulating film, and a gate electrode in this order on the substrate.
(3)
The gate insulating film includes the same constituent material as the insulating film and has the same thickness as the insulating film.
The semiconductor device according to (2), wherein the gate electrode contains the same constituent material as the first wiring and has the same thickness as the first wiring.
(4)
The semiconductor device according to (3), wherein the low resistance region and the second region of the semiconductor film are exposed from the insulating film and the gate insulating film.
(5)
Furthermore, it has a storage capacity,
The semiconductor device according to any one of (1) to (4), wherein the second wiring constitutes one electrode of the storage capacitor.
(6)
The semiconductor device according to any one of (1) to (5), wherein a length of the first region along the predetermined direction is 2 μm or less.
(7)
The semiconductor device according to any one of (1) to (6), wherein the semiconductor film contains an oxide semiconductor material.
(8)
The thickness of the semiconductor film is 60 nm or less. The semiconductor device according to any one of (1) to (7).
(9)
The semiconductor device according to any one of (1) to (8), wherein the semiconductor film has the low resistance region in a region adjacent to the first region.
(10)
The semiconductor device according to any one of (1) to (9), wherein the semiconductor film has a stacked structure in the first region and the second region.
(11)
A display element and a semiconductor device for driving the display element;
The semiconductor device is
A substrate in which a first region, a second region, and a third region are provided in this order along a predetermined direction,
First wiring provided on the first area, the second area, and the third area on the substrate;
It has a channel region of a transistor and a low resistance region provided between the channel region and the first region, and is provided between the first wiring and the substrate in the first region. And a semiconductor film in contact with the first wiring in the second region,
A second wire provided at a position closer to the substrate than the semiconductor film and in contact with the first wire in the third region;
An insulating film provided between the first wiring of the first region and the semiconductor film;
In the semiconductor film, a thickness of the low resistance region is smaller than a thickness of the second region.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, Tr ... Transistor, Cs ... Storage capacity 10 ... Contact part 10-1 ... 1st area | region 10-2 ... 2nd area | region 10-3 ... 3rd area | region 11 ... board | substrate, 12, 12A , 12B: UC film, 13: lower electrode, 14: first insulating film, 15: semiconductor film, 15a: channel region, 15b, 15b-1, 15b-2: low resistance region, 15C: upper electrode, 16: first 2 insulating film 17 gate electrode 17 W gate wiring 18 metal oxide film 19, 19A, 19B, 19C interlayer insulating film 21 source / drain electrode 2A display device 2B imaging device 3 ... electronic device 31, 35 ... timing control unit 32, 32 ... signal processing unit, 33, 36 ... driving unit, 34 ... display pixel unit, 37 ... imaging pixel unit, 40 ... interface unit, t1, t2 ... thickness.

Claims (11)

A substrate in which a first region, a second region, and a third region are provided in this order along a predetermined direction,
First wiring provided on the first area, the second area, and the third area on the substrate;
It has a channel region of a transistor and a low resistance region provided between the channel region and the first region, and is provided between the first wiring and the substrate in the first region. And a semiconductor film in contact with the first wiring in the second region,
A second wire provided at a position closer to the substrate than the semiconductor film and in contact with the first wire in the third region;
An insulating film provided between the first wiring of the first region and the semiconductor film;
In the semiconductor film, a thickness of the low resistance region is smaller than a thickness of the second region. The semiconductor device according to claim 1, wherein the transistor has the semiconductor film, a gate insulating film, and a gate electrode in this order on the substrate. The gate insulating film includes the same constituent material as the insulating film and has the same thickness as the insulating film.
The semiconductor device according to claim 2, wherein the gate electrode includes the same constituent material as the first wiring and has the same thickness as the first wiring. The semiconductor device according to claim 3, wherein the low resistance region and the second region of the semiconductor film are exposed from the insulating film and the gate insulating film. Furthermore, it has a storage capacity,
The semiconductor device according to claim 1, wherein the second wiring constitutes one electrode of the storage capacitor. The semiconductor device according to claim 1, wherein a length of the first region along the predetermined direction is 2 μm or less. The semiconductor device according to claim 1, wherein the semiconductor film contains an oxide semiconductor material. The semiconductor device according to claim 1, wherein a thickness of the semiconductor film is 60 nm or less. The semiconductor device according to claim 1, wherein the semiconductor film includes the low resistance region in a region adjacent to the first region. The semiconductor device according to claim 1, wherein the semiconductor film has a stacked structure in the first region and the second region. A display element and a semiconductor device for driving the display element;
The semiconductor device is
A substrate in which a first region, a second region, and a third region are provided in this order along a predetermined direction,
First wiring provided on the first area, the second area, and the third area on the substrate;
It has a channel region of a transistor and a low resistance region provided between the channel region and the first region, and is provided between the first wiring and the substrate in the first region. And a semiconductor film in contact with the first wiring in the second region,
A second wire provided at a position closer to the substrate than the semiconductor film and in contact with the first wire in the third region;
An insulating film provided between the first wiring of the first region and the semiconductor film;
In the semiconductor film, a thickness of the low resistance region is smaller than a thickness of the second region.

Images