JP2019024063A - Thin-film wiring board - Google Patents

Abstract

To prevent short circuit and migration between wiring and alleviate thermal stress applied to an end of a thin-film wiring to prevent the occurrence of cracks and film peeling.SOLUTION: A thin-film wiring board comprises: an insulating substrate 1; and a thin-film multilayer wiring 2 consisting of three layers: an adhesion layer 3; a barrier layer 4; and a main conductor layer 5, which are laminated in order on the insulating substrate. In top view, the position of a top face end edge 51 of the main conductor layer is inside a top face end edge 41 of the barrier layer; the position of the top face end edge 41 of the barrier layer is inside a top face end edge 31 of the adhesion layer; the position of the top face end edge 31 of the adhesion layer is inside an under surface end edge 21 of the adhesion layer. The thin-film wiring board preferably has concave parts 34, 44, 54 that become concave in vertical sectional view with respect to virtual line segments L1, L2, L3 connecting the top face end edges of the layers.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a thin film wiring board in which a thin film multilayer wiring is formed on an insulating substrate.

  As described in Patent Document 1, there is a technique for forming a thin film multilayer wiring including an adhesive layer, a barrier layer, and a main conductor layer on an insulating substrate.

2. Description of the Related Art Conventionally, a wiring board in an electric circuit board, a semiconductor element housing package or the like has its circuit wiring formed by a thick film forming technique such as a Mo-Mn method.
In this Mo-Mn method, an organic solvent or solvent is added to a metal powder composed of a high melting point metal such as tungsten (W), molybdenum (Mo), manganese (Mn), etc. In this method, a predetermined pattern as circuit wiring is printed and applied to the outer surface of the sintered ceramic body by screen printing, and then fired in a reducing atmosphere to sinter and integrate the refractory metal and the ceramic body.

  However, when the circuit wiring is formed using this Mo-Mn method, the circuit wiring is formed by screen printing a metal paste, so that it is difficult to make the circuit wiring finer. It had the disadvantage that it was not possible.

Therefore, in order to eliminate the above-mentioned drawbacks, instead of forming the circuit wiring by the conventional thick film forming technique, a thin film wiring board formed by using a thin film forming technique that can be miniaturized, that is, Ti, Cr on the insulating substrate. Etc., a barrier layer made of Pd, Pt, Ag, Cu, etc., and a main conductor layer made of gold (Au) by a thin film forming technique such as an ion plating method, a sputtering method, a vapor deposition method, or a plating method. A thin film wiring board has been proposed in which these layers are sequentially stacked and then these layers are formed into a predetermined pattern by photolithography to form circuit wiring.
In the thin film wiring board, the adhesive layer acts to firmly bond the circuit wiring to the insulating substrate, and the barrier layer suppresses mutual diffusion between the adhesive layer and the main conductor layer and firmly fixes the main conductor layer to the adhesive layer. Has the effect of bonding.

Although the technology for forming the above-described thin film multilayer wiring has made it possible to increase the density of circuit wiring, the narrowing of the wiring gap is also progressing accordingly.
As a result, solder at the time of mounting electronic components flows into the gap between the wires, causing a short circuit, or heating at the time of mounting after wiring formation increases the thermal stress applied to the end of the thin film wiring, causing cracks and There was a concern of film peeling.

JP-A 63-78591

  The present invention has been devised in view of the above conventional problems, and its purpose is to suppress short-circuiting and migration between wirings in a thin-film wiring board in which a thin-film multilayer wiring is formed on an insulating substrate. Furthermore, the thermal stress applied to the end portion of the thin film wiring is relaxed to suppress the occurrence of cracks and film peeling.

  The present invention provides a thin-film wiring board having an insulating substrate and a thin-film multilayer wiring composed of these three layers in which an adhesive layer, a barrier layer, and a main conductor layer are sequentially laminated on the insulating substrate. The position of the upper surface edge of the barrier layer is on the inner side of the upper surface edge of the barrier layer, the position of the upper surface edge of the barrier layer is on the inner side of the upper surface edge of the adhesive layer, and the upper surface edge of the adhesive layer Is located inside the lower edge of the adhesive layer.

  In the thin film wiring board of the present invention, preferably, the distance between the upper surface edge of the main conductor layer and the upper surface edge of the barrier layer is such that the upper surface edge of the barrier layer and the upper surface edge of the adhesive layer are It is characterized by being longer than the distance between.

  The thin film wiring board according to the present invention preferably has a concave portion in a side view of the main conductor layer, the barrier layer, and the adhesive layer that is concave in a longitudinal sectional view with respect to a virtual line segment connecting the upper edge of each layer. It is characterized by having.

  The thin film wiring board of the present invention is preferably characterized in that the recess is provided on the entire side surface of the barrier layer and the entire side surface of the adhesive layer.

  The thin film wiring board of the present invention is preferably characterized in that the depth of the concave portion of the barrier layer from the virtual line segment is deeper than the depth of the concave portion of the adhesive layer from the virtual line segment.

  The thin film wiring board of the present invention preferably has a virtual line segment connecting the upper surface edge of the main conductor layer and the upper surface edge of the barrier layer, and the upper surface edge of the barrier layer and the An angle formed by the virtual line segment connecting the upper edge of the adhesive layer on the inner side of the wiring is an obtuse angle.

  In the thin film wiring board of the present invention, preferably, the insulating substrate has a lower step surface that is lowered with respect to an upper step surface to which the lower surface of the adhesive layer is bonded, and the lower surface edge of the adhesive layer is viewed from above. It exists in the edge of the said upper stage surface, and exists inside the edge of the said lower stage surface which adjoins the said upper stage surface, It is characterized by the above-mentioned.

  In the thin film wiring board of the present invention, preferably, a side surface connecting the upper surface and the lower surface of the insulating substrate passes from the upper surface edge of the adhesive layer to the lower surface edge of the adhesive layer in a longitudinal sectional view. It is characterized by being on a virtual half line.

  According to the thin film wiring board of the present invention, in the thin film wiring board in which the thin film multilayer wiring is formed on the insulating substrate, the short circuit and the migration between the wirings are suppressed, and further, the thermal stress applied to the end of the thin film wiring is reduced. Suppresses the occurrence of cracks and film peeling.

It is a longitudinal section showing a thin film wiring board concerning one embodiment of the present invention. It is a longitudinal cross-sectional view which shows the thin film wiring board which concerns on other one Embodiment of this invention. It is a longitudinal cross-sectional view which shows the thin film wiring board which concerns on other one Embodiment of this invention. It is a longitudinal cross-sectional view which shows the thin film wiring board which concerns on other one Embodiment of this invention. It is a longitudinal cross-sectional view which shows the wiring formation process of a thin film wiring board concerning embodiment of this invention. It is a schematic diagram which shows the mode of the etching by perpendicular | vertical sputtering in reactive ion etching. It is a schematic diagram which shows the mode of the etching by sputtering which raised the scattering probability in reactive ion etching.

  An embodiment of the present invention will be described below with reference to the drawings. The following is one embodiment of the present invention and does not limit the present invention.

(Laminated structure)
As shown in FIGS. 1 to 4, a thin film wiring board according to an embodiment of the present invention includes an insulating substrate 1, and these three layers in which an adhesive layer 3, a barrier layer 4, and a main conductor layer 5 are sequentially laminated on the insulating substrate 1. And a thin film multilayer wiring 2 made of
The insulating substrate 1 includes an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body, and the like. The insulating substrate 1 is, for example, an aluminum oxide sintered body. In the case of a body, by adding a suitable organic solvent and solvent to the raw material powder such as alumina, magnesia, calcia, silica, etc. and mixing it into a mud, this is adopted by adopting the doctor blade method, calender roll method, etc. The ceramic green sheet (ceramic green sheet) is formed, and then the ceramic green sheet is subjected to an appropriate punching process to obtain a predetermined shape and fired at a high temperature (about 1600 ° C.).

  A thin film multilayer wiring 2 is deposited on the upper surface of the insulating substrate 1 by a thin film formation technique. The thin film multilayer wiring 2 has a three-layer structure of an adhesive layer 3, a barrier layer 4, and a main conductor layer 5. Yes.

  The adhesive layer 3 constituting the thin film multilayer wiring 2 is made of Ti, Cr or the like and is deposited on the insulating substrate 1 by a thin film forming technique such as a vapor deposition method or an ion plating method.

  The adhesive layer 3 has an effect of increasing the adhesive strength between the insulating substrate 1 and the thin film multilayer wiring 2, and if the thickness is less than 100 angstroms, it is difficult to firmly adhere the thin film multilayer wiring 2 to the insulating substrate 1. In addition, when it exceeds 10000 angstroms, the adhesive strength between the insulating substrate 1 and the adhesive layer 3 tends to decrease due to internal stress when the adhesive layer 3 is applied by the thin film formation technique. The thickness is preferably in the range of 300 to 2000 angstroms, and more preferably in the range of 500 to 1500 angstroms.

  Further, a barrier layer 4 is deposited on the upper surface of the adhesive layer 3, and the barrier layer 4 improves the adhesion between the adhesive layer 3 and the main conductor layer 5, and the adhesive layer 3 and the main conductor layer 5 are mutually connected. It has the effect of preventing diffusion.

  The barrier layer 4 is made of Pd, Pt, Ag, Cu or the like, and is deposited on the upper surface of the adhesive layer 3 by a thin film forming technique such as vapor deposition, ion plating, or sputtering.

  When the thickness of the barrier layer 4 is less than 500 angstroms, the adhesion between the adhesive layer 3 and the main conductor layer 5 is lowered and the mutual diffusion between the adhesive layer 3 and the main conductor layer 5 can be effectively prevented. When the thickness exceeds 10,000 angstroms, the adhesive strength between the adhesive layer 3 and the barrier layer 4 tends to decrease due to internal stress when the barrier layer 4 is deposited by the thin film formation technique. The thickness is preferably in the range of 800 to 5000 angstroms, and more preferably 1000 to 3000 angstroms.

  A main conductor layer 5 is deposited on the upper surface of the barrier layer 4 by a thin film forming technique such as a vapor deposition method, an ion plating method, a sputtering method, or a plating method. The main conductor layer 5 is mainly used as a passage for conducting electricity. Has an effect.

  The main conductor layer 5 is made of gold (Au) having a very small conduction resistance, and if the thickness is less than 1 μm, the conduction resistance of the thin film multilayer wiring 2 tends to be high and tends to be unsuitable as a thin film wiring board. The thickness is preferably 1 μm or more, more preferably 4 μm or more.

  The thin-film multilayer wiring 2 formed on the insulating substrate 1 is made finer because the adhesive layer 3, the barrier layer 4 and the main conductor layer 5 constituting the thin-film multilayer wiring 2 are formed by a thin-film formation technique. It is possible to achieve high density of the thin film multilayer wiring 2.

(Wiring side edge structure)
In the thin film wiring substrate according to the embodiment of the present invention, the side edge portion of the thin film multilayer wiring 2 is formed in the following structure in order to suppress short circuit and migration between the wirings.

In the thin film wiring substrate shown in FIGS. 1 to 4, the position 51 of the upper surface edge of the main conductor layer 5 is inside the upper surface edge 41 of the barrier layer 4 when viewed from above (arrow A). 4 is located on the inner side of the upper surface edge 31 of the adhesive layer 3, and the position of the upper surface edge 31 of the adhesive layer 3 is located on the inner side of the lower surface edge 21 of the adhesive layer 3.
The side surface 52 of the main conductor layer 5 is inclined, and the position of the lower surface edge of the main conductor layer 5 coincides with the upper surface edge 41 of the barrier layer 4.
The side surface 42 of the barrier layer 4 is inclined, and the position of the lower surface edge of the barrier layer 4 coincides with the upper surface edge 31 of the adhesive layer 3.
The side surface 32 of the adhesive layer 3 is inclined, and the position of the lower surface edge of the adhesive layer 3 coincides with the edge 21 of the upper stage surface 20 of the insulating substrate 1.
According to such a structure, when an element or the like is mounted on the main conductor layer 5, the solder wraps around the side surface of the wiring 2, but the side surface length is long because the side surface of the main conductor layer 5 is inclined. 2 short circuit and migration are suppressed.
By being inclined, the distance between the upper ends of the adjacent wirings 2 and 2 is increased, and the occurrence of a solder short during mounting is suppressed.
When the area of the interface between the main conductor layer 5 and the barrier layer 4 is compared with the area of the interface between the barrier layer 4 and the adhesive layer 3, the area of the interface between the barrier layer 4 and the adhesive layer 3 is larger. A high diffusion suppressing effect can be obtained.

Further, as shown in FIG. 1, a distance 53 between the upper surface edge 51 of the main conductor layer 5 and the upper surface edge 41 of the barrier layer 4 is such that the upper surface edge 41 of the barrier layer 4 and the upper surface edge 31 of the adhesive layer 3. It is preferable that it is longer than the distance 43 between.
According to such a structure, when an element or the like is mounted on the main conductor layer 5, if the solder wraps around the side surface of the wiring 2, more solder can be held on the side surface of the main conductor layer 5 having high solder wettability. Since it is repelled on the side surface of the barrier layer 4 having no wettability, wiring short-circuiting and migration are suppressed.

In addition, as shown in FIG. 2, on the side surfaces of the main conductor layer 5, the barrier layer 4 and the adhesive layer 3, the imaginary line segments L1 and L2 connecting the upper surface edges of the respective layers are provided with concave portions 44 which are concave in a longitudinal sectional view. 54 is preferred. The virtual line segment L1 is a virtual line segment connecting the two end edges 51 and 41. The virtual line segment L2 is a virtual line segment that connects the two end edges 41 and 31. The virtual line segment L3 is a virtual line segment connecting the two end edges 31 and 21.
According to such a structure, since the recesses 44 and 54 having a large depth are present, the length of the side surface of the wiring 2 is increased, and the shorting and migration of the solder that has entered the side surface are suppressed.
One recess 44 (54) is preferably provided in a side surface of each layer without straddling a plurality of layers. One recess 44 is provided on the side surface of the barrier layer 4, and another recess 54 is provided on the side surface of the main conductor layer 5.
By having such recesses 44 and 54, the vicinity of the wiring edge at the interface between the main conductor layer 5 and the barrier layer 4 becomes thin and easily deforms, so that the stress is relieved and the main conductor layer 5 and the barrier Peeling of the layer 4 is suppressed.

In addition, as shown in FIG. 3, it is preferable that one recess 44 is provided on the entire side surface of the barrier layer 4 and the other recess 34 is provided on the entire side surface of the adhesive layer 3.
Since the side surface length of the wiring 2 is further longer than the structure shown in FIG. 2, it is possible to suppress solder shorting and migration.

Moreover, as shown in FIG. 4, it is preferable that the depth of the recessed part 44 of the barrier layer 4 from the virtual line segment L2 is larger than the depth of the recessed part 34 of the adhesive layer 3 from the virtual line segment L3.
According to such a structure, since the concave portion 44 of the barrier layer 4 having a high solder diffusion preventing function is large, solder short-circuiting and migration can be more effectively suppressed.

Further, as shown in FIG. 1, a virtual line segment L1 connecting the upper surface edge 51 of the main conductor layer 5 and the upper surface edge 41 of the barrier layer 4 and the upper surface edge 41 of the barrier layer 4 are bonded to each other in a longitudinal sectional view. The angle α formed by the virtual line segment L2 connecting the upper surface edge 31 of the layer 3 on the inner side of the wiring 2 is preferably an obtuse angle (an angle greater than 90 degrees and smaller than 180 degrees).
According to such a structure, since the side length of the main conductor layer 5 is increased, solder shorts can be suppressed and the area of the barrier layer 4 is increased with respect to the solder mounting area, thereby suppressing the diffusion of solder components. it can.

In addition, as shown in FIG. 1, the insulating substrate 1 has a lower step surface 10 that is lowered with respect to the upper step surface 20 to which the lower surface of the adhesive layer 3 is bonded, and the lower surface of the adhesive layer 3 as viewed from above (arrow A). It is preferable that the end edge is located at the end edge 21 of the upper stage surface 20 and is located inside the edge 11 of the lower stage surface 10 adjacent to the upper stage surface 20.
According to such a structure, the stress generated in the thin-film multilayer wiring 2 is relaxed by deforming the step portion (convex portion) of the insulating substrate 1 from the upper step surface 20 to the lower step surface 10, and as a result, the insulating substrate 1 and the thin-film multilayer are relieved. Film peeling between the wiring 2 is suppressed.

Further, as shown in FIG. 1, the side surface 22 that connects the upper surface 20 and the lower surface 10 of the insulating substrate 1 passes from the upper surface edge 31 of the adhesive layer 3 to the lower surface edge 21 of the adhesive layer 3 in a longitudinal sectional view. It is preferable to be on the virtual half line L4.
Moisture easily falls from the side surface 32 of the adhesive layer 3 along the side surface 22 to the lower step surface 10, and does not accumulate on the side edge of the wiring 2. Will improve.

(Production method)
Next, a method for manufacturing the above thin film wiring board will be described.
As described above, the adhesive layer 3, the barrier layer 4, and the main conductor layer 5 are sequentially deposited on the insulating substrate 1 having a predetermined shape by a thin film forming technique (FIGS. 5A and 5B).
Next, a resist mask 6 corresponding to the wiring pattern is formed on the main conductor layer 5 as shown in FIG. 5 (c), and an adjacent region of the portion to be the thin film multilayer wiring 2 is shown in FIG. 5 (d). The adhesive layer 3, the barrier layer 4, the main conductor layer 5, and the surface of the insulating substrate 1 are dry-etched, and then the resist mask 6 is removed as shown in FIG.

In dry etching of FIG. 5D, reactive ion etching (RIE) is applied.
In reactive ion etching, an etching gas is subjected to an electromagnetic wave or the like in a reaction chamber to form plasma, and at the same time, a high frequency voltage is applied to a cathode on which a sample is placed. Then, a self-bias potential is generated between the sample and the plasma, and ion species and radical species in the plasma are accelerated toward the sample and collide with each other. At that time, sputtering by ions and the chemical reaction of the etching gas occur at the same time, and etching with high accuracy suitable for fine processing can be performed.
Sputtering by ions is highly anisotropic physical etching, chemical reaction of etching gas is isotropic chemical etching, and reactive ion etching is a fine processing technique that combines these.
As the reactive ion etching progresses, the main conductor layer 5, the barrier layer 4, and the adhesive layer 3 are etched in this order. The side surface of the thin-film multilayer wiring 2 is controlled by controlling the anisotropy and isotropic property in the reactive ion etching according to the etching characteristics (reference tables I and II) of the material of the exposed layer according to the progress of the reactive ion etching. Inclination and depression can be formed.

  Since Au or the like constituting the main conductor layer 5 has poor chemical reactivity, it is difficult to form recesses by chemical etching. Therefore, the ions 7 are not perpendicular as shown in FIG. 6, but are incident at an angle inclined with respect to the workpiece by raising the gas pressure of Ar or the like and raising the scattering probability in the plasma as shown in FIG. 7A. Control is performed so that the ratio of the increase is increased (that is, the isotropic property is increased). Then, as shown in FIG. 7 (b), the etching of Au of the main conductor layer 5 wraps under the resist 6 to form an inclined surface and a recess.

When it is desired to form local recesses (44, 54) as shown in FIG. 2, the incidence of Ar ions is increased by increasing the gas pressure (ie, increasing isotropicity) only during a partial time during the etching process. The angle changes and local recesses (44, 54) can be formed.
The above can be applied as a formation method common to all of the main conductor layer 5, the barrier layer 4, and the adhesive layer 3.

Further, since Pt, Pd, etc. constituting the barrier layer 4 undergo a chemical reaction, recesses can be formed even by chemical etching.
After the main conductor layer 5 is physically etched with Ar ions or the like, the gas atmosphere is switched to CF ₄ and changed to chemical etching, so that anisotropic etching is switched to isotropic etching, and concave portions are formed on the side surfaces of the barrier layer 4. Can be formed.

<Specific processing conditions>
Specific examples of processing conditions include C ₃ F ₈ gas, CF ₄ gas, and Ar by IE (double frequency excitation type reactive ion etching apparatus) or ICP (Inductively Coupled Plasma) type RIE. Using a mixed gas of gas (Cl ₂ / C ₃ F ₈ / Ar) and using the resist 6 as a mask, the thin films 3, 4, and 5 are dry-etched to form the thin film multilayer wiring 2. In ICP, pressure = 0.5-5 Pa, source power = 500-1000 W, bias power = 200 W-500 W can be applied.

Ａｕ，Ｐｄはスパッタチング率が大きいので、メカニカルなエッチングが進行しやすい。つまりガス圧を上げて、Ａｒイオンを散乱させ物理エッチングで凹部を形成する方が良い。

Since Au and Pd have a high sputtering rate, mechanical etching tends to proceed. In other words, it is better to increase the gas pressure to scatter Ar ions and form the recesses by physical etching.

Ｐｔは融点の低いフッ化物をつくるので、化学なエッチングで凹部を作るとよい。

Since Pt forms a fluoride having a low melting point, it is preferable to form a recess by chemical etching.

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Thin film multilayer wiring 3 Adhesion layer 4 Barrier layer 5 Main conductor layer 6 Resist mask 34 Recess 44 Recess 54 Recess L1, L2, L3 Virtual line segment α Angle

Claims (8)

In a thin film wiring board having an insulating substrate and a thin film multilayer wiring composed of these three layers in which an adhesive layer, a barrier layer, and a main conductor layer are sequentially laminated on the insulating substrate,
In top view, the position of the upper surface edge of the main conductor layer is inside the upper surface edge of the barrier layer, and the position of the upper surface edge of the barrier layer is inside the upper surface edge of the adhesive layer The thin film wiring board is characterized in that the position of the upper surface edge of the adhesive layer is inside the lower surface edge of the adhesive layer. The distance between the upper surface edge of the main conductor layer and the upper surface edge of the barrier layer is longer than the distance between the upper surface edge of the barrier layer and the upper surface edge of the adhesive layer. The thin film wiring board according to claim 1. The side surfaces of the main conductor layer, the barrier layer, and the adhesive layer have a concave portion that is concave in a longitudinal sectional view with respect to an imaginary line segment that connects the upper edge of each layer. Item 3. The thin film wiring board according to Item 2. 4. The thin film wiring board according to claim 3, wherein the concave portion is provided on the entire side surface of the barrier layer and the entire side surface of the adhesive layer. 5. The thin film wiring board according to claim 3, wherein a depth of the concave portion of the barrier layer from the virtual line segment is deeper than a depth of the concave portion of the adhesive layer from the virtual line segment. In a longitudinal sectional view, a virtual line segment connecting the upper surface edge of the main conductor layer and the upper surface edge of the barrier layer, and a virtual line connecting the upper surface edge of the barrier layer and the upper surface edge of the adhesive layer 6. The thin film wiring substrate according to claim 1, wherein an angle formed between the line segment and the inside of the wiring is an obtuse angle. The insulating substrate has a lower step surface that is lowered with respect to an upper step surface to which the lower surface of the adhesive layer is bonded,
7. The upper surface of the adhesive layer is located on an edge of the upper surface and is located on an inner side of an edge of the lower surface adjacent to the upper surface in a top view. The thin film wiring board according to any one of the above. A side surface connecting the upper surface and the lower surface of the insulating substrate is on a virtual half line that passes from the upper surface edge of the adhesive layer to the lower surface edge of the adhesive layer in a longitudinal sectional view. The thin film wiring board according to claim 7.

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