JP2013110231A - Wiring structure and manufacturing method for wiring structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure which uses two modes occurring in a wiring structure embedded between a first insulating layer and a second insulating layer and discharging from upper and lower corners of wiring as single mode, and has excellent dielectric breakdown resistance.SOLUTION: A wiring structure comprises: a first insulating layer 2; wirings 4' and 4" provided on the first insulating layer 2 and having a copper wiring part 4a composed of copper or copper alloy; a dielectric layer 5 provided on the first insulating layer 2 and extending in a belt like shape along the wirings in a state in which the dielectric layer is in contact with one side surface of the wirings; and a second insulating layer 3 provided on the first insulating layer 2 and coating the wirings and the dielectric layer 5. The dielectric layer 5 has a relative permittivity higher than the first insulating layer 2 and the second insulating layer 3.

Description

  The present invention relates to a wiring structure and a manufacturing method of the wiring structure.

  A multilayer wiring circuit board for mounting a semiconductor element, such as a package board, a wafer level package board, or a silicon interposer board, often uses a wiring structure in which copper wiring is embedded in an insulating layer. As the wiring structure is miniaturized as the number of terminals of the semiconductor element is increased and the pitch of the terminals is reduced, the distance between the wirings is further reduced. For this reason, there is a concern about a decrease in reliability due to dielectric breakdown between wirings.

  For manufacturing a fine multilayer wiring structure, a semi-additive method or a damascene method that can easily produce a fine wiring is often used. In the semi-additive method, a wiring is formed on the upper surface of the lower insulating layer and then covered with an upper insulating layer. In the damascene method, a wiring embedded in a lower insulating layer is formed, and then the upper insulating layer is covered with the wiring. Therefore, in the wiring structure manufactured by these manufacturing methods, the corners of the lower surface or the upper surface of the wiring are formed close to the interface between the lower insulating layer and the upper insulating layer. Electric field concentration tends to occur at the corners of the wiring. For this reason, in these wiring structures in which the corners of the wiring are close to the interface between the upper and lower insulating layers, there is a possibility that a dielectric breakdown in which discharge proceeds from the corner of the wiring along the interface of the upper and lower insulating layers may occur.

  In order to suppress the discharge that proceeds along the interface between the upper and lower insulating layers, a method of extending the interface between the upper and lower insulating layers extending between the wirings has been proposed. In this method, the lower insulating layer exposed between the wirings is dug down. As a result, the interface between the upper and lower insulating layers is extended by the distance that descends and rises the dug depth. For this reason, it is expected that the discharge along the interface is suppressed.

  On the other hand, it is estimated that the above-mentioned dielectric breakdown is related to copper diffusion. For this reason, the proposal which suppresses a dielectric breakdown by covering the outer peripheral surface of a copper wiring with a copper diffusion prevention film is made.

Japanese Patent Laid-Open No. 2008-232828 JP 2010-045456 A JP 2008-215847 A

  As described above, in a wiring structure including a copper wiring manufactured by a semi-additive method or a damascene method, when the wiring structure becomes fine, discharge proceeds from the corner of the wiring where the electric field is concentrated along the interface of the upper and lower insulating layers. There is a risk of dielectric breakdown. For this reason, a multilayer wiring structure having high insulation resistance and a precise reliability test capable of ensuring the insulation resistance are desired.

  The HAST test (Highly-Accelerated Temprature and Humidity Stress Test) is widely adopted as a test for measuring the reliability of a wiring structure against dielectric breakdown. As a result of applying the HAST test to the wiring structure manufactured by the semi-additive method, dielectric breakdown that discharges from the lower corner of the wiring close to the interface along the interface of the upper and lower insulating layers, and adjacent to the upper corner of the wiring far from the interface Dielectric breakdown that discharges through the insulating layer toward the upper corner of the wiring to be connected and two modes of dielectric breakdown were observed.

  It is impossible to predict in advance which of these two modes will break down. For this reason, in the reliability test, two modes of dielectric breakdown events overlap, resulting in a large variation in time until dielectric breakdown, resulting in a problem that the reliability of the wiring structure is lowered. Further, as a result of the overlap of the two modes, the main cause of the deterioration of the insulation resistance cannot be specified, which hinders the improvement of the insulation resistance of the wiring structure.

  According to the HAST test, the conventional wiring structure in which the lower insulating layer exposed between the wirings is dug down to extend the interface between the upper and lower insulating layers is almost the same as the wiring structure without dug-down. It was. Thus, the effect of digging down the lower insulating layer is limited. Moreover, although the conventional wiring structure which coat | covered the outer peripheral surface of the copper wiring with the copper diffusion prevention film has an improvement effect according to a HAST test result, the suppression effect of the dielectric breakdown is not enough.

  The present invention relates to a wiring structure including a copper wiring embedded in an insulating layer, having a high resistance to dielectric breakdown and controlled to discharge only from one of upper and lower corners of the wiring, and its manufacture It aims to provide a method.

  According to one aspect of the present invention for solving the above-described problems, a wiring having a first insulating layer and a copper wiring portion provided on the first insulating layer and made of copper or a copper alloy; A dielectric layer provided on the first insulating layer and having a side surface in contact with the wiring and extending in a strip shape along the wiring; and provided on the first insulating layer, the wiring and the dielectric And a second insulating layer covering the body layer, wherein the dielectric layer has a higher dielectric constant than the first and second insulating layers.

  According to the present invention, there is provided a wiring structure including a copper wiring embedded in an insulating layer, which has a high resistance to dielectric breakdown and is controlled so that discharge proceeds only from one of upper and lower corners of the wiring. Provided.

Plan view of HAST test wiring Cross-sectional view of conventional wiring structure Sectional drawing of the wiring structure of 1st Embodiment of this invention HAST test result of the first embodiment of the present invention Electric field intensity distribution diagram of the first embodiment of the present invention Electric field strength distribution diagram of conventional wiring structure The expanded sectional view of the wiring structure of a 1st embodiment of the present invention. The figure showing Cu diffusion path | route of the wiring structure of this invention Manufacturing process sectional drawing of the wiring structure of 1st Embodiment of this invention (the 1) Manufacturing process sectional drawing of the wiring structure of 1st Embodiment of this invention (the 2) Manufacturing process sectional drawing of the wiring structure of 1st Embodiment of this invention (the 3) Manufacturing process sectional drawing of the wiring structure of 1st Embodiment of this invention (the 4) Sectional drawing of the wiring structure of 2nd Embodiment of this invention Manufacturing process sectional drawing of the wiring structure of 2nd Embodiment of this invention (the 1) Manufacturing process sectional drawing of the wiring structure of 2nd Embodiment of this invention (the 2) Sectional drawing of the wiring structure of 3rd Embodiment of this invention Manufacturing process sectional drawing of the wiring structure of 3rd Embodiment of this invention (the 1) Manufacturing process sectional drawing of the wiring structure of 3rd Embodiment of this invention (the 2) Sectional drawing of the wiring structure of 4th Embodiment of this invention Manufacturing process sectional drawing of the wiring structure of 4th Embodiment of this invention (the 1) Manufacturing process sectional drawing of the wiring structure of 4th Embodiment of this invention (the 2) Manufacturing process sectional drawing of the wiring structure of 4th Embodiment of this invention (the 3)

  Prior to describing the present invention, a conventional wiring structure used for a circuit board and its dielectric breakdown will be described.

  FIG. 1 is a plan view of a HAST test wiring, and shows a planar shape of the wiring subjected to the HAST test. FIG. 2 is a cross-sectional view of a conventional wiring structure, and shows a cross-sectional structure of a wiring manufactured by a semi-additive method. 2 is an enlarged view of a part of the XX ′ cross section of FIG. 1. FIG. 2 (a) shows wiring formed in a rectangular cross section, and FIG. 2 (b) shows wiring upward. A wiring formed by being deformed so that the width is increased is shown.

  Referring to FIG. 1, a HAST test wiring 20 used for the HAST test is composed of two comb-shaped wirings 20 ′ and 20 ″ that mesh with each other. , Connecting portions 20A ′ and 20A ″ extending in parallel to each other, and wirings 4 ′ and 4 ″ extending in a line shape in a direction perpendicular to the connecting portions 20A ′ and 20A ″. These wirings 4 ′ and 4 ”. "Constitutes a comb-tooth portion of each of the comb-like wirings 20 'and 20". Also, the line-like wirings 4' and 4 "are arranged alternately and in parallel to form a line-and-space. The wiring 4 'is connected to the connecting portion 20A' to form a comb-like wiring 20 ', and the wiring 4 "is connected to the connecting portion 20A" to form a comb-like wiring 20 ".

  In the HAST test, a voltage is applied between the comb-like wirings 20 ′ and 20 ″ and the substrate is left in a high-temperature and high-humidity atmosphere, and dielectric breakdown occurs between the wirings 4 ′ and 4 ″ constituting the line and space. The time until is measured.

  Referring to FIG. 2A, in the conventional wiring structure 15, a first insulating layer 2 (lower insulating layer) formed on the substrate 1 and a cross-sectional rectangle formed on the first insulating layer 2. And the second insulating layer 3 (upper insulating layer) formed on the first insulating layer 2 so as to cover the wirings 4 ′ and 4 ″. .

  The upper surface of the first insulating layer 2 is dug down between the wirings 4 ′ and 4 ″ to form a recess 2a. That is, the upper surface of the first insulating layer 2 is parallel to the paper surface of FIG. A groove-like recess 2a extending in the shape of a line and a mesa stripe-like protrusion 2b formed between the recesses 2a are formed in a line-and-space shape. Placed in. Therefore, the inner surface of the recess 2a, that is, the wall surface of the recess 2a connected from the lower corner A ′ to the lower corner A ′ of the wiring 4 ′, the bottom surface of the recess 2a, and the wall surface of the recess 2a connected to the lower corner A ″ of the wiring 4 ″ An interface 21 where the first insulating layer 2 and the second insulating layer are in contact with each other is formed.

  The wirings 4 ′ and 4 ″ include an adhesion layer 4b made of, for example, a titanium film provided in close contact with the upper surface of the first insulating layer 2, and a copper wiring portion 4a made of copper or a copper alloy formed on the adhesion layer 4b. And have.

  In the HAST test of the conventional wiring structure 15, two modes of breakdown are often observed. In the first mode, discharge is caused by a path indicated by a broken line A′-CA ′ in FIG. 2A to cause dielectric breakdown. Here, C is a point C on the bottom surface of the recess 2a. In the first mode, the first and second wirings 4 ′ and 4 ″ between the lower corners A ′ and A ″ (the corners close to the interface between the first and second insulating layers 2 and 3) are adjacent to each other. Discharge occurs along the interface 21 between the second insulating layers 2 and 3.

  On the other hand, in the second mode, discharge is caused by a path indicated by a broken line B′-B ″ in FIG. 2B to cause dielectric breakdown. That is, the adjacent upper corners of the adjacent wiring 4 ′ and the wiring 4 ″ facing each other. B ′ and B ″ are discharged through the second insulating layer 3 (in the direction parallel to the bottom surface of the recess 2a). These upper corners B ′ and B ″ are connected to the wirings 4 ′ and 4 ″. Are the two corners farthest from the interface 21 between the first and second insulating layers 2 and 3. This second mode is a variation in manufacturing conditions with reference to FIG. Therefore, it frequently occurs when the upper sides of the wirings 4 ′ and 4 ″ are deformed wider than the lower sides.

  These dielectric breakdowns are considered to occur as follows. The wirings 4 ′ and 4 ″ are formed in a rectangular cross section. Therefore, the electric field tends to concentrate on the corners of the wirings 4 ′ and 4 ″, for example, the lower corners A ′ and A ″ or the upper corners B ′ and B ″. Then, a strong electric field concentrated on the corners A ′, A ″, B ′, B ″ causes the copper component in the wirings 4 ′, 4 ″ to be drawn into the second insulating layer 3, and the wirings 4 ′, 4 ″. Are diffused along a broken line A′-CA ′ or a broken line B′-B ″ connecting the corners of the two to form a discharge path. And it is estimated that it discharges along the discharge path formed by diffusion of copper.

  A discharge path between the lower corners A ′ and A ″ of the wirings 4 ′ and 4 ″ is formed along the interface between the first and second insulating layers 2 and 3. This is considered because copper is diffused along the interface having a high defect density because the lower corners A ′ and A ″ of the wirings 4 ′ and 4 ″ are close to the interface. On the other hand, the discharge path between the upper corners B ′ and B ″ away from the interface is formed in a straight line connecting the shortest distance regardless of the interface.

  It is difficult to predict which of the first and second mode dielectric breakdowns will precede. Therefore, in the HAST test of the conventional wiring structure, two breakdown modes occur in a mixed manner, and it is possible to analyze separately the cause of breakdown and the reliability of the insulation resistance in which each breakdown mode is involved. There wasn't. For this reason, it is not easy to analyze the cause of the dielectric breakdown, which is an obstacle to improving the dielectric breakdown resistance of the wiring structure. The present invention relates to a wiring structure having high insulation resistance and having no dielectric breakdown mode.

  1st Embodiment of this invention is related with the wiring structure of the circuit board produced by the semi-additive method.

  FIG. 3 is a cross-sectional view of the wiring structure according to the first embodiment of the present invention. Of the multilayer wiring board manufactured by the build-up method using the semi-additive method, the wiring structure 10 of the portion manufactured for the HAST test is shown. Represents. The planar shape of the portion of the wiring structure 10 produced for the HAST test is the same as the planar shape of the HAST test wiring shown in FIG. That is, referring to FIG. 1, it is composed of two comb-like wirings 20 'and 20 ".

  Referring to FIG. 3, in the wiring structure 10 of the first embodiment of the present invention, the first insulating layer 2 is formed on the support substrate 1, and the wiring 4 ′ is in contact with the upper surface of the first insulating layer 2. In addition, a dielectric layer 5 is provided on the first insulating layer 2 so as to contact the side surfaces of the wirings 4 ′ and 4 ″ and extend in a strip shape along the wirings 4 ′ and 4 ″. .

  The board | substrate 1 will not be restrict | limited especially if it is a board | substrate which has the rigidity which can support the wiring structure 10. FIG. For example, a resin substrate, a ceramic substrate, a metal substrate, or a Si wafer, which is usually used as a core of a circuit board, can be used. In the first embodiment, a Si wafer is used.

  The first and second insulating layers 2 and 3 may be any insulating material capable of forming a multilayer wiring using a build-up method as an interlayer insulating layer of the multilayer wiring. For example, a phenol-based or polyimide-based resin Can be used. In the first embodiment, a photosensitive phenolic resin is used.

  The wirings 4 ′ and 4 ″ are formed in a rectangular cross section, and include a copper wiring part 4a made of copper or a copper alloy, and an adhesion layer 4b provided on the lower surface of the copper wiring part 4a. The bottom surface is formed in close contact with the top surface of the first insulating layer 2, and the close contact layer 4b is sandwiched between the first insulating layer 2 and the copper wiring portion 4a, and the first insulating layer 2 and the copper wiring The adhesiveness with the part 4a is improved.

  The copper wiring portion 4a is a wiring member having a rectangular cross section made of copper or a copper alloy, and is formed in a rectangular cross section having a width of 2000 nm and a height of 2000 nm, for example. The copper wiring portion 4a is formed, for example, as a stacked structure of a seed layer 4c made of copper or a copper alloy formed on the adhesion layer 4b by sputtering and a copper plating layer 14a formed on the seed layer 4c. . In addition, this copper wiring part 4a may be produced by methods other than plating, and may have other structures other than the lamination of the seed layer 4c and the copper plating layer 14a.

  The adhesion layer 4b only needs to improve the adhesion between the first insulating layer 2 and the copper wiring portion 4a. For example, a metal film made of a metal of Ti, Ta, W, Zr, Cr or an alloy of these metals. Alternatively, a film made of a nitride of these metals can be used. In the first embodiment, a Ti film having a thickness of 50 nm is used.

  The dielectric layer 5 is made of an insulating material having a relative dielectric constant higher than that of the first and second insulating layers 2 and 3. The dielectric layer 5 is composed of a strip-shaped dielectric plate having a certain width, for example, a dielectric plate having a width of 80 nm and a thickness of 50 nm, and is formed in close contact with the upper surface of the first insulating layer 2. Furthermore, the dielectric layer 5 is formed so as to extend in parallel with the wirings 4 ′, 4 ″ with one side surface in contact with the side surfaces of the wirings 4 ′, 4 ″. Accordingly, the dielectric layer 5 is provided such that one side surface thereof is in contact with the lower corners of the wirings 4 ′ and 4 ″ (lower side surfaces of the wirings), and the other side surface projects horizontally from the lower corners of the wirings 4 ′ and 4 ″. .

  On the upper surface of the first insulating layer 2 described above, a region where the wirings 4 ′, 4 ″ and the dielectric layer 5 are disposed is formed in the convex portion 2b, and the other region is formed in the concave portion 2a. Of the first insulating layer 2 extending to the outside of the dielectric layer 5 (that is, between the dielectric layers 5 disposed in contact with the opposing side surfaces of the adjacent wirings 4 ′ and 4 ″). The upper surface is dug down and formed in the recess 2a. As a result, the mesa-shaped protrusion 2b is formed between the recesses 2a. The wirings 4 ′, 4 ″ and the dielectric layer 5 are formed in this protrusion. Provided on the upper surface of the portion 2b. The wirings 4 ′, 4 ″ and the dielectric layer 5 may be provided so as to cover the entire upper surface of the convex portion 2 b or may be provided so as to cover a part of the upper surface.

  In the first embodiment, the distance between the adjacent wirings 4 ′ and 4 ″ is 2000 nm, and the depth of the concave portion 2a is 800 nm. Therefore, the width of the upper surface of the convex portion 2b is 2160 nm, and the width of the concave portion 2a is 1840 nm. The height of the convex portion 2b is 800 nm, and the distance from the upper surface of the convex portion 2b to the upper surface of the silicon substrate 1 is set to 5000 nm in the wiring region for the HAST test.

  In addition, a copper diffusion preventing film 6 is provided so as to cover the copper wiring portion 4a. If there is no copper diffusion prevention film 6, this copper diffusion prevention film 6 covers the surface of the copper wiring part 4 a (the upper surface and the side surface of the copper wiring part 4 a) that will be in contact with the second insulating layer 3 described later. Is provided. The copper diffusion preventing film 6 may be any material that prevents copper diffusion and is not particularly limited. For example, it is possible to use an electroless plating film made of Co or Ni known as a copper diffusion preventing material, or Co or Ni alloy or a phosphorus compound thereof. In addition, a silicon nitride film, a silicon oxide film or a silicon oxynitride film formed by CVD (chemical vapor deposition), or a composite film thereof, and Ti, Ta, W, or Zr formed by CVD It is also possible to use a metal film made of or a compound or nitride of these metals. Note that the copper diffusion preventing film 6 may be omitted if not necessary. In the first embodiment, a CoWP film having a thickness of 20 nm is formed on the exposed surface of the copper wirings 4 ′, 4 ″ by electroless plating, and this is used as the copper diffusion prevention film 6.

  Further, the second insulating layer 3 covers the wirings 4 ′, 4 ″ and the dielectric layer 5, and the upper surface of the first insulating layer 2 extending outside the wirings 4 ′, 4 ″ and the dielectric layer 5. It is provided so that it may coat | cover. The second insulating layer 3 is exposed in a state where the second insulating layer 3 is not provided, and is exposed to the surfaces of the wirings 4 ′, 4 ″ and the dielectric layer 5, and the first insulating layer extending to the outside thereof. It is provided in close contact with the upper surface of the layer 2 so as to form an interface with the second insulating layer 3. Therefore, the surface of the recess 4a becomes the interface between the first and second insulating layers 2 and 3. .

  The second insulating layer 3 may be any insulating material that can be used as an interlayer insulating layer of a multilayer wiring and can form a multilayer wiring by a build-up method. For example, a phenol-based or polyimide-based resin can be used. . In the first embodiment, the same photosensitive phenolic resin as that of the first insulating layer 2 is used. The first and second insulating layers 2 and 3 may be made of the same material or different materials.

  In the description of the wiring structure 10 described above, the wiring portion for the HAST test has been described. However, the wiring structure 10 described above, that is, the upper surface of the first insulating layer 2 is formed in the concave portion 2a and the convex portion 2b, and the wirings 4 ′, 4 ″ and the dielectric layer 5 are disposed on the upper surface of the convex portion 2b. The structure in which the wirings 4 ′, 4 ″, the dielectric layer 5 and the recess 2b are embedded by the second insulating layer 3 is the same for other wirings of the circuit board of the first embodiment.

  That is, among the wirings used in the circuit board of the first embodiment, wirings formed in regions other than the HAST test wiring part, for example, wirings connecting between semiconductor elements or wirings constituting an electronic circuit are also planar. Other than the different shapes, they are formed to have the same cross-sectional structure. Of course, a part of the wiring having a different structure may be provided.

  The circuit board of the first embodiment described above was subjected to a HAST test, and insulation resistance was measured. In the HAST test, a voltage of 3.5 V was applied to the wiring 4 ′, and the wiring 4 ″ adjacent to the wiring 4 ′ and the substrate 1 were set to 0 V, and left in an environment with a temperature of 132 ° C. and a humidity of 85%. The time until dielectric breakdown was measured.

  FIG. 4 shows the HAST test results of the first embodiment of the present invention, and shows the time until the wiring structure 10 of the first embodiment reaches dielectric breakdown. As a comparative example, the test results of the conventional wiring structure 15 shown in FIG. 1 are also shown.

  Referring to FIG. 1A, the conventional wiring structure 15 used here is a wiring 4 ′, 4 ″ having a rectangular cross section with a width of 2000 nm and a height of 2000 nm arranged at a spacing of 2000 nm. And a recess 2a having a width of 2000 nm and a depth of 800 nm formed on the upper surface of the first insulating layer 2 between the wirings 4 ′ and 4 ″. Further, a copper diffusion prevention film (not shown) made of CoWP with a thickness of 20 nm is formed on the surface of the copper wiring portion 4a. Further, the distance between the wirings 4 ′ and 4 ″ and the upper surface of the substrate 1 is 5000 nm. Therefore, the first embodiment and the comparative example are different in the presence or absence of the dielectric layer 5, and accordingly, the concave portions 2b and the convex portions 2a are formed. The materials and dimensions are the same except that the widths are different.

  With reference to FIG. 4, in the wiring structure 10 of the first embodiment of the present invention, the time to dielectric breakdown was 150 hours or more for all the samples of sample numbers 1 to 9. Moreover, all the samples subjected to dielectric breakdown were broken down in the first mode in which discharge was performed along the interface between the first and second insulating layers 2 and 3.

  On the other hand, in the wiring structure 15 of the comparative example, referring to the sample numbers 11 to 19, the time until the dielectric breakdown reaches 92.2 hours to 150.0 hours varies widely, and the maximum is 150.0 hours. And shorter than the first embodiment. In addition, the dielectric breakdown is caused by the first mode in which discharge occurs along the interface between the first and second insulating layers 2 and 3 and the second corners of the wirings 4 ′ and 4 ″ penetrate through the second insulating layer 3. And the second mode of discharging.

  This test result shows that the wiring structure 10 of the first embodiment has better dielectric breakdown resistance than the conventional wiring structure 15 and that the wiring structure of the first embodiment is dielectric breakdown only in the first mode. To make it clear.

  The reason for this test result has not yet been clarified. However, the inventor of the present invention speculates that the concentration position of the electric field generated in the first and second insulating layers 2 and 3 around the wirings 4 ′ and 4 ″ moves as described below. Yes.

  FIG. 5 is an electric field intensity distribution diagram of the first embodiment of the present invention, showing the electric field intensity around the wiring structure 10 in a plane perpendicular to the wirings 4 ′ and 4 ″ (wirings 4 ′ and 4 ″ shown in FIG. 3). Represents the simulated result. Note that 3.5 V is applied to the wiring 4 ′ in FIG. 5 and 0 V is applied to the wiring 4 ″ adjacent to both sides and the substrate 1. FIG. 6 is a field intensity distribution diagram of the conventional wiring structure 15. 7 shows a simulation result of the electric field intensity around the conventional wiring structure 15 used as a comparative example in a plane perpendicular to the wirings 4 ′ and 4 ″.

  Here, the curves with decimal numbers in FIGS. 5 and 6 represent the surface of the equal electric field strength. Further, the attached numerical value is the logarithm of the intensity normalized by the reference electric field intensity Eo, log (Ex / Eo), of the electric field intensity Ex on the surface of the equal electric field intensity. In order to make the figure easy to see, the electric field strength is not displayed for the region surrounded by the dotted lines in the vicinity of the wirings 4 ′ and 4 ″ (the normalized electric field strength of this region is 6.2 or less). is there.).

  Referring to FIGS. 5 and 6, the region where the electric field strength is maximum (hereinafter referred to as “maximum electric field strength regions 22 ′, 22 ″, 23 ′, 23 ″”) has a standardized electric field strength of 6.4. These are areas surrounded by the surface of the equal electric field strength, and are shown as black areas in FIG. The maximum electric field strength regions 22 ′, 22 ″, 23 ′, and 23 ″ are outside the wirings 4 ′ and 4 ″ having a rectangular cross section (in the first and second insulating layers 2 and 3). “4” is formed near upper corners B ′ and B ″ and lower corners A ′ and A ″.

  The maximum electric field intensity regions 22 ′ and 22 ″ formed near the upper corners B ′ and B ″ of the wirings 4 ′ and 4 ″ are outside the wirings 4 ′ and 4 ″ in both the first embodiment and the comparative example. The second insulating layer 3 is formed in contact with the upper corners B ′ and B ″ of the wirings 4 ′ and 4 ″ or in the vicinity of the upper corners B ′ and B ″. The magnitudes of the intensity regions 22 ′, 22 ″, 23 ′, 23 ″ may represent the maximum electric field strength in that region. The maximum electric field strength region 22 near the upper corners B ′, B ″ of FIGS. Since the sizes of ', 22 "are substantially the same, the maximum electric field strength in the vicinity of the upper corners B', B" is not significantly different between the first embodiment and the comparative example. This point will be described later.

  On the other hand, the maximum electric field strength regions 23 ′ and 23 ″ formed near the lower corners A ′ and A ″ of the wirings 4 ′ and 4 ″ correspond to the wirings 4 ′ and 4 ″ in the first embodiment with reference to FIG. 4 ″, a region having a weaker electric field strength (regions with normalized electric field strengths of 6.2 and 6.0) is sandwiched between the lower corners A ′ and A ″ of the wirings 4 ′ and 4 ″. It is formed. On the other hand, referring to FIG. 6, in the comparative example, the maximum electric field strength region 23 ′ formed near the lower corners A ′ and A ″ of the wiring 4 ′ is formed very close to the lower corner A ′ of the wiring 4 ′. In the comparative example, the maximum electric field strength region is not formed in the vicinity of the lower corner A ″ of the wiring 4 ″. This state will be described in more detail below.

  FIG. 7 is an enlarged cross-sectional view of the first embodiment of the present invention, showing the vicinity of the lower corner A ′ of the wiring 4 ′. 7A shows the wiring 4 ′ of the first embodiment shown in FIG. 3, and FIG. 7B shows the wiring 4 ′ of the comparative example shown in FIG. 2.

  With reference to FIG. 7A, in the first embodiment of the present invention, a strip-shaped (plate-shaped) dielectric layer 5 is provided in contact with the side surface of the adhesion layer 4b constituting the lower portion of the wiring 4 '. In the figure, A ′ represents the lower corner 4 ′ of the wiring 4 ′, A′-1 represents a point A′-1 where the interface between the copper wiring portion 4a and the adhesion layer 4b appears on the side surface of the wiring 4 ′, and D 'And D'-1 represent the lower corner D' and the upper corner D'-1 of the side surface of the dielectric layer 5 that is not in contact with the wiring 4 '.

  The maximum electric field strength region 23 ′ of the first embodiment has side surfaces D ′ to D′-1 (side surfaces connecting the lower corner D ′ and the upper corner D′-1) of the dielectric layer 5 on the side not contacting the wiring 4 ′. Formed nearby. On the other hand, since the dielectric layer 5 having a high dielectric constant is in close contact with the lower corner A ′ of the wiring 4 ′, the electric field intensity near the lower corner A ′ is relaxed. Therefore, the maximum electric field strength region 23 ′ is formed near the side surfaces D ′ to D′−1 of the dielectric layer 5 at a position away from the wiring 4 ′.

  On the other hand, referring to FIG. 7B, in the comparative example, the lower corner A ′ of the wiring 4 ′ is in direct contact with the first and second insulating layers 2 and 3. Therefore, the electric field concentrates in the vicinity of the lower corner A ′ of the wiring 4 ′, and the maximum electric field strength region 23 ′ is formed in the vicinity of the lower corner A ′.

  Cu contained in the wiring 4 ′ is extracted and diffused into the first and second insulating layers 2 and 3 under a strong electric field. The diffusion of Cu is accelerated particularly in a region having a high structure defect density such as a surface or an interface. Therefore, if an interface exists near the place where the electric field concentration occurs, Cu diffuses along the interface to increase defects at the interface, and a discharge path along the interface is easily formed. This results in a first mode dielectric breakdown that discharges along the interface.

  FIG. 8 is a view showing the Cu diffusion path of the first embodiment of the present invention. FIG. 8A shows an Auger image of a cross section near the wiring after 150 hours have elapsed from the start of the HAST test. Represents an EELS analysis result of a location a (a region surrounded by a white circle), a location b (a cross section of the second insulating layer 3), and a location c (a cross section of the wiring 4 ′) shown in FIG. Yes.

  Referring to FIG. 8A, from the lower left corner of the wiring 4 ′ to the beginning left, then to the bottom, and finally to the left again, that is, along the interface 21 between the first and second insulating layers 2 and 3. It was observed that Cu was diffused (white line figure in FIG. 8A). Referring to the line a in FIG. 8B, the EELS analysis result at the location a indicates that the diffused Cu becomes insulating CuO. Therefore, the diffusion of Cu does not increase the conductivity of the interface 21. The inventor of the present invention does not directly induce the discharge of Cu, but Cu diffuses at the interface having a high defect density and further defects are introduced into the interface 21. As a result, the interface 21 becomes more in the discharge path. It is presumed to be easily altered. Note that Cu is not observed in the second insulating layer 3 50 nm above the interface location a (location b shown in FIG. 8A), and it is clear that Cu diffuses along the interface 21. Has been. The line c shows the spectrum of unoxidized Cu for reference.

  Considering that this Cu diffuses along the interface 21, referring to FIGS. 5 and 7A again, in the wiring structure 10 of the first embodiment, the maximum electric field concentration is the side surface of the dielectric layer 5. Occurs outside in contact with D ′ to D′−1 to form a maximum electric field strength region 23 ′. However, the normalized electric field strength is about 6.0 between the lower corner A ′ of the wiring 4 ′ and the side surfaces D ′ to D′−1 of the dielectric layer 5 where the maximum electric field strength region 23 ′ is formed. And weaker than the maximum electric field strength region 23 '.

  As described above, Cu is extracted by the electric field from the lower corner A ′ of the wiring 4 ′ (more precisely, the lower corner A′-1 of the copper wiring portion 4a), and the upper and lower surfaces (first and second insulating layers) of the dielectric layer 5 are used. Diffused along the interface between the layers 2 and 3 and diffused to the side surfaces D ′ to D′−1 of the dielectric layer 5. However, since the electric field strength at the lower corner A 'of the wiring 4' and the upper and lower surfaces of the dielectric layer 5 is weak, the diffusion rate is relatively slow. For this reason, a long diffusion time is required until the diffusion speed is accelerated by the strong electric field in the maximum electric field strength region 23 '. As a result, the inventor of the present invention considers that the time to dielectric breakdown becomes longer.

  In contrast, in the comparative example, referring to FIG. 6 and FIG. 7B, the maximum electric field concentration occurs on the outer side of the lower corner A ′ of the wiring 4 ′ and forms the maximum electric field strength region 23 ′. To do. Since the maximum electric field strength region 23 ′ is in contact with the wiring 4 ′, Cu is easily extracted from the wiring 4 ′ (precisely, the lower corner A′- 1 of the copper wiring portion 4 a). Moreover, the extracted Cu is accelerated by a strong electric field in the maximum electric field strength region 23 ′, diffuses on the side surface (between A′- 1 and A ′) of the thin adhesion layer 4 b in a short time, and reaches the interface 21. To do. Thus, in the comparative example, since the weak electric field region as formed in the first embodiment is not interposed between the wiring 4 ′ and the maximum electric field strength region 23 ′, the maximum electric field strength region is formed from the wiring 4 ′ to the interface. The inventor of the present invention considers that Cu diffusion is accelerated by a strong electric field of 23 'and dielectric breakdown proceeds in a short time.

  In other words, it is considered that the time until the dielectric breakdown in the first embodiment is longer than that in the comparative example is due to the movement of the maximum electric field strength region 23 ′ caused by electric field concentration. That is, the maximum electric field strength region 23 ′ is formed in contact with the wiring 4 ′ in the comparative example, whereas it is formed apart from the wiring 4 ′ in the first embodiment. For this reason, it is considered that the diffusion time during that period (while the upper and lower surfaces of the dielectric layer 5 are diffused) becomes longer, thereby delaying the dielectric breakdown.

  Next, in the first embodiment of the present invention, the inventor of the present invention speculates why the dielectric breakdown is limited to the first mode in which the interface is a discharge path as follows.

  Referring to FIGS. 5 and 6 again, the second breakdown mode is generated as a discharge between the upper corners B ′ and B ″ of the adjacent wirings 4 ′ and 4 ″. Such second mode dielectric breakdown is presumed to occur when the wirings 4 ′ and 4 ″, which should be rectangular in cross section, are formed with the upper portion widened as shown in FIG. 2B during the manufacturing process. That is, when the upper part of the wirings 4 ′ and 4 ″ is widened, the inner corners of the upper corners B ′ and B ″ become acute, and strong electric field concentration is likely to occur. Becomes narrower. For this reason, diffusion of Cu is likely to occur, and it is considered that dielectric breakdown occurs in a short time.

  As will be described later, for example, when the copper plating layer 14a constituting the copper wiring portion a is formed by electroplating, the resist cross-sectional shape that defines the copper plating layer 14a is the upper part of the opening. It is caused by deforming to spread. Accordingly, the deformation of the lower portion of the resist opening is small, and the shape of the bottom of the wiring 4 ', 4 "defined by the lower portion of the opening is hardly deformed. Further, the interval between the bottom of the wiring 4', 4" is formed almost constant.

  In the first embodiment, the dielectric layer 5 is provided in contact with the lower corners A ′ and A ″ of the wirings 4 ′ and 4 ″. However, the volume of the dielectric layer 5 is extremely small compared to the volume of the first and second insulating layers 2 and 3 between the wirings 4 ′ and 4 ″. For this reason, the wiring 4 ′ and the adjacent wiring 4 The stray capacitance between the substrate 1 and the substrate 1 hardly changes depending on the installation of the dielectric layer 5, and is usually smaller than the fluctuation of the stray capacitance caused by the variation in the manufacturing process. Therefore, in the simulation of the electric field strength, the total number of lines of electric force emitted from the wiring 4 ′ may be regarded as not changing depending on the presence or absence of the dielectric layer 5.

  On the other hand, since the number of electric field lines emitted from the lower corner A ′ of the wiring 4 ′ is substantially proportional to the size (surface area) of the maximum electric field strength region 23 ′, the first embodiment has a large maximum electric field strength region 23 ′. In many cases, there are few in a small comparative example. Therefore, the number (density) of electric lines of force emitted from the upper corner B 'of the wiring 4' is small in the first embodiment and larger in the comparative example. To put it simply, the number of lines of electric force is constant, and in the first embodiment, the lines of electric force are concentrated in the lower corner A ′ of the wiring 4 ′ than in the comparative example. Thus, the electric field strength at the upper corner B ′ is smaller than that of the comparative example. For this reason, the inventors of the present invention consider that the dielectric breakdown mode between the wirings 4 ′ and 4 ″ upper corners B ′ and B ″ is suppressed.

  As described above, the dielectric layer 5 relaxes the electric field at the lower corner A ′ of the wiring 4 ′, and at the same time, generates electric field concentration on the side surfaces D ′ to D′−1 far from the wiring 4 ′ of the dielectric layer 5. Let Thereby, the dielectric breakdown resistance of the wiring structure 10 is improved, and the dielectric breakdown mode is limited to one. In order to effectively improve the dielectric breakdown resistance and limit the breakdown mode, sufficient electric field relaxation in the lower corner A ′ of the wiring 4 ′ and sufficient electric field concentration on the side surfaces D ′ to D′−1 of the dielectric layer 5 are required. There must be. From this point of view, the dielectric constant and shape of the dielectric layer 5 are designed.

  Specifically, the dielectric constant of the dielectric layer 5 is desirably large and should be at least larger than the dielectric constant of the first and second insulating layers 2 and 3. Usually, an insulating material having a dielectric constant of about 3 to 8 is used for the first and second insulating layers 2 and 3. Therefore, it is preferable to use an insulating material having a dielectric constant of 20 or more, for example, a metal oxide of Ti, Ta, W, Zr or Cr. In the first embodiment, Ti oxide is used as the material of the dielectric layer 5. As will be described later, the dielectric layer 5 can be formed by oxidizing a part of the adhesion layer 4b. Thereby, the dielectric material layer 5 can be formed easily. The dielectric layer 5 may be formed by other methods.

  The dielectric layer 5 preferably has a thin plate shape, and is disposed so that the upper and lower main surfaces thereof are in contact with the first and second insulating layers 2, respectively. By forming the thin plate shape, strong electric field concentration can be caused at a position sufficiently separated from the wiring 4 ′ (side surfaces D ′ to D′−1 of the dielectric layer on the side far from the wiring 4 ′).

  The preferred shape and dimensions of the dielectric layer 4 depend on the dielectric constant of the dielectric layer 5 and must be appropriately designed according to the dielectric constant. For example, the dielectric layer 4 made of titanium oxide preferably has a thickness of 10 to 50 nm and a width that is 1.5 times or more of the thickness, and further has a thickness of 10 to 20 nm and a width of 50 to 100 nm. preferable. If the dielectric layer 4 is too thin, the electric field relaxation at the lower corner of the wiring 4 'becomes insufficient, and excellent discharge breakdown resistance cannot be obtained. If it is too thick, the electric field strength in the vicinity of the side surfaces D 'to D'-1 will not be sufficiently strong, and it will not be possible to prevent a mixture of discharge breakdown modes. On the other hand, if the width of the dielectric layer 4 is too narrow, the electric field concentration position is close to the wiring, and the discharge breakdown resistance deteriorates. If it is too wide, the distance between the dielectric layers 4 in close contact with the adjacent wirings 4 ′, 4 ″ becomes narrow, and the discharge breakdown resistance deteriorates.

  Hereinafter, the manufacturing process of the wiring structure 10 of the first embodiment described above will be described.

  9 to 12 are sectional views (No. 1) to (No. 4) of a manufacturing process of the wiring structure according to the first embodiment of the present invention, and show the wiring structure in the middle of manufacturing.

  Referring to FIG. 9A, first, a substrate 1 serving as a support base, for example, a silicon substrate is prepared. Next, the first insulating layer 2, the adhesion layer 4 b and the seed layer 4 c were sequentially laminated on the upper surface of the substrate 1. For the first insulating layer 2, a positive type photosensitive phenolic resin (product name WPRseries of JSR Corporation) was used. A non-photosensitive resin such as polyimide may be used. For the adhesion layer 4b, a 50 nm thick Ti film formed by sputtering was used. In order to form the thin dielectric layer 5, it is more preferable to use a Ti film having a thickness of 5 to 20 nm as the adhesion layer 4b. As the seed layer 4c, a Cu layer having a thickness of 20 to 100 nm formed by sputtering was used. In addition, you may form the contact | adherence layer 4b and the seed layer 4c by other methods, for example, CVD method or electroless plating. Furthermore, the adhesion layer 4b can also be formed from Ta, W, Zr and Cr or their alloys and nitrides.

  Next, referring to FIG. 9B, a resist 41 having a thickness of, for example, 3000 nm is applied on the seed layer 4c, exposed and developed, and groove-shaped openings 41a having a width of 2160 nm are formed at a pitch of 4000 nm. A stepper or contact aligner was used for exposure, and TMAH (tetramethylammonium hydroxide) was used for development. If necessary, thereafter, the surface of the resist 41 is hydrophilized. Thereafter, resist was post-baked.

  By this post-baking process, the upper part of the opening 41a of the resist 41 may be deformed so as to be widened. If the deformation is large, as shown in FIG. 2B, wirings 4 ′ and 4 ″ whose upper portions are widened are easily formed. As a result, a discharge occurs between the wirings 4 ′ and 4 ″ upper corners B ′ and B ″. On the other hand, the width of the bottom surface of the opening 41a is hardly deformed from the width formed by exposure and development. Therefore, the variation in the width of the bottom surface of the wirings 4 ′ and 4 ″ is slight. The effect of the fluctuation on dielectric breakdown resistance is small.

  Next, with reference to FIG. 10C, a copper plating layer 14a having a thickness of about 2000 nm for embedding the opening 41a of the resist 41 was formed by electrolytic plating using the seed layer 4c as one electrode. A copper sulfate plating bath was used as the electrolytic plating solution. Note that the copper plating layer 14a can also be formed by another method of filling the opening 41a with a copper layer, for example, electroless plating.

  Next, referring to FIG. 10D, the resist 41 is removed using an organic solvent such as NMP (n-methyl-2-pyrrolidone) or acetone. Next, the seed layer 4c exposed in the region from which the resist 41 was removed, and the adhesion layer 4b immediately below the seed layer 4c were removed by etching using the copper plating layer 14a as a mask. The seed layer 4c was removed by etching using a potassium sulfate solution as an etchant. In addition, an iron chloride or ammonium persulfate solution can be used as an etchant for the seed layer 4c. The adhesion layer 4b was removed by etching using an ammonium fluoride solution as an etchant. In addition, for the removal of the adhesion layer 4b, for example, dry etching using tetrafluoromethane as an etching gas can be used.

  Next, the surface of the first insulating layer 2 exposed between the copper plating layers 14a was etched by a depth of 800 nm using dry etching using oxygen gas as an etching gas. As a result, referring to FIG. 11E, the surface of the first insulating layer 2 exposed between the copper plating layers 14a is dug down to form the recesses 2a. At the same time, the surface immediately below the copper plating layer 14a is left as it is, and becomes a convex portion 2b. Accordingly, the recesses 2a having a width of 1840 nm and the protrusions 2b having a width of 2160 nm are alternately formed in a line and space pattern on the surface of the first insulating layer 2.

  Next, with reference to FIG. 11F, the exposed surfaces of the copper plating layer 14a and the seed layer 4c were etched by wet etching in which a potassium sulfate solution was etched. The etching amount is approximately the width of the dielectric layer 4, for example, 80 nm. As a result, a copper wiring portion 4a having a width of 2000 nm composed of a laminate of the copper plating layer 14a and the seed layer 4c was formed. At this time, a part of the adhesion layer 4b is exposed outside the both side surfaces of the copper wiring portion 4a.

  Next, referring to FIG. 12G, the adhesion layer 4b exposed on the exposed surface of the copper wiring portion 4a and the outside of the copper wiring portion 4a is oxidized by dry etching using oxygen gas as an etching gas. As a result, the portion of the adhesion layer 4b that appears outside the copper wiring portion 4a is oxidized and converted to the dielectric layer 5 made of, for example, titanium oxide. In addition, the exposed surface (upper surface and side surface) of the copper wiring portion 4a is oxidized to form a copper oxide layer 4ox.

  Next, referring to FIG. 12H, the oxide layer 4ox formed on the surface of the copper wiring portion 4a was removed by etching using dilute sulfuric acid as an etchant. The oxide layer 4ox is thin, and normally, the dimensional change of the copper wiring portion 4a due to the formation of the oxide layer 4ox can be ignored. Next, a copper diffusion prevention film 6 made of CoWP having a thickness of 20 nm was formed on the exposed surface of the copper wiring portion 4a by electroless plating. As the copper diffusion preventing film 6, a NiP electroless plating film may be used, and further a silicon nitride CVD film may be used.

  Next, a second insulating layer 3 made of a photosensitive phenol resin was formed on the first insulating layer 2. Through the above steps, the wiring structure 10 according to the first embodiment of the present invention described with reference to FIG. 3 is manufactured.

  The second embodiment of the present invention relates to a wiring structure in which the surface of the first insulating layer is flat.

  FIG. 13 is a cross-sectional view of the wiring structure according to the second embodiment of the present invention. Of the wiring structure of the multilayer wiring board manufactured by the build-up method using the semi-additive method, the portion manufactured for the HAST test is shown. The wiring structure 11 is shown. The planar shape of the wiring structure 10 in this portion is the same as the planar shape of the HAST test wiring shown in FIG.

  Referring to FIG. 13, the wiring structure 11 of the second embodiment is the same as the wiring structure 10 of the first embodiment except that the upper surface of the first insulating layer 2 is flat. That is, the concave portion 2a and the convex portion 2b are not formed on the upper surface of the first insulating layer 2 as in the wiring structure 10 of the first embodiment.

  In this wiring structure 11, the shape of the wirings 4 ′, 4 ″ and the surrounding dielectric constant (comprising the first and second insulating layers 2, 3) are the same as those in the first embodiment. The electric field strength distribution in the structure 11 is the same as the electric field strength distribution of the first embodiment shown in Fig. 5. Therefore, as in the first embodiment, excellent dielectric breakdown resistance and a single dielectric breakdown mode are obtained. Realized.

  However, in the second embodiment, the interface 21 between the first and second insulating layers 2 and 3 is formed flat, so that the interface 4 includes the wiring 4 ′ as compared with the first embodiment in which the interface 21 includes the surface of the recess 2a. The interface 21 extending between 4 ″ is short. The breakdown resistance is deteriorated by the short part of the interface. Nevertheless, this deterioration is often caused by the breakdown resistance due to the installation of the dielectric layer 5. Therefore, the dielectric breakdown resistance superior to that of the conventional example is realized.

  Hereinafter, the manufacturing process of the wiring structure of the second embodiment will be described.

  14 to 15 are sectional views (No. 1) to (No. 2) of the manufacturing process of the wiring structure according to the second embodiment of the present invention, and show the wiring structure during the manufacturing.

  The manufacturing process of the wiring structure 11 of the second embodiment is the same as the manufacturing process of the wiring structure 10 of the first embodiment shown in FIGS. That is, referring to FIG. 10D, the laminated structure of the adhesion layer 4b, the seed layer 4c, and the copper plating layer 14a manufactured in a line shape having a width of 2160 nm by the steps up to FIG. Formed on layer 2.

  Next, the exposed surfaces of the copper plating layer 14a and the seed layer 4c were etched by wet etching in which a potassium sulfate solution was etched to remove the thickness of 80 nm. As a result, referring to FIG. 14A, a copper wiring portion 4a having a width of 2000 nm made of a laminate of the seed layer 4c and the copper plating layer 14a was formed. An adhesion layer 4b having a width of 80 nm is exposed on both sides outside of the copper wiring portion 4a.

  Next, referring to FIG. 14B, the adhesion layer 4 b exposed on the exposed surface of the copper wiring portion 4 a and the outside of the copper wiring portion 4 a was oxidized by dry etching using oxygen gas as an etching gas. As a result, the adhesion layer 4b exposed outside the copper wiring portion 4a is oxidized and converted into the dielectric layer 5 made of titanium oxide, and at the same time, a copper oxide layer 4ox is formed on the exposed surface of the copper wiring portion 4a. The

  Next, referring to FIG. 15C, the oxide layer 4ox (see FIG. 14C) is removed by etching. Thereafter, referring to FIG. 15D, as in the first embodiment, a copper diffusion prevention film 6 made of a CoWP electroless plating film having a thickness of 20 nm was formed on the exposed surface of the copper wiring portion 4a. Next, the second insulating layer 3 was formed on the first insulating layer 2 to manufacture the wiring structure 11 of the second embodiment shown in FIG.

  In the second embodiment, since there is no formation process of the recess 2a, the manufacturing process is simple. On the other hand, substantially the same breakdown resistance and a single breakdown mode as in the first embodiment are realized.

  3rd Embodiment of this invention is related with the wiring structure 12 which abbreviate | omitted the etching process of the copper wiring part 4a.

  FIG. 16 is a cross-sectional view of a wiring structure according to the third embodiment of the present invention. FIG. 16A shows a cross-sectional structure perpendicular to the wirings 4 ′ and 4 ″ of the wiring structure 2, and FIG. A part of the wiring 4 ′ in FIG.

  Referring to FIG. 16, the wiring structure 12 of the third embodiment is the same as that of the second embodiment except that the width of the dielectric layer 5 is narrow and the dielectric layer 5 and the adhesion layer 4b are thin. It is. That is, in the wiring structure 12 of the third embodiment, the width of the dielectric layer 5 is narrow, for example, 30 nm, compared to the wiring structure 11 of the second embodiment. The dielectric layer 5 is also thin, for example, 10 nm. Similarly, the thickness of the adhesion layer 4b is, for example, 10 nm as with the dielectric layer 5.

  Similar to the first and second embodiments, the wiring structure 12 having such a structure has excellent dielectric breakdown resistance and a single dielectric breakdown mode characteristic.

  17 to 18 are sectional views (No. 1) to (No. 2) of the manufacturing process of the wiring structure of the third embodiment of the present invention, showing the sectional structure of the wiring structure 12 of the third embodiment during the manufacturing. Yes.

  The manufacturing process of the wiring structure 12 of the third embodiment is the same as the process shown in FIGS. 9 to 10D of the first embodiment until halfway. However, referring to FIG. 10D, the width of the copper plating layer 14a and the seed layer 4c is formed to be, for example, 2060 nm narrower than that of the first embodiment. As a result, with reference to FIG. 17A, a laminated body having a width of 2060 nm composed of the copper plating layer 14a and the seed layer 4c laminated via the adhesion layer 4b is formed on the flat upper surface of the first insulating layer 2. Is done.

  Next, referring to FIG. 17B, the exposed surface of the copper plating layer 14 a and the seed layer is oxidized by, for example, exposure to oxygen plasma to form a copper oxide layer 4 ox having a thickness of 30 nm, for example. At the same time, both side surfaces of the adhesion layer 4b are oxidized to form a dielectric layer 5 made of, for example, an oxide of the adhesion layer having a width of 30 nm and a thickness of 10 nm, for example, titanium oxide. In this step, the laminate of the copper plating layer 14a and the seed layer 4c is formed on the copper wiring portion 4a having a width of 2000 nm. The copper wiring portion 4a forms wirings 4 'and 4 "together with the adhesion layer 4b on the bottom surface.

  Next, referring to FIG. 18C, the oxide layer 4a formed on the surface of the copper wiring portion 4a was removed by etching. Next, referring to FIG. 18D, a copper diffusion preventing film made of CoWP having a thickness of 20 nm was formed on the exposed surface of the copper wiring portion 4a by, for example, electroless plating.

  In the third embodiment, the etching process for the copper wiring portion 4a required in the first and second embodiments is not required, and therefore the process is simplified.

  The fourth embodiment of the present invention relates to a wiring structure 13 formed by a damascene method.

  FIG. 19 is a cross-sectional view of a wiring structure according to a fourth embodiment of the present invention. FIG. 19A shows a HAST test among the wiring structure 13 of the multilayer wiring board manufactured by the build-up method using the damascene method. Represents the produced part. FIG. 19B shows an enlarged cross section near the upper corner of the wiring 4 ′ shown in FIG.

  Referring to FIG. 19A, in the wiring structure 13 of the fourth embodiment, a wiring groove 31 is formed on the upper surface of the first insulating layer 2 provided on the upper surface of the substrate 1, and the wiring groove 31 is embedded, for example. Wirings 4 ′ and 4 ″ having a width of 2000 nm and a thickness (height) of 2000 nm are formed. The wirings 4 ′ and 4 ″ include a copper wiring portion 4a made of copper or a copper alloy, side surfaces of the copper wiring portion 4a, and It is comprised from the contact | adherence layer 5 which coat | covers a bottom face. The adhesion layer 5 may be a Ti film made of the same material as that of the first embodiment, for example, having a thickness of 10 nm.

  Referring to FIG. 19B, the upper surface of the wiring 4 ′ (the upper surface of the copper wiring portion 4a) is the opening surface of the wiring groove 31 (the first and second insulating layers 2 extending outside the wiring groove 31). For example, 30 nm lower than the three interfaces 21). Further, the upper side surface (a plane connecting B ′ to B′−1 in the drawing) of the adhesion layer 4 b is also located at the same height as the upper surface of the wiring 4 ′. In FIG. 19B, symbols B ′ and B′−1 denote the upper corner B ′ of the wiring 4 ′ (that is, the upper corner of the adhesion layer 4b away from the copper wiring portion 4a) and the copper wiring, respectively. This represents the upper corner B′-1 of the portion 4a (that is, the upper corner of the adhesion layer 4b on the side in contact with the copper wiring layer 4a).

  Furthermore, the dielectric layer 5 is provided on the side wall surface of the wiring groove 31 extending in contact with the upper side surface of the adhesion layer 4b. The dielectric layer 5 is composed of a plate-like dielectric material extending in a band shape along the wiring 4 '. The thickness, width and material of the dielectric layer 5 are the same as those in the first to third embodiments.

  A copper diffusion preventing film 6 having the same material and thickness as in the first embodiment is formed on the upper surface of the copper wiring portion 4a. If not necessary, the copper diffusion prevention film 6 may be omitted. Furthermore, a second insulating layer 3 is provided which covers the wiring 4 ′, the dielectric layer 5 and the copper diffusion preventing film 6 and covers the upper surface of the first insulating layer 2 extending outside the wiring groove 31. The second insulating layer 3 is exposed when the second insulating layer 3 is not present, and the upper surface of the copper diffusion preventing film 6 (or the upper surface of the copper wiring portion 4 ′) that is exposed. The dielectric layer 5 is provided so as to cover the main surface and the upper side surface of the dielectric layer 5 and the upper surface of the first insulating layer 2 exposed if the second insulating layer 3 is not provided, and to form an interface on these surfaces. . The structure related to the wiring 4 ′ has been described so far, but the same applies to the wiring 4 ″. The materials of the first and second insulating layers 2 and 3, the adhesion layer 5 and the substrate 1 are also the first embodiment. The same as above.

  In the wiring structure 13 of the fourth embodiment, electric field concentration occurs at a position away from the wirings 4 ′ and 4 ″, that is, in the vicinity of the upper side surface (surface connecting E ′ to E′-1) of the dielectric layer. Therefore, the wiring structure 13 has the same excellent dielectric breakdown resistance as that of the first embodiment, and the dielectric breakdown mode is also limited to a discharge path between the upper corners B ′ and B ″ of the wirings 4 ′ and 4 ″. Is done.

  Hereinafter, the manufacturing process of the wiring structure 13 of the fourth embodiment will be described.

  20 to 22 are sectional views (No. 1) to (No. 3) of the manufacturing process of the wiring structure according to the fourth embodiment of the present invention, and show the wiring structure 13 being manufactured by the damascene process.

  Referring to FIG. 20A, in the wiring structure 13 of the fourth embodiment, first, the first insulating layer 2 made of a photosensitive resin is formed on the substrate 1, and then the first insulating layer 2 is formed. Are exposed and developed to form a wiring groove 31 having a depth of 2030 nm for defining the wirings 4 ′ and 4 ″.

  Next, referring to FIG. 20B, an adhesion layer 4 b made of, for example, a 10 nm-thick Ti film that covers the inner wall surface of the wiring groove 31 and the upper surface of the first insulating layer 2 is formed. This adhesion layer 4b can be formed by sputtering or CVD, for example. In addition to Ti, a material that improves adhesion to copper or a copper alloy, for example, a metal film made of Ti, Ta, W, Zr, or Cr, an alloy film of these metals, or a metal or alloy of these metals or alloys A nitride film can be used. Next, the wiring trench 31 is buried, and a copper layer 32 extending on the upper surface of the first insulating layer 2 is formed. The copper layer 32 can be formed by, for example, CVD, electroless plating, or electrolytic plating as in the first to third embodiments.

  Next, referring to FIG. 21C, the copper layer 32 is polished by CMP (Chemical Mechanical Polishing) until the upper surface of the first insulating layer is exposed. As a result, a copper wiring portion 4a made of the copper layer 32 embedded in the wiring groove 31 is formed, and wirings 4 ′ and 4 ″ made of the copper wiring portion 4a and the adhesion layer 4b covering the side and bottom surfaces thereof are formed. Is done.

  Next, referring to FIG. 21D, the upper surfaces (exposed surfaces) of the wirings 4 ′ and 4 ″ are oxidized by dry etching using oxygen gas as an etching gas. Thereby, the upper surface of the copper wiring part 4a. Is oxidized to a depth of 30 nm, for example, and converted to an oxide layer 4ox, and at the same time, the portion from the upper end of the adhesion layer 4b to a depth of 30 nm is oxidized and converted to a dielectric layer 5 made of, for example, titanium oxide.

  Next, referring to FIG. 22E, the oxide layer 4ox is removed by etching. Next, referring to FIG. 22F, a copper diffusion prevention layer 6 made of, for example, CoWP having a thickness of 20 nm was formed on the upper surface of the copper wiring portion 4a exposed in the region where the oxide layer 4ox was removed. Next, referring to FIG. 19, the second insulating layer 3 is formed thereon, and the wiring structure 13 according to the fourth embodiment of the present invention is manufactured.

  In the manufacturing process shown in FIG. 21 of the wiring structure 13 of the fourth embodiment described above, after the wirings 4 ′ and 4 ″ are formed in the process shown in FIG. 21E, the oxide layer 4ox shown in FIG. The upper surface of the copper wiring portion 4a can also be removed by etching before forming the dielectric layer 5. Thereafter, the exposed copper wiring portion 4a and the adhesion layer 4b are oxidized to form the oxide layer 4ox and The dielectric layer 5 is formed.

  Thus, by etching the upper surface of the copper wiring portion 4a in advance, the wide dielectric layer 5 can be reliably formed even when the upper surface of the copper wiring portion 4a is oxidized shallowly. As a result, the electric field concentration region can be more reliably moved away from the wirings 4 ′ and 4 ″, and the dielectric breakdown resistance can be further increased.

  By applying the present invention to the wiring structure of a circuit board on which a semiconductor device is mounted, a highly reliable circuit board having excellent dielectric breakdown resistance and limited dielectric breakdown modes is provided.

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 1st insulating layer 2a Concave part 2b Convex part 3 2nd insulating layer 4 ', 4 "wiring 4a Copper wiring part 4b Adhesion layer 4c Seed layer 4ox Oxide layer 5 Dielectric layer 6 Copper diffusion prevention film 10, 11, 12, 13 Wiring structure 15 Conventional wiring structure 14a Copper plating layer 20 Wiring for HAST test 20 ', 20 "Comb-shaped wiring 20A', 20A" Connection portion 21 Interface 31 Wiring groove 32 Copper layer 41 Resist 41a Opening 22 ', 22 ", 23', 23" Maximum field strength region

Claims (8)

A first insulating layer;
A wiring provided on the first insulating layer and having a copper wiring portion made of copper or a copper alloy;
A dielectric layer provided on the first insulating layer and extending in a band along the wiring with one side contacting the wiring;
A second insulating layer provided on the first insulating layer and covering the wiring and the dielectric layer;
The wiring structure according to claim 1, wherein the dielectric layer has a higher dielectric constant than the first and second insulating layers. The wiring has an adhesion layer made of a metal that adheres to the first insulating layer on a lower surface of the copper wiring portion,
The wiring structure according to claim 1, wherein the dielectric layer is made of a metal oxide constituting the adhesion layer.   3. The wiring structure according to claim 2, wherein a copper diffusion preventing film made of an insulator or a metal film having a relative dielectric constant lower than that of the dielectric layer is provided on an upper surface and a side surface of the copper wiring portion. A first insulating layer having a wiring groove formed on the upper surface;
Wiring having a copper wiring portion made of copper or a copper alloy embedded in the wiring groove to the middle of the wiring groove;
A dielectric layer formed on a side wall surface of the wiring groove located above the wiring and extending in a strip shape along the wiring with a lower surface in contact with the upper surface of the wiring;
A second insulating layer provided on the first insulating layer and covering the wiring and the dielectric layer;
The wiring structure according to claim 1, wherein the dielectric layer has a higher dielectric constant than the first and second insulating layers. The wiring has, on the side surface of the copper wiring portion, an adhesion layer made of a metal that is in close contact with the side wall surface of the wiring groove,
The wiring structure according to claim 4, wherein the dielectric layer is made of a metal oxide constituting the adhesion layer. Sequentially forming a first insulating layer, a metal adhesion layer and a copper seed layer on a substrate;
Forming a resist layer having an opening on the copper seed layer;
Using electrolytic plating with the copper seed layer as one electrode, forming a copper plating layer made of a buried alloy up to a height of the opening; and
Removing the copper seed layer and the adhesion layer extending outside the copper plating layer by etching using the copper plating layer as a mask after removing the resist layer;
Next, the exposed surfaces of the adhesion layer, the copper seed layer, and the copper plating layer are oxidized, and both end portions of the adhesion layer are made of a metal oxide constituting the adhesion layer and are higher than the first insulating layer. Converting to a dielectric layer having a dielectric constant;
Etching away the oxidized surfaces of the copper plating layer and the copper seed layer;
Forming a second insulating layer having a relative dielectric constant lower than that of the dielectric layer covering the copper plating layer, the copper seed layer, and the dielectric layer on the first insulating layer;
A method for manufacturing a wiring structure, comprising: Instead of converting to the dielectric layer,
Etching the exposed surfaces of the copper plating layer and the copper seed layer by selective etching of copper, and exposing the upper surface of the adhesion layer outside the copper seed layer after etching;
The adhesion layer, the copper plating layer, and the exposed surface of the copper seed layer are oxidized, and the adhesion layer that is exposed to the outside of the copper seed layer is composed of an oxide of the metal constituting the adhesion layer. Converting to a dielectric layer having a higher dielectric constant than the first insulating layer;
The method for manufacturing a wiring structure according to claim 6, wherein: Forming a first insulating layer provided with a wiring groove on the substrate;
Covering the inner wall surface of the wiring groove and forming an adhesion layer made of metal extending on the upper surface of the first insulating layer;
Next, forming a copper layer made of copper or a copper alloy filling the wiring groove and extending on the first insulating layer;
Polishing from the upper surface of the copper layer to the upper surface of the first insulating layer to leave the adhesion layer and the copper layer in the wiring groove;
The upper surface of the adhesion layer exposed on the polished surface and the upper surface of the copper layer are oxidized by the polishing, and the upper portion of the adhesion layer is oxidized with the higher dielectric constant than the first insulating layer. Converting to a dielectric layer made of a material,
Etching and removing the oxide layer formed on the upper surface of the copper layer by the oxidation;
Next, forming a second insulating layer having a dielectric constant lower than that of the dielectric layer on the first insulating layer;
A method for manufacturing a wiring structure, comprising: