JP2018536942A - ハードウェアフロー制御を伴う拡張シリアル周辺インターフェース - Google Patents

ハードウェアフロー制御を伴う拡張シリアル周辺インターフェース Download PDF

Info

Publication number
JP2018536942A
JP2018536942A JP2018529109A JP2018529109A JP2018536942A JP 2018536942 A JP2018536942 A JP 2018536942A JP 2018529109 A JP2018529109 A JP 2018529109A JP 2018529109 A JP2018529109 A JP 2018529109A JP 2018536942 A JP2018536942 A JP 2018536942A
Authority
JP
Japan
Prior art keywords
slave
voltage state
select line
line
slave select
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2018529109A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018536942A5 (enExample
Inventor
ララン・ジー・ミシュラ
リチャード・ドミニク・ウィートフェルト
Original Assignee
クアルコム,インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム,インコーポレイテッド filed Critical クアルコム,インコーポレイテッド
Publication of JP2018536942A publication Critical patent/JP2018536942A/ja
Publication of JP2018536942A5 publication Critical patent/JP2018536942A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/404Coupling between buses using bus bridges with address mapping
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4411Configuring for operating with peripheral devices; Loading of device drivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Information Transfer Systems (AREA)
  • Power Sources (AREA)
JP2018529109A 2015-12-10 2016-11-15 ハードウェアフロー制御を伴う拡張シリアル周辺インターフェース Pending JP2018536942A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562265877P 2015-12-10 2015-12-10
US62/265,877 2015-12-10
US15/348,435 US10140243B2 (en) 2015-12-10 2016-11-10 Enhanced serial peripheral interface with hardware flow-control
US15/348,435 2016-11-10
PCT/US2016/062106 WO2017099959A1 (en) 2015-12-10 2016-11-15 Enhanced serial peripheral interface with hardware flow-control

Publications (2)

Publication Number Publication Date
JP2018536942A true JP2018536942A (ja) 2018-12-13
JP2018536942A5 JP2018536942A5 (enExample) 2019-12-05

Family

ID=57442825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018529109A Pending JP2018536942A (ja) 2015-12-10 2016-11-15 ハードウェアフロー制御を伴う拡張シリアル周辺インターフェース

Country Status (9)

Country Link
US (1) US10140243B2 (enExample)
EP (1) EP3387542B1 (enExample)
JP (1) JP2018536942A (enExample)
KR (1) KR20180092972A (enExample)
CN (1) CN108369569B (enExample)
AU (1) AU2016369271A1 (enExample)
BR (1) BR112018011598A2 (enExample)
TW (1) TW201729110A (enExample)
WO (1) WO2017099959A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170371830A1 (en) * 2016-06-28 2017-12-28 Qualcomm Incorporated Accelerated i3c master stop
US9734099B1 (en) * 2017-04-27 2017-08-15 Micro Lambda Wireless, Inc. QSPI based methods of simultaneously controlling multiple SPI peripherals
US10459869B2 (en) * 2017-12-17 2019-10-29 Himax Technologies Limited Electronic apparatus and operation method thereof
CN110008155B (zh) * 2018-01-04 2023-02-28 奇景光电股份有限公司 电子装置及其操作方法
US11288215B2 (en) * 2020-08-28 2022-03-29 Juniper Networks, Inc. Mapped register access by microcontrollers
CN114138700B (zh) * 2021-12-03 2023-11-24 西安广和通无线软件有限公司 一种串口数据传输的流控方法、装置、设备及存储介质
TWI812194B (zh) * 2022-04-27 2023-08-11 凌通科技股份有限公司 序列周邊介面相容性擴展切換方法與使用其之嵌入式系統
CN114911743B (zh) * 2022-07-12 2022-10-25 杭州晶华微电子股份有限公司 Spi从机设备、spi主机设备和相关的通信方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020120795A1 (en) * 2001-02-28 2002-08-29 Alcatel Serial peripheral interface master device, a serial peripheral interface slave device and a serial peripheral interface
US20080307126A1 (en) * 2007-06-07 2008-12-11 Via Technologies, Inc. System and method for serial-peripheral-interface data transmission
CN102508812A (zh) * 2011-11-30 2012-06-20 上海大学 一种基于spi总线的双处理器通信方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3134819B2 (ja) 1997-06-04 2001-02-13 ソニー株式会社 データ処理装置
US5933025A (en) * 1997-01-15 1999-08-03 Xilinx, Inc. Low voltage interface circuit with a high voltage tolerance
US7171542B1 (en) * 2000-06-19 2007-01-30 Silicon Labs Cp, Inc. Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins
US20030028864A1 (en) 2001-01-29 2003-02-06 Matt Bowen System, method and article of manufacture for successive compilations using incomplete parameters
US6957284B2 (en) 2002-01-16 2005-10-18 Microsoft Corporation System and method for pendant bud for serially chaining multiple portable pendant peripherals
JP4834294B2 (ja) 2004-01-07 2011-12-14 日立オートモティブシステムズ株式会社 データ通信装置及びそれを用いたコントローラ
US20050223141A1 (en) * 2004-03-31 2005-10-06 Pak-Lung Seto Data flow control in a data storage system
US20060143348A1 (en) 2004-12-29 2006-06-29 Wilson Matthew T System, method, and apparatus for extended serial peripheral interface
US7509445B2 (en) 2006-04-12 2009-03-24 National Instruments Corporation Adapting a plurality of measurement cartridges using cartridge controllers
JP4066383B2 (ja) 2006-07-06 2008-03-26 シチズンホールディングス株式会社 通信装置および通信制御方法、並びに当該通信装置を備えたプリンタ
US7755412B2 (en) 2008-04-01 2010-07-13 Kyocera Corporation Bi-directional level shifted interrupt control
US8732366B2 (en) 2012-04-30 2014-05-20 Freescale Semiconductor, Inc. Method to configure serial communications and device thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020120795A1 (en) * 2001-02-28 2002-08-29 Alcatel Serial peripheral interface master device, a serial peripheral interface slave device and a serial peripheral interface
US20080307126A1 (en) * 2007-06-07 2008-12-11 Via Technologies, Inc. System and method for serial-peripheral-interface data transmission
CN102508812A (zh) * 2011-11-30 2012-06-20 上海大学 一种基于spi总线的双处理器通信方法

Also Published As

Publication number Publication date
TW201729110A (zh) 2017-08-16
AU2016369271A1 (en) 2018-05-24
US20170168978A1 (en) 2017-06-15
CN108369569A (zh) 2018-08-03
WO2017099959A1 (en) 2017-06-15
EP3387542B1 (en) 2019-12-25
EP3387542A1 (en) 2018-10-17
CN108369569B (zh) 2021-04-27
KR20180092972A (ko) 2018-08-20
US10140243B2 (en) 2018-11-27
BR112018011598A2 (pt) 2018-11-27

Similar Documents

Publication Publication Date Title
JP2018536942A (ja) ハードウェアフロー制御を伴う拡張シリアル周辺インターフェース
US11256651B2 (en) Multiple master, multi-slave serial peripheral interface
US10445270B2 (en) Configuring optimal bus turnaround cycles for master-driven serial buses
JP2019508915A (ja) メッセージングおよび入出力転送インターフェースのための最適レイテンシパケタイザ有限ステートマシン
US11106620B1 (en) Mixed signal device address assignment
TW201907314A (zh) 用於虛擬通用輸入/輸出有限狀態機器之硬體事件優先感測可程式化傳輸等待窗
US10572438B1 (en) Dynamic optimal data sampling time on a multi-drop bus
US11520729B2 (en) I2C bus architecture using shared clock and dedicated data lines
TW202024931A (zh) I3c匯流排上的緊急帶內中斷
US20180260357A1 (en) I2c clock stretch over i3c bus
CN120660083A (zh) 耦合到共享总线的设备的地址分配
TWI685749B (zh) 用於通信波形的短位址模式
US20180181532A1 (en) Data transfer ending in phase differential modes
US20190018818A1 (en) Accelerated i3c stop initiated by a third party
US10545886B2 (en) Clock line driving for single-cycle data over clock signaling and pre-emption request in a multi-drop bus
US20200042750A1 (en) Secure access for system power management interface (spmi) during boot
US20170371830A1 (en) Accelerated i3c master stop
US11023408B2 (en) I3C single data rate write flow control
WO2018226505A1 (en) Error correction calculation upon serial bus abort
US20190171611A1 (en) Protocol-framed clock line driving for device communication over master-originated clock line
US11119696B2 (en) Technique of register space expansion with branched paging
US20180181533A1 (en) Ending write data transfer in i3c hdr-ddr mode

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191023

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191023

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20201027

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20201130

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20210628