JP2018525825A - メモリデバイスのためのメタライゼーションプロセス - Google Patents

メモリデバイスのためのメタライゼーションプロセス Download PDF

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Publication number
JP2018525825A
JP2018525825A JP2018506392A JP2018506392A JP2018525825A JP 2018525825 A JP2018525825 A JP 2018525825A JP 2018506392 A JP2018506392 A JP 2018506392A JP 2018506392 A JP2018506392 A JP 2018506392A JP 2018525825 A JP2018525825 A JP 2018525825A
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Japan
Prior art keywords
metallization layer
metallization
mram
module
forming
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JP2018506392A
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English (en)
Japanese (ja)
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JP2018525825A5 (https=
Inventor
ユ・ル
スン・ヒョク・カン
Original Assignee
クアルコム，インコーポレイテッド
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Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2018525825A publication Critical patent/JP2018525825A/ja
Publication of JP2018525825A5 publication Critical patent/JP2018525825A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Materials of the active region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
JP2018506392A 2015-08-10 2016-07-11 メモリデバイスのためのメタライゼーションプロセス Pending JP2018525825A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/822,326 2015-08-10
US14/822,326 US10109674B2 (en) 2015-08-10 2015-08-10 Semiconductor metallization structure
PCT/US2016/041790 WO2017027148A1 (en) 2015-08-10 2016-07-11 Metallization process for a memory device

Publications (2)

Publication Number Publication Date
JP2018525825A true JP2018525825A (ja) 2018-09-06
JP2018525825A5 JP2018525825A5 (https=) 2019-07-18

Family

ID=56497906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018506392A Pending JP2018525825A (ja) 2015-08-10 2016-07-11 メモリデバイスのためのメタライゼーションプロセス

Country Status (8)

Country Link
US (1) US10109674B2 (https=)
EP (1) EP3304610B1 (https=)
JP (1) JP2018525825A (https=)
KR (1) KR20180040147A (https=)
CN (1) CN107924994B (https=)
AU (1) AU2016306123A1 (https=)
BR (1) BR112018002617B1 (https=)
WO (1) WO2017027148A1 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9799562B2 (en) * 2009-08-21 2017-10-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US10270025B2 (en) * 2015-12-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having magnetic tunneling junction (MTJ) layer
US10169520B2 (en) * 2016-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells
US9997456B2 (en) * 2016-07-27 2018-06-12 Globalfoundries Inc. Interconnect structure having power rail structure and related method
US10566519B2 (en) * 2017-08-18 2020-02-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a flat bottom electrode via (BEVA) top surface for memory
US10374005B2 (en) * 2017-12-29 2019-08-06 Globalfoundries Singapore Pte. Ltd. Density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology and method for producing the same
CN110648960B (zh) * 2018-06-27 2021-12-28 中电海康集团有限公司 Mram器件与其制作方法
CN110890460B (zh) * 2018-09-07 2023-06-30 联华电子股份有限公司 半导体元件及其制作方法
US11069853B2 (en) * 2018-11-19 2021-07-20 Applied Materials, Inc. Methods for forming structures for MRAM applications
US11476415B2 (en) 2018-11-30 2022-10-18 International Business Machines Corporation Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features
CN112447788B (zh) * 2019-09-03 2023-09-12 联华电子股份有限公司 磁阻式随机存取存储器
US11424403B2 (en) 2020-02-21 2022-08-23 International Business Machines Corporation Magnetoresistive random-access memory cell having a metal line connection

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004274016A (ja) * 2003-02-18 2004-09-30 Mitsubishi Electric Corp 磁気記憶半導体装置
JP2005303231A (ja) * 2004-04-16 2005-10-27 Sony Corp 磁気メモリ装置
JP2012043977A (ja) * 2010-08-19 2012-03-01 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
JP2012527129A (ja) * 2009-05-14 2012-11-01 クアルコム，インコーポレイテッド 磁気トンネル接合デバイスおよび製作

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EP0817269B1 (en) * 1996-06-28 2008-09-10 Texas Instruments Incorporated Wordline layout for semiconductor memory device
US6635496B2 (en) * 2001-10-12 2003-10-21 Infineon Technologies, Ag Plate-through hard mask for MRAM devices
US6794238B2 (en) 2001-11-07 2004-09-21 Micron Technology, Inc. Process for forming metallized contacts to periphery transistors
AU2003235298A1 (en) 2002-04-23 2003-11-10 Nec Corporation Magnetic memory and its operating method
US6783995B2 (en) * 2002-04-30 2004-08-31 Micron Technology, Inc. Protective layers for MRAM devices
US7031183B2 (en) 2003-12-08 2006-04-18 Freescale Semiconductor, Inc. MRAM device integrated with other types of circuitry
US7635884B2 (en) * 2005-07-29 2009-12-22 International Business Machines Corporation Method and structure for forming slot via bitline for MRAM devices
JP4406407B2 (ja) * 2006-03-13 2010-01-27 株式会社東芝 磁気ランダムアクセスメモリ
US7666578B2 (en) * 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8674465B2 (en) 2010-08-05 2014-03-18 Qualcomm Incorporated MRAM device and integration techniques compatible with logic integration
US9153981B2 (en) 2011-09-09 2015-10-06 Tyler Jon Back Electric power supply adapter device for electric golf cars and electric utility vehicles
US8772051B1 (en) * 2013-02-14 2014-07-08 Headway Technologies, Inc. Fabrication method for embedded magnetic memory
KR102099191B1 (ko) 2013-03-15 2020-05-15 인텔 코포레이션 내장된 자기 터널 접합을 포함하는 로직 칩
US9349772B2 (en) * 2014-04-25 2016-05-24 Globalfoundries Singapore Pte. Ltd. Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004274016A (ja) * 2003-02-18 2004-09-30 Mitsubishi Electric Corp 磁気記憶半導体装置
JP2005303231A (ja) * 2004-04-16 2005-10-27 Sony Corp 磁気メモリ装置
JP2012527129A (ja) * 2009-05-14 2012-11-01 クアルコム，インコーポレイテッド 磁気トンネル接合デバイスおよび製作
JP2012043977A (ja) * 2010-08-19 2012-03-01 Renesas Electronics Corp 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
US20170047374A1 (en) 2017-02-16
US10109674B2 (en) 2018-10-23
AU2016306123A1 (en) 2018-01-25
KR20180040147A (ko) 2018-04-19
WO2017027148A1 (en) 2017-02-16
EP3304610B1 (en) 2019-01-09
CN107924994A (zh) 2018-04-17
EP3304610A1 (en) 2018-04-11
BR112018002617B1 (pt) 2022-12-13
CN107924994B (zh) 2020-10-23
BR112018002617A2 (pt) 2018-10-02

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