JP2018525731A5 - - Google Patents
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- JP2018525731A5 JP2018525731A5 JP2018502231A JP2018502231A JP2018525731A5 JP 2018525731 A5 JP2018525731 A5 JP 2018525731A5 JP 2018502231 A JP2018502231 A JP 2018502231A JP 2018502231 A JP2018502231 A JP 2018502231A JP 2018525731 A5 JP2018525731 A5 JP 2018525731A5
- Authority
- JP
- Japan
- Prior art keywords
- destination
- source
- data elements
- register
- simd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/805,456 US10489155B2 (en) | 2015-07-21 | 2015-07-21 | Mixed-width SIMD operations using even/odd register pairs for wide data elements |
| US14/805,456 | 2015-07-21 | ||
| PCT/US2016/038487 WO2017014892A1 (en) | 2015-07-21 | 2016-06-21 | Mixed-width simd operations having even-element and odd-element operations using register pair for wide data elements |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018525731A JP2018525731A (ja) | 2018-09-06 |
| JP2018525731A5 true JP2018525731A5 (enExample) | 2020-02-20 |
| JP6920277B2 JP6920277B2 (ja) | 2021-08-18 |
Family
ID=56204087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018502231A Active JP6920277B2 (ja) | 2015-07-21 | 2016-06-21 | 広いデータ要素のためのレジスタのペアを用いた偶数要素演算および奇数要素演算を有する混合幅ｓｉｍｄ演算 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US10489155B2 (enExample) |
| EP (1) | EP3326060B1 (enExample) |
| JP (1) | JP6920277B2 (enExample) |
| KR (1) | KR102121866B1 (enExample) |
| CN (1) | CN107851010B (enExample) |
| BR (1) | BR112018001208B1 (enExample) |
| ES (1) | ES2795832T3 (enExample) |
| HU (1) | HUE049260T2 (enExample) |
| WO (1) | WO2017014892A1 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2540943B (en) * | 2015-07-31 | 2018-04-11 | Advanced Risc Mach Ltd | Vector arithmetic instruction |
| US10698685B2 (en) * | 2017-05-03 | 2020-06-30 | Intel Corporation | Instructions for dual destination type conversion, mixed precision accumulation, and mixed precision atomic memory operations |
| CN109298886A (zh) * | 2017-07-25 | 2019-02-01 | 合肥君正科技有限公司 | Simd指令执行方法、装置及处理器 |
| US20190272175A1 (en) * | 2018-03-01 | 2019-09-05 | Qualcomm Incorporated | Single pack & unpack network and method for variable bit width data formats for computational machines |
| US10528346B2 (en) | 2018-03-29 | 2020-01-07 | Intel Corporation | Instructions for fused multiply-add operations with variable precision input operands |
| CN111324354B (zh) * | 2019-12-27 | 2023-04-18 | 湖南科技大学 | 一种融合寄存器对需求的寄存器选择方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5673321A (en) | 1995-06-29 | 1997-09-30 | Hewlett-Packard Company | Efficient selection and mixing of multiple sub-word items packed into two or more computer words |
| US6202141B1 (en) | 1998-06-16 | 2001-03-13 | International Business Machines Corporation | Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors |
| US7127593B2 (en) * | 2001-06-11 | 2006-10-24 | Broadcom Corporation | Conditional execution with multiple destination stores |
| US6922716B2 (en) | 2001-07-13 | 2005-07-26 | Motorola, Inc. | Method and apparatus for vector processing |
| US7107305B2 (en) | 2001-10-05 | 2006-09-12 | Intel Corporation | Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions |
| KR100553252B1 (ko) * | 2002-02-01 | 2006-02-20 | 아바고테크놀로지스코리아 주식회사 | 휴대용 단말기의 전력 증폭 장치 |
| US7376812B1 (en) | 2002-05-13 | 2008-05-20 | Tensilica, Inc. | Vector co-processor for configurable and extensible processor architecture |
| US7668897B2 (en) | 2003-06-16 | 2010-02-23 | Arm Limited | Result partitioning within SIMD data processing systems |
| US7275148B2 (en) * | 2003-09-08 | 2007-09-25 | Freescale Semiconductor, Inc. | Data processing system using multiple addressing modes for SIMD operations and method thereof |
| GB2411975B (en) * | 2003-12-09 | 2006-10-04 | Advanced Risc Mach Ltd | Data processing apparatus and method for performing arithmetic operations in SIMD data processing |
| GB2409068A (en) * | 2003-12-09 | 2005-06-15 | Advanced Risc Mach Ltd | Data element size control within parallel lanes of processing |
| US7353244B2 (en) * | 2004-04-16 | 2008-04-01 | Marvell International Ltd. | Dual-multiply-accumulator operation optimized for even and odd multisample calculations |
| US7400271B2 (en) * | 2005-06-21 | 2008-07-15 | International Characters, Inc. | Method and apparatus for processing character streams |
| CN1964490A (zh) * | 2005-11-09 | 2007-05-16 | 松下电器产业株式会社 | 一种滤波器及滤波方法 |
| US9235414B2 (en) | 2011-12-19 | 2016-01-12 | Intel Corporation | SIMD integer multiply-accumulate instruction for multi-precision arithmetic |
| CN104011644B (zh) * | 2011-12-22 | 2017-12-08 | 英特尔公司 | 用于产生按照数值顺序的相差恒定跨度的整数的序列的处理器、方法、系统和指令 |
| US10628156B2 (en) | 2013-07-09 | 2020-04-21 | Texas Instruments Incorporated | Vector SIMD VLIW data path architecture |
-
2015
- 2015-07-21 US US14/805,456 patent/US10489155B2/en active Active
-
2016
- 2016-06-21 JP JP2018502231A patent/JP6920277B2/ja active Active
- 2016-06-21 HU HUE16732213A patent/HUE049260T2/hu unknown
- 2016-06-21 WO PCT/US2016/038487 patent/WO2017014892A1/en not_active Ceased
- 2016-06-21 ES ES16732213T patent/ES2795832T3/es active Active
- 2016-06-21 KR KR1020187001696A patent/KR102121866B1/ko active Active
- 2016-06-21 BR BR112018001208-4A patent/BR112018001208B1/pt active IP Right Grant
- 2016-06-21 CN CN201680041468.2A patent/CN107851010B/zh active Active
- 2016-06-21 EP EP16732213.0A patent/EP3326060B1/en active Active
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