KR102121866B1 - 와이드 데이터 엘리먼트들에 대한 레지스터 쌍을 사용하는 짝수-엘리먼트 및 홀수-엘리먼트 연산들을 가지는 혼합-폭 simd 연산들 - Google Patents

와이드 데이터 엘리먼트들에 대한 레지스터 쌍을 사용하는 짝수-엘리먼트 및 홀수-엘리먼트 연산들을 가지는 혼합-폭 simd 연산들 Download PDF

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KR102121866B1
KR102121866B1 KR1020187001696A KR20187001696A KR102121866B1 KR 102121866 B1 KR102121866 B1 KR 102121866B1 KR 1020187001696 A KR1020187001696 A KR 1020187001696A KR 20187001696 A KR20187001696 A KR 20187001696A KR 102121866 B1 KR102121866 B1 KR 102121866B1
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KR20180030986A (ko
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에릭 웨인 마후린
아제이 아난트 잉글
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
KR1020187001696A 2015-07-21 2016-06-21 와이드 데이터 엘리먼트들에 대한 레지스터 쌍을 사용하는 짝수-엘리먼트 및 홀수-엘리먼트 연산들을 가지는 혼합-폭 simd 연산들 Active KR102121866B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/805,456 US10489155B2 (en) 2015-07-21 2015-07-21 Mixed-width SIMD operations using even/odd register pairs for wide data elements
US14/805,456 2015-07-21
PCT/US2016/038487 WO2017014892A1 (en) 2015-07-21 2016-06-21 Mixed-width simd operations having even-element and odd-element operations using register pair for wide data elements

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KR20180030986A KR20180030986A (ko) 2018-03-27
KR102121866B1 true KR102121866B1 (ko) 2020-06-11

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US (1) US10489155B2 (enExample)
EP (1) EP3326060B1 (enExample)
JP (1) JP6920277B2 (enExample)
KR (1) KR102121866B1 (enExample)
CN (1) CN107851010B (enExample)
BR (1) BR112018001208B1 (enExample)
ES (1) ES2795832T3 (enExample)
HU (1) HUE049260T2 (enExample)
WO (1) WO2017014892A1 (enExample)

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GB2540943B (en) * 2015-07-31 2018-04-11 Advanced Risc Mach Ltd Vector arithmetic instruction
US10698685B2 (en) * 2017-05-03 2020-06-30 Intel Corporation Instructions for dual destination type conversion, mixed precision accumulation, and mixed precision atomic memory operations
CN109298886A (zh) * 2017-07-25 2019-02-01 合肥君正科技有限公司 Simd指令执行方法、装置及处理器
US20190272175A1 (en) * 2018-03-01 2019-09-05 Qualcomm Incorporated Single pack & unpack network and method for variable bit width data formats for computational machines
US10528346B2 (en) 2018-03-29 2020-01-07 Intel Corporation Instructions for fused multiply-add operations with variable precision input operands
CN111324354B (zh) * 2019-12-27 2023-04-18 湖南科技大学 一种融合寄存器对需求的寄存器选择方法

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US20050125476A1 (en) 2003-12-09 2005-06-09 Arm Limited Data processing apparatus and method for performing arithmetic operations in SIMD data processing
US20070033381A1 (en) 2001-06-11 2007-02-08 Broadcom Corporation Conditional execution with multiple destination stores

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US6202141B1 (en) 1998-06-16 2001-03-13 International Business Machines Corporation Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors
US6922716B2 (en) 2001-07-13 2005-07-26 Motorola, Inc. Method and apparatus for vector processing
US7107305B2 (en) 2001-10-05 2006-09-12 Intel Corporation Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
KR100553252B1 (ko) * 2002-02-01 2006-02-20 아바고테크놀로지스코리아 주식회사 휴대용 단말기의 전력 증폭 장치
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
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GB2409068A (en) * 2003-12-09 2005-06-15 Advanced Risc Mach Ltd Data element size control within parallel lanes of processing
US7353244B2 (en) * 2004-04-16 2008-04-01 Marvell International Ltd. Dual-multiply-accumulator operation optimized for even and odd multisample calculations
US7400271B2 (en) * 2005-06-21 2008-07-15 International Characters, Inc. Method and apparatus for processing character streams
CN1964490A (zh) * 2005-11-09 2007-05-16 松下电器产业株式会社 一种滤波器及滤波方法
CN107368286B (zh) 2011-12-19 2020-11-06 英特尔公司 用于多精度算术的simd整数乘法累加指令
US10866807B2 (en) * 2011-12-22 2020-12-15 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride
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US20070033381A1 (en) 2001-06-11 2007-02-08 Broadcom Corporation Conditional execution with multiple destination stores
US20050125476A1 (en) 2003-12-09 2005-06-09 Arm Limited Data processing apparatus and method for performing arithmetic operations in SIMD data processing

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BR112018001208A2 (pt) 2018-09-11
WO2017014892A1 (en) 2017-01-26
HUE049260T2 (hu) 2020-09-28
KR20180030986A (ko) 2018-03-27
BR112018001208B1 (pt) 2023-12-26
EP3326060A1 (en) 2018-05-30
US10489155B2 (en) 2019-11-26
EP3326060B1 (en) 2020-03-25
JP2018525731A (ja) 2018-09-06
CN107851010A (zh) 2018-03-27
ES2795832T3 (es) 2020-11-24
US20170024209A1 (en) 2017-01-26
JP6920277B2 (ja) 2021-08-18
CN107851010B (zh) 2021-11-12

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