JP6920277B2 - 広いデータ要素のためのレジスタのペアを用いた偶数要素演算および奇数要素演算を有する混合幅ｓｉｍｄ演算 - Google Patents

広いデータ要素のためのレジスタのペアを用いた偶数要素演算および奇数要素演算を有する混合幅ｓｉｍｄ演算 Download PDF

Info

Publication number
JP6920277B2
JP6920277B2 JP2018502231A JP2018502231A JP6920277B2 JP 6920277 B2 JP6920277 B2 JP 6920277B2 JP 2018502231 A JP2018502231 A JP 2018502231A JP 2018502231 A JP2018502231 A JP 2018502231A JP 6920277 B2 JP6920277 B2 JP 6920277B2
Authority
JP
Japan
Prior art keywords
data elements
destination
source
simd
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018502231A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018525731A5 (enExample
JP2018525731A (ja
Inventor
エリック・ウェイン・マハーアン
アジャイ・アナント・イングル
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2018525731A publication Critical patent/JP2018525731A/ja
Publication of JP2018525731A5 publication Critical patent/JP2018525731A5/ja
Application granted granted Critical
Publication of JP6920277B2 publication Critical patent/JP6920277B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
JP2018502231A 2015-07-21 2016-06-21 広いデータ要素のためのレジスタのペアを用いた偶数要素演算および奇数要素演算を有する混合幅ｓｉｍｄ演算 Active JP6920277B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/805,456 US10489155B2 (en) 2015-07-21 2015-07-21 Mixed-width SIMD operations using even/odd register pairs for wide data elements
US14/805,456 2015-07-21
PCT/US2016/038487 WO2017014892A1 (en) 2015-07-21 2016-06-21 Mixed-width simd operations having even-element and odd-element operations using register pair for wide data elements

Publications (3)

Publication Number Publication Date
JP2018525731A JP2018525731A (ja) 2018-09-06
JP2018525731A5 JP2018525731A5 (enExample) 2020-02-20
JP6920277B2 true JP6920277B2 (ja) 2021-08-18

Family

ID=56204087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018502231A Active JP6920277B2 (ja) 2015-07-21 2016-06-21 広いデータ要素のためのレジスタのペアを用いた偶数要素演算および奇数要素演算を有する混合幅ｓｉｍｄ演算

Country Status (9)

Country Link
US (1) US10489155B2 (enExample)
EP (1) EP3326060B1 (enExample)
JP (1) JP6920277B2 (enExample)
KR (1) KR102121866B1 (enExample)
CN (1) CN107851010B (enExample)
BR (1) BR112018001208B1 (enExample)
ES (1) ES2795832T3 (enExample)
HU (1) HUE049260T2 (enExample)
WO (1) WO2017014892A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2540943B (en) * 2015-07-31 2018-04-11 Advanced Risc Mach Ltd Vector arithmetic instruction
US10698685B2 (en) * 2017-05-03 2020-06-30 Intel Corporation Instructions for dual destination type conversion, mixed precision accumulation, and mixed precision atomic memory operations
CN109298886A (zh) * 2017-07-25 2019-02-01 合肥君正科技有限公司 Simd指令执行方法、装置及处理器
US20190272175A1 (en) * 2018-03-01 2019-09-05 Qualcomm Incorporated Single pack & unpack network and method for variable bit width data formats for computational machines
US10528346B2 (en) 2018-03-29 2020-01-07 Intel Corporation Instructions for fused multiply-add operations with variable precision input operands
CN111324354B (zh) * 2019-12-27 2023-04-18 湖南科技大学 一种融合寄存器对需求的寄存器选择方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673321A (en) 1995-06-29 1997-09-30 Hewlett-Packard Company Efficient selection and mixing of multiple sub-word items packed into two or more computer words
US6202141B1 (en) 1998-06-16 2001-03-13 International Business Machines Corporation Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors
US7127593B2 (en) * 2001-06-11 2006-10-24 Broadcom Corporation Conditional execution with multiple destination stores
US6922716B2 (en) 2001-07-13 2005-07-26 Motorola, Inc. Method and apparatus for vector processing
US7107305B2 (en) 2001-10-05 2006-09-12 Intel Corporation Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
KR100553252B1 (ko) * 2002-02-01 2006-02-20 아바고테크놀로지스코리아 주식회사 휴대용 단말기의 전력 증폭 장치
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7668897B2 (en) 2003-06-16 2010-02-23 Arm Limited Result partitioning within SIMD data processing systems
US7275148B2 (en) * 2003-09-08 2007-09-25 Freescale Semiconductor, Inc. Data processing system using multiple addressing modes for SIMD operations and method thereof
GB2411975B (en) * 2003-12-09 2006-10-04 Advanced Risc Mach Ltd Data processing apparatus and method for performing arithmetic operations in SIMD data processing
GB2409068A (en) * 2003-12-09 2005-06-15 Advanced Risc Mach Ltd Data element size control within parallel lanes of processing
US7353244B2 (en) * 2004-04-16 2008-04-01 Marvell International Ltd. Dual-multiply-accumulator operation optimized for even and odd multisample calculations
US7400271B2 (en) * 2005-06-21 2008-07-15 International Characters, Inc. Method and apparatus for processing character streams
CN1964490A (zh) * 2005-11-09 2007-05-16 松下电器产业株式会社 一种滤波器及滤波方法
US9235414B2 (en) 2011-12-19 2016-01-12 Intel Corporation SIMD integer multiply-accumulate instruction for multi-precision arithmetic
CN104011644B (zh) * 2011-12-22 2017-12-08 英特尔公司 用于产生按照数值顺序的相差恒定跨度的整数的序列的处理器、方法、系统和指令
US10628156B2 (en) 2013-07-09 2020-04-21 Texas Instruments Incorporated Vector SIMD VLIW data path architecture

Also Published As

Publication number Publication date
KR102121866B1 (ko) 2020-06-11
HUE049260T2 (hu) 2020-09-28
WO2017014892A1 (en) 2017-01-26
US20170024209A1 (en) 2017-01-26
CN107851010A (zh) 2018-03-27
CN107851010B (zh) 2021-11-12
EP3326060B1 (en) 2020-03-25
BR112018001208A2 (pt) 2018-09-11
JP2018525731A (ja) 2018-09-06
ES2795832T3 (es) 2020-11-24
BR112018001208B1 (pt) 2023-12-26
EP3326060A1 (en) 2018-05-30
KR20180030986A (ko) 2018-03-27
US10489155B2 (en) 2019-11-26

Similar Documents

Publication Publication Date Title
JP6920277B2 (ja) 広いデータ要素のためのレジスタのペアを用いた偶数要素演算および奇数要素演算を有する混合幅ｓｉｍｄ演算
CN107408041B (zh) 用于图像处理器的能量高效的处理器核心架构
JP6373425B2 (ja) 複数のビットを左にシフトし、複数の１を複数の下位ビットにプルインするための命令
TWI752343B (zh) 用於執行絕對差計算之加總的執行單元電路、影像處理器以及方法
CN107533460B (zh) 紧缩有限冲激响应（fir）滤波处理器、方法、系统和指令
CN103109261B (zh) 用于通用逻辑操作的方法和设备
CN107851013B (zh) 数据处理装置和方法
WO2015114305A1 (en) A data processing apparatus and method for executing a vector scan instruction
CN104838357A (zh) 瓦解的多嵌套循环的向量化
US20220206796A1 (en) Multi-functional execution lane for image processor
CN107851016B (zh) 向量算术指令
WO2009131007A1 (ja) Ｓｉｍｄ型並列計算機システム、ｓｉｍｄ型並列計算方法及び制御プログラム

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180123

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190605

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200108

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20200108

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200514

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20200611

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200622

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200923

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20201221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210413

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20210413

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20210423

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20210426

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210705

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210726

R150 Certificate of patent or registration of utility model

Ref document number: 6920277

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250