JP2018206867A - Group iii nitride semiconductor device and manufacturing method of the same - Google Patents

Abstract

To provide a group III nitride semiconductor transistor and a manufacturing method of the same, which can reduce defects on a surface of a group III nitride semiconductor such as GaN to improve On-state current of the transistor.SOLUTION: Improvement of performance in a transistor is achieved by heating a group II nitride semiconductor while supplying nitrogen radicals to reduce surface defects caused by nitrogen vacancy and subsequently, performing formation of a gate insulation film and formation of a group III nitride semiconductor film to be source and drain regions. Alternatively, On-state current of the transistor can be improved by reducing contact resistance between the source and drain regions and the electrode.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a group III nitride semiconductor device, and more particularly to an FET using a group III nitride semiconductor and a method for manufacturing the same.

Group III nitride wide gap semiconductors typified by GaN are being applied to power devices that require high output and high voltage operation because of their high breakdown voltage and high electron mobility. A representative example of such a power device is a field effect transistor (FET) using a group III nitride semiconductor.
The problem with insulated gate FETs using group III nitride semiconductors is that the vapor pressure of nitrogen is high and nitrogen escape is likely to occur, so it is difficult to form a gate insulating film with a low interface state with the group III nitride semiconductor surface. Therefore, instability of the threshold voltage (Vth shift) and increase in the leakage current between the source and the drain are likely to occur, and further, the common problem of the FET is that the contact resistance with the source and drain regions of the group III nitride semiconductor is reduced. It is difficult.

For example, as a FET using a GaN-based semiconductor, Patent Document 1 discloses a method for manufacturing a high-performance insulated gate FET by forming a silicon nitride film on GaN by plasma-free by the CAT-CVD method. Yes.
In addition, Patent Document 2 discloses MOCVD without performing recess etching in order to reduce the contact resistance between the source / drain regions and the electrodes of Schottky gate type and insulated gate type AlGaN / GaN-HEMTs using a GaN-based semiconductor. A technique for realizing ohmic contact by selectively re-growing an n + GaN layer on an AlGaN layer in a source / drain region by a method and forming an electrode on the n + GaN layer is disclosed. Since the recess etching is not performed, there is no etching damage, a good n + GaN layer can be formed, and the contact resistance is reduced.

  As described above, a transistor using a GaN-based semiconductor has the above-described problems, and it is particularly difficult to achieve both a realization of a normally-off transistor that suppresses a source-drain leakage current and an increase in on-current. . For example, Patent Document 3 discloses a technique for forming nickel oxide (NiO) in a gate region as a solution for resolving these problems. Non-Patent Documents 2 and 3 also disclose gate electrode structures using NiO films.

JP 2008-103408 A JP 2008-124262 A WO2014 / 020809

M.M. H. Kim, et al. "Investigation of the initial stage of GaN epitaxial growth on 6H-SiC6H-SiC (0001) at room temperature", Appl. Phys. Lett. 89, 031916 (2006) N. Kaneko, et al. "Normally-off AlGaN / GaN HFETs using NiOx gate with recess", IEEE ISPSD, pp. 25-28, 2009. A. Suzuki, et al, “NiO gate GaN-based enhancement-mode heterojunction field-effect transistor with extremal low-resistive use of metallogenous energy. 55, Num. 12

As described above, although a technique for preventing damage on the surface of the group III nitride has been developed, further improvement is necessary to realize a high-performance FET.
That is, GaN is prone to nitrogen desorption (nitrogen desorption), and there is a problem that defects due to nitrogen vacancies generated in the manufacturing process may exist in the vicinity of the GaN surface, but the conventional technology does not consider this problem. Therefore, this problem cannot be solved.

  In the above-mentioned patent document 1, it is said that plasma damage to the underlying GaN layer can be eliminated by forming a plasma-free film. However, defects near the surface generated in the previous process are not considered. CAT-CVD promotes the decomposition of the source gas by the catalytic action of the metal surface, but is basically thermal CVD and cannot solve the problem of nitrogen desorption due to the heat treatment of GaN.

  Patent Document 2 can eliminate plasma damage due to recess etching of a group III nitride substrate. However, in the actual manufacturing process, when the silicon oxide film on the AlGaN layer is dry-etched for the purpose of forming a mask for selective regrowth, overetching is inevitable in order to cope with the film thickness variation of the silicon oxide film. . Therefore, it is difficult to avoid plasma damage to the outermost surface of the AlGaN layer. Furthermore, since MOCVD selectively grows GaN at a high temperature of 1000 ° C. or higher, nitrogen gas is desorbed from the GaN surface in the process of stopping the supply of source gas and cooling the high-temperature group III nitride semiconductor substrate to room temperature. And crystal defects due to nitrogen vacancies cannot be prevented.

  By using MOMBE using an organic metal gas source instead of MOCVD, selective growth at a relatively low substrate temperature is possible. However, even when MOMBE is used, the substrate temperature is 800 [° C.] or more, and the problem of crystal defects due to nitrogen desorption cannot be solved.

  In addition, a processing method for recovering crystal defects on the surface of the group III nitride semiconductor generated in the manufacturing process is not disclosed in any patent document. When heat treatment is performed to recover crystal defects, there is a problem that defects due to nitrogen desorption are newly generated.

  As described above, the problem of the gate insulating film of the group III nitride semiconductor and the problem of the contact resistance with the group III nitride semiconductor cited in Patent Documents 1 and 2 are considered for crystal defects due to nitrogen desorption. No technology has been developed that can solve this crystal defect problem.

  Further, the NiO film described in Patent Document 3 can increase the hole concentration by the oxidation heat treatment and obtain good normally-off characteristics, but the group III nitride resulting from the substrate oxidation and nitrogen desorption by the oxidation heat treatment. There is a risk of increasing crystal defects on the semiconductor surface. Therefore, advanced techniques for adjusting temperature, oxygen partial pressure, etc. are required. In addition, when the opening of the insulator protective film layer in the gate region is performed by a dry etching method, there is a risk that plasma damage may occur on the surface of the group III nitride semiconductor. However, when the dry etching method is used, The patent document 3 does not disclose a method for avoiding or repairing damage.

  In view of the above problems, an object of the present invention is to provide a high-performance group III nitride semiconductor device and a method for manufacturing the same while suppressing crystal defects near the surface of the group III nitride semiconductor.

A method for manufacturing a semiconductor device according to the present invention includes:
It includes a step of performing a nitrogen radical treatment for heating a substrate having a group III nitride semiconductor on the surface while irradiating the surface of the substrate with nitrogen radicals.

  In this way, by heating while irradiating nitrogen radicals with the group III nitride semiconductor exposed on the surface, generation of defects due to nitrogen desorption on the group III nitride semiconductor surface, which has been a conventional problem, is prevented. Further, even when a crystal defect due to nitrogen desorption occurs on the surface of the group III nitride semiconductor in the manufacturing process of the semiconductor device, the defect can be repaired. As a result, the crystal surface of the group III nitride semiconductor for manufacturing a high-performance semiconductor device can be easily obtained.

A method for manufacturing a semiconductor device according to the present invention includes:
The semiconductor device is a transistor,
A first step of performing the nitrogen radical treatment;
After the first step, a silicon nitride film is formed on the substrate surface by a PLD method using silicon as a target while continuously irradiating the surface of the substrate with nitrogen radicals, thereby forming a gate insulating film. And the process of
A third step of forming a gate electrode on the silicon nitride film;
And a fourth step of removing the silicon nitride film on regions to be a source region and a drain region and forming a source electrode and a drain electrode.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
The gate electrode formed in the third step is made of metal.

By setting it as the manufacturing method of such a semiconductor device,
Since silicon nitride, which is a gate insulating film, is formed after preventing surface crystal defects due to nitrogen desorption of group III nitride semiconductors, a gate insulating film with few interface states can be formed, and the transistor is stable. Operation can be realized.
In particular, by irradiating a heated substrate with nitrogen radicals, crystal defects can be repaired effectively.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
In the third step, the NiO film containing Ag is formed by the PLD method in an oxygen atmosphere using Ag or Ag oxynitride and Ni or Ni oxynitride as a target mixed on the silicon nitride film. A NiO film and an Ag oxide film by a PLD method in an oxygen atmosphere targeting Ni or Ni oxynitride and a PLD method in an oxygen atmosphere targeting Ag or Ag oxynitride Forming a laminated film with
A step of forming a p-type NiO film by heat-treating the NiO film containing Ag or a stacked film of the NiO film and an Ag oxide film in an oxygen atmosphere at a temperature of 200 [° C.] or higher;
And patterning the p-type NiO film to form a gate electrode.

In this manner, the hole concentration in the NiO film can be increased by heat-treating the NiO film at a temperature of 200 [° C.] or higher in an oxygen atmosphere. It is also possible to obtain the same effect by raising the substrate temperature during PLD film formation in an oxygen atmosphere to 200 [° C.] or higher.
In either case, the underlying silicon nitride film can effectively prevent the group III nitride semiconductor surface from being oxidized, and nitrogen desorption (defects or deep levels) can also occur on the group III nitride semiconductor surface. Therefore, it is possible to easily prevent the interface state from increasing.
Furthermore, by introducing Ag as a p-type dopant into the NiO film, the hole concentration can be controlled by the content (concentration) of Ag by increasing the hole concentration.
The work function of the NiO film formed on the gate insulating film is controlled by the Ag concentration, the Ag concentration is increased, and the hole concentration is increased so that the work function has a band of electron affinity 2.5 [eV] and NiO. The gap energy can be close to 4.0 [eV].
As a result, a gate electrode having a high work function can be formed, and an enhancement type FET can be provided.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
In the step of patterning the p-type NiO film and forming a gate electrode,
It includes a step of etching the p-type NiO film by immersing the substrate in a mixed solution containing concentrated sulfuric acid and hydrogen peroxide solution at a temperature of 60 [° C.] or higher.

By setting it as the manufacturing method of such a semiconductor device,
The p-type NiO film, which has been difficult to etch, can be etched by the wet etching method, and the gate electrode made of the p-type NiO film can be patterned at a low cost.

A method for manufacturing a semiconductor device according to the present invention includes:
The semiconductor device is a transistor,
A first step of forming an etching mask having openings in regions serving as a source region and a drain region on a substrate having a group III nitride semiconductor on the surface;
A second step of etching the regions to be the source region and the drain region of the substrate using the etching mask as a mask;
A third step of performing the nitrogen radical treatment;
After the third step, an n-type group III nitride semiconductor is converted into the source region and the drain region by a PLD method targeting a group III element containing a group IV element while continuously irradiating nitrogen radicals. A fourth step of epitaxially growing the region;
And a fifth step of forming a conductive film on the epitaxially grown n-type group III nitride semiconductor.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
The fifth step is a step of forming 12CaO.7Al ₂ O ₃ (hereinafter referred to as “C12A7 film”) on the substrate by a PLD method;
Forming a film containing Ti on the substrate;
And a step of heat-treating the substrate in a vacuum at a temperature of 200 [° C.] or higher.

By setting it as the manufacturing method of such a semiconductor device,
A group III nitride semiconductor containing an n-type dopant can be regrown while suppressing crystal defects on the group III nitride semiconductor of the substrate, and the regrown n-type group III nitride semiconductor and the substrate The contact resistance (contact resistance) and the contact resistance between the n-type group III nitride semiconductor and the electrode (contact electrode) are reduced, and a high-performance transistor can be provided.
In particular, the PLD method can effectively prevent nitrogen desorption compared to the film formation by the MBE method or the MOCVD method. The substrate temperature is 1000 [° C.] or higher in the MOCVD method used for forming a group III nitride semiconductor, and the substrate temperature is 800 [° C.] or higher even in the MBE method capable of forming a film at a relatively low temperature. is there. However, as described in Non-Patent Document 1, the PLD method allows group III nitride semiconductor crystals to grow even when the substrate temperature is 700 [° C.] or even 500 [° C.] or less. Therefore, the substrate temperature can be lowered as compared with the MBE method and the MOCVD method, and nitrogen desorption can be prevented.
In addition, the C12A7 film can be effectively reduced by performing heat treatment at 200 [° C.] or higher continuously after forming Ti. As a result, the contact resistance can be further reduced by using the C12A7 film as a contact electrode in ohmic contact with the n-type group III nitride semiconductor.
In the present specification, 12CaO · 7Al ₂ O ₃ known as electride may be referred to as C12A7, which is a general notation.

A method for manufacturing a semiconductor device according to the present invention includes:
The semiconductor device is a transistor,
A first step of forming an etching mask having a region serving as a source region and a drain region on a substrate having a group III nitride semiconductor on the surface; and the source region and the drain of the substrate using the etching mask as a mask A second step of etching a region to be a region;
A third step of performing the nitrogen radical treatment;
After the third step, a p-type group III nitride semiconductor is formed in the source region and the drain region by a PLD method using a group III element containing Mg as a target while continuously irradiating nitrogen radicals. A fourth step of epitaxially growing
A fifth step of forming a source electrode and a drain electrode on the epitaxially grown p-type group III nitride semiconductor;
It is characterized by including.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
In the fifth step, a NiO film containing Ag is formed on the substrate by a PLD method using NiO containing Ag as a target, or a PLD method using NiO as a target and a PLD method using Ag as a target. Forming a laminated film of NiO and Ag by:
Heat treating the substrate in an oxygen atmosphere at a temperature of 200 ° C. or higher to form a NiO film containing Ag or a stacked film of NiO and Ag as a p-type NiO film;
Patterning the p-type NiO film and leaving it on the epitaxially grown p-type group III nitride semiconductor;
It is characterized by including.

With such a method for manufacturing a semiconductor device, a group III nitride semiconductor containing a p-type dopant can be regrown while suppressing crystal defects on the group III nitride semiconductor of the substrate. As a result, the contact resistance (contact resistance) between the regrown p-type group III nitride semiconductor and the substrate and the contact resistance between the p-type group III nitride semiconductor and the electrode are reduced, and a high-performance transistor is provided. Can do.
Further, the contact resistance can be further reduced by using the p-type NiO film as a contact electrode in contact with the p-type group III nitride semiconductor.

A method for manufacturing a semiconductor device according to the present invention includes:
After the fourth step, the substrate is immersed in a TMAH (tetramethylammonium hydroxide) solution at 50 [° C.] or higher.

By employing such a semiconductor device manufacturing method, the etching mask can be easily removed.
This is because TMAH has the characteristics that the etching rate for the c-plane of the GaN crystal is low and the etching rate for the a-plane and m-plane is high. That is, the epitaxially grown GaN does not progress in etching, and the polycrystalline GaN film deposited on the etching mask includes various crystal planes, so that the etching proceeds preferentially. As a result, the lower etching mask is easily exposed and easily removed with hydrofluoric acid or the like.

A method for manufacturing a semiconductor device according to the present invention includes:
The semiconductor device is a transistor,
Etching at least a region serving as a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor; A first step of exposing one group III nitride semiconductor;
A second step of performing the nitrogen radical treatment;
After the second step, the n-type having a smaller electron affinity than the first group III nitride semiconductor is formed on the exposed first group III nitride semiconductor while continuously irradiating nitrogen radicals. A third step of forming a third group III nitride semiconductor by a PLD method;
And a fourth step of forming a contact electrode on the third group III nitride semiconductor.

  Thus, by recovering crystal defects by heating in nitrogen radicals and re-growing the group III nitride semiconductor in the source region while suppressing the generation of defects by the PLD method, electrons are transferred from the source region to the channel region. When injected, an n-channel transistor capable of increasing the speed of electrons and increasing the on-current can be easily manufactured.

A method for manufacturing a semiconductor device according to the present invention includes:
The semiconductor device is a transistor,
Etching at least a region to be a drain region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor; A first step of exposing one group III nitride semiconductor;
A second step of performing the nitrogen radical treatment;
After the second step, the n-type having higher electron affinity than the first group III nitride semiconductor is formed on the exposed first group III nitride semiconductor while continuously irradiating nitrogen radicals. A third step of forming a fourth group III nitride semiconductor by a PLD method;
And a fourth step of forming a contact electrode on the third group III nitride semiconductor.

  In this way, electrons are transferred from the channel region to the drain region by recovering crystal defects by heating in nitrogen radicals and re-growing the group III nitride semiconductor in the drain region while suppressing the generation of defects by the PLD method. When injected, an n-channel transistor capable of increasing the speed of electrons and increasing the on-current can be easily manufactured.

A method for manufacturing a semiconductor device according to the present invention includes:
The semiconductor device is a transistor,
Etching a region to be a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor; A first step of exposing the group III nitride semiconductor of
A second step of performing the nitrogen radical treatment;
After the second, while irradiating nitrogen radicals continuously, on the exposed first group III nitride semiconductor, an n-type third having a lower electron affinity than the first group III nitride semiconductor. A third step of forming the group III nitride semiconductor of PLD by the PLD method;
Etching a region to be a drain region of the substrate to expose the first group III nitride semiconductor;
A fifth step of performing the nitrogen radical treatment;
After the fifth, an n-type fourth having a higher electron affinity than the first group III nitride semiconductor is formed on the exposed group III nitride semiconductor while continuously irradiating nitrogen radicals. A sixth step of forming the group III nitride semiconductor of PLD by the PLD method;
And a seventh step of forming a contact electrode on the third group III nitride semiconductor and the fourth group III nitride semiconductor.

  With such a method of manufacturing a semiconductor device, when electrons are injected from the source region to the channel region, the speed of the electrons increases, and when electrons are injected from the channel region to the drain region, By increasing the electron velocity, an n-channel transistor that can further increase the on-state current can be provided.

A method for manufacturing a semiconductor device according to the present invention includes:
The step of forming the contact electrode includes a step of forming a metal or a C12A7 film by a PLD method, a step of forming Ti by a PLD method, and a step of heating the substrate in a vacuum.
It is characterized by including in this order.

  By adopting such a method for manufacturing a semiconductor device, the contact resistance between the source and drain regions and the contact electrode is reduced, and the performance of the n-channel transistor is improved.

A method for manufacturing a semiconductor device according to the present invention includes:
The PLD method is a PLD method using a pulse laser having a pulse width on the order of picoseconds.

In the PLD method, by using a pulse laser having a pulse width on the order of picoseconds, it is possible to form a film having good flatness and a crystallinity good in a group III nitride semiconductor at a low temperature of 500 ° C. or lower. Is possible. Thereby, generation | occurrence | production of the crystal defect by nitrogen detachment | desorption can also be suppressed effectively.
In this specification, it means a PLD method using a pulse laser having a pulse width on the order of picoseconds, that is, a pulse laser having a width of 1 picosecond or more and 1000 picoseconds or less.

The transistor according to the present invention is
A transistor using a group III nitride semiconductor,
A gate insulating film made of a silicon nitride film is provided on the group III nitride semiconductor,
An NiO gate electrode containing Ag is provided on the gate insulating film.

  By using the transistor having such a structure, a gate electrode having a large work function can be realized by controlling the concentration of Ag in the NiO film, and an enhancement type transistor that has been difficult to manufacture can be provided. .

The transistor according to the present invention is
An n-channel transistor using a group III nitride semiconductor, comprising an n-type group III nitride semiconductor epitaxially grown in a source region and a drain region,
An electrode is provided on the epitaxially grown n-type group III nitride semiconductor,
The electrode includes a C12A7 film in contact with the epitaxially grown n-type group III nitride semiconductor.

  With the transistor having such a structure, contact resistance between the n-type group III nitride semiconductor in the source region and the drain region and the electrode can be reduced, and the on-state current of the n-channel transistor can be improved.

The transistor according to the present invention is
A p-channel transistor using a group III nitride semiconductor, comprising a p-type group III nitride semiconductor epitaxially grown in a source region and a drain region,
An electrode is provided on the epitaxially grown p-type group III nitride semiconductor,
The electrode includes an NiO film containing Ag in contact with the epitaxially grown p-type group III nitride semiconductor.

  With the transistor having such a structure, contact resistance between the p-type group III nitride semiconductor in the source region and the drain region and the electrode can be reduced, and the on-current of the p-channel transistor can be improved.

The transistor according to the present invention is
An n-channel transistor using a group III nitride semiconductor,
A channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor;
The source region in contact with the channel region has a third group III nitride semiconductor containing an n-type impurity having an electron affinity smaller than that of the first group III nitride semiconductor.
The third group III nitride semiconductor is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor.

  With the transistor having such a structure, when electrons are injected from the source region to the channel region, the speed of the electrons is increased and the on-state current of the transistor can be improved.

The transistor according to the present invention is
An n-channel transistor using a group III nitride semiconductor,
A channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor;
The drain region in contact with the channel region has a fourth group III nitride semiconductor containing an n-type impurity having an electron affinity larger than that of the first group III nitride semiconductor.
The fourth group III nitride semiconductor is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor.

With the transistor having such a structure, when electrons are injected from the channel region to the drain region, the speed of the electrons is increased and the on-state current of the transistor can be improved.
The regrowth source and drain regions are not limited to high-concentration Ge-doped GaN, but can be replaced with high-concentration Ge-doped AlGaN or high-concentration Ge-doped InGaN. Alternatively, the source region and the drain region can be replaced with group III nitride semiconductors having different band gaps. In this case, when electrons move from a group III nitride semiconductor with a large band gap to a group III nitride semiconductor with a small band gap, the effect of increasing the speed of the electrons can be obtained. become.

  According to the transistor using the group III nitride semiconductor of the present invention and the manufacturing method thereof, the crystal defects on the surface of the group III nitride semiconductor are suppressed, and the gate insulating film and the source / drain regions and the electrode having a low interface state are formed. A low-resistance contact can be realized, and a high-performance transistor can be obtained.

The conceptual diagram of the film-forming apparatus used for manufacture of the semiconductor device of this invention. Sectional drawing which shows the main manufacturing processes of Embodiment 1. FIG. Sectional drawing which shows the main manufacturing processes of Embodiment 1. FIG. The graph which shows the characteristic of an insulated gate transistor. Sectional drawing which shows the main manufacturing processes of Embodiment 2. FIG. The surface SEM photograph of the formed group III nitride semiconductor. Sectional drawing which shows the main manufacturing processes of Embodiment 2. FIG. Sectional drawing which shows the main manufacturing processes of Embodiment 3. FIG. Sectional drawing which shows the main manufacturing processes of Embodiment 3. FIG. Sectional drawing which shows the main manufacturing processes of Embodiment 3. FIG. Sectional drawing which shows the main manufacturing processes of Embodiment 4. FIG. Sectional drawing which shows the main manufacturing processes of Embodiment 5. FIG. Sectional drawing which shows the main manufacturing processes of Embodiment 5. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, none of the following embodiments gives a limited interpretation in the recognition of the gist of the present invention. The same or similar members are denoted by the same reference numerals, and the description thereof may be omitted.

  For the sake of simplicity, in the following description, GaN, AlGaN, and the like will be described as examples of group III nitride semiconductors, but the present invention is not limited to GaN and AlGaN. For example, a mixed crystal of InN, GaN, AlN, BN, etc. is also included in the group III nitride semiconductor.

(Embodiment 1)
FIG. 1 is a conceptual diagram showing a main configuration of a film forming apparatus used for manufacturing a group III nitride semiconductor device of the present invention.

  This film forming apparatus irradiates the surface of a target made of a film forming material with a pulsed laser by a PLD (PLD: Pulsed Laser Deposition) method, evaporates (ablates) the material, and forms a film on the substrate (hereinafter referred to as a film forming apparatus). , Referred to as a PLD device).

The PLD apparatus includes a substrate support device 2 and a target support device 3 inside a chamber 1 that is an airtight vacuum vessel. On the substrate support apparatus 2, a substrate 4 as an object for forming a film is placed.
The substrate 4 is exemplified by a circular wafer having a GaN layer on the surface, but is not limited thereto.

  The substrate supporting device 2 can heat the substrate 4 by a built-in heating device and can maintain the substrate 4 at a constant temperature.

On the target support device 3, a target container 5a is supported. The target container 5a stores a target 6a that is a film forming material. Therefore, the target support device 3 supports the target 6a via the target container 5a.
In addition, the target support device 3 includes a temperature control device. The temperature control device includes a heating or cooling device, and can maintain the temperature of the target 6a at a constant temperature via the target container 5a.

A plurality of target containers can be provided in the chamber 1. FIG. 1 shows an example in which different targets 6a and 6b are stored in two target containers 5a and 5b, respectively. Therefore, it is possible to continuously form a plurality of different types of films.
Note that the number of target containers is not limited to two, but may be more or one.

The chamber 1 includes a light transmission window 7 for introducing laser light. The pulsed laser emitted from the laser irradiation device 8 installed outside the chamber 1 is collected by the lens 9, introduced into the chamber 1 through the light transmission window 7, and irradiated onto the target 6a.
As will be described later, the frequency of the laser pulse is set to be equal to or higher than a threshold of a repetition frequency that can maintain continuous excitation on the film forming material on the surface of the target 6a.
By setting the pulse width of the laser pulse to the picosecond order, a film having a flat surface can be stably formed.
When the pulse width exceeds the nanosecond order, it evaporates due to the thermal process, and the crystallinity deteriorates. When the pulse width falls below the femtosecond order, the target material comes in a cluster and the flatness deteriorates.
The center wavelength of the pulsed laser and the energy of one pulse can be 1064 [nm] and 50 [μJ], respectively, but are not limited thereto. In addition, the laser irradiation area (spot) diameter on the target 6a is focused to, for example, 100 [μm] or less, but is not limited thereto.

  The film forming material evaporates at the location irradiated with the laser beam on the surface of the target 6a. The film forming material released from the surface of the target 6 a forms a plume 11, and a film is formed by the film forming material that has reached the opposing substrate 4.

The chamber 1 includes a gas introduction port 12 and an exhaust port 13, and pressure control and atmosphere control are possible.
A vacuum pump is connected to the exhaust port 13 so that the inside of the chamber 1 can be exhausted and kept in a vacuum state.

  An atmosphere control gas can be introduced from the gas inlet 12 as necessary. The pressure inside the chamber 1 can be kept constant by controlling the opening of an APC (Auto Pressure Controller) valve installed between the exhaust port 13 and the vacuum pump and the number of rotations of the vacuum pump.

In addition, this apparatus has a load lock chamber for substrate replacement in order to prevent unnecessary oxidation of the target surface, and a turbo molecular pump is used for exhausting the film formation chamber 1 to provide base pressure. Can be 10 ⁻⁵ [Pa] or less.
Furthermore, the nitrogen gas to be used is a high-purity gas corresponding to a semiconductor. For example, a gas purifier is used, and a gas having an oxygen concentration of 1 [ppb] or less is particularly preferably used.

Further, the chamber 1 is provided with a radical irradiation device 14, for example, a radical gun.
The radical irradiation device 14 is supplied with nitrogen gas whose flow rate is controlled by an MFC (mass flow controller), for example, 2 [sccm] nitrogen (N ₂ ) gas, and is supplied with high frequency power, for example, 13.56 [MHz]. . The radical irradiation device 14 generates nitrogen radicals 18 from nitrogen gas by the supplied power energy, and irradiates the generated nitrogen radicals 18 on the surface of the substrate 4 from the nozzle 15 which is an outlet. Since nitrogen radicals are active, they have a nitriding action on the surface of the substrate 4 and the film forming material that has come from the target 6 a to the substrate 4.
Note that the frequency of the applied power is not limited to the above.

Hereinafter, a method of manufacturing a group III nitride semiconductor device using the present PLD device will be described with reference to FIGS.
2 and 3 are sectional views showing main manufacturing steps of the insulated gate FET according to this embodiment.

For simplicity, one semiconductor transistor is drawn on the drawing, but a plurality of transistors may be formed on the group III nitride semiconductor substrate. Similarly, although an isolation region for isolating a plurality of transistors is also omitted in the drawing, an inactive region by ion implantation may be provided as an element isolation region, or a trench embedded with an insulating film may be provided. For example, in FIGS. 2 and 3, an element isolation region may be formed at a position perpendicular to the paper surface.
Ion implantation for element isolation is performed using a photoresist mask, for example, with N (nitrogen), Fe (iron), and Zn (zinc) ions under the conditions of an acceleration voltage of 100 [keV] and a dose of 10 ¹⁵ [/ cm ² ]. It can be carried out.

First, as a group III nitride semiconductor substrate, a first group III nitride semiconductor layer 21, for example, a GaN layer is formed on a support substrate such as a (111) plane silicon substrate, a C plane silicon carbide, or a Ga plane GaN template substrate. A substrate 20 on which a second group III nitride semiconductor layer 22, for example, Al _0.15 Ga _0.85 N is epitaxially grown to about 10 [nm] is prepared by epitaxial growth of about [μm].
The first group III nitride semiconductor layer 21 and the second group III nitride semiconductor layer 21 and the second group III nitride semiconductor layer 22 are combined as described above, so that the first group III nitride semiconductor layer 21 and the second group III nitride The physical semiconductor layer 22 forms a heterojunction, and two-dimensional electrons are formed in the vicinity of the heterojunction interface.

  In the following, the second group III nitride semiconductor layer 22 is formed on the first group III nitride semiconductor layer 21, and at least in the region where the gate insulating film is formed or the channel region of the field effect transistor, the second group III nitride semiconductor layer 22 is formed. Although the substrate 20 with the group III nitride semiconductor layer 2 exposed is described, the present invention is not limited thereto. The substrate may be a substrate in which the group III nitride semiconductor layer is further formed in multiple layers or a substrate composed of a single layer of the group III nitride semiconductor layer.

As shown in FIG. 2A, in the PLD apparatus 1 shown in FIG. 1, the substrate 20 is supported by the substrate support apparatus 2 and irradiated with the nitrogen radicals 23 generated by the radical irradiation apparatus 14 at a predetermined temperature. And a time, for example, at a temperature of 200 [° C.] or higher for 1 [min] or longer.
Note that the above holding conditions are exemplary, and the temperature and time are determined in accordance with the state of crystal defects in the substrate 20. The crystal state of the surface can be confirmed by, for example, reflection high-energy electron diffraction (RHEED). Therefore, an analyzer such as RHEED may be incorporated in the PLD device 1.

  For example, when nitrogen vacancies exist near the surface of the second group III nitride semiconductor layer 22 due to possible damage in the manufacturing process, for example, the second group III nitride semiconductor layer 22 exposed to the substrate 20 is used. Since the nitrogen radicals 23 irradiated to the surface of the substrate are active nitrogen, they react to fill the nitrogen vacancies. Further, heating the substrate 20 promotes the reaction of nitrogen radicals and effectively recovers crystal defects near the surface.

  Note that when heating is performed to recover crystal defects of a GaN-based crystal, nitrogen may be desorbed from the surface and new crystal defects may be generated. However, by heating the substrate 20 while irradiating the nitrogen radicals 23 as in the present embodiment, the generation of crystal defects due to nitrogen desorption from the surface can be prevented while recovering the crystal defects.

  Next, as shown in FIG. 2B, the evaporated silicon is supplied to the surface of the substrate 20 by the PLD method using silicon (Si) as a target while continuing the irradiation of the nitrogen radicals 23 onto the substrate 20. . On the surface of the substrate 20, Si and nitrogen radicals react to form a silicon nitride film 24, for example, a film thickness of 20 nm, serving as a gate insulating film on the second group III nitride semiconductor layer 22. The At this time, in order to promote the reaction between silicon and nitrogen, the temperature of the substrate 20 is set to 200 [° C.], for example.

Thus, after recovering the crystal defects while preventing nitrogen detachment from the surface of the second group III nitride semiconductor layer 22, the second group III nitride is formed to continuously form the silicon nitride film. Generation of interface states between the semiconductor layer 22 and the silicon nitride film 24 can be suppressed.
Further, the nitrogen radical is continuously supplied at a substrate temperature of 200 [° C.] or higher without interruption between the process shown in FIG. 2A and the silicon nitride film forming process shown in FIG. By continuing to do so, nitrogen desorption can be effectively prevented at the start of film formation and at the time of film formation, and defects that have already existed are repaired beyond the activation energy for restoration. I can do it.

Next, as shown in FIG. 2C, a NiO film containing Ag is formed by a PLD method in an oxygen atmosphere using Ag or Ag oxynitride mixed with Ni or Ni oxynitride as a target. Vapor deposition is performed on the nitride film 24. By forming a film in an oxygen atmosphere, the oxidation of NiO can be promoted and the hole concentration can be increased.
Thereafter, oxygen gas is supplied to the radical irradiation device 14 to generate oxygen radicals, and heat treatment is performed at 200 ° C. or higher, for example, for 10 minutes while irradiating the surface of the NiO film with oxygen radicals.
By performing heat treatment in an oxygen atmosphere, oxygen defects can be reduced and p-type conduction can be realized.

As a result, a p-type NiO film 25 doped with Ag can be formed. The content of Ag is, for example, 1 to 5 [mol%]. Further, the carrier concentration of the NiO film can be changed by changing the temperature and time of the heat treatment. By increasing the carrier concentration, extension of the depletion layer toward the NiO film can be suppressed.
In addition, by providing a plurality of targets in the same PLD apparatus, after the step of FIG. 2B, the step of FIG. 2C can be continuously performed without exposing the substrate 20 to the atmosphere. . Thereby, unnecessary contamination and the like can be effectively eliminated from the silicon nitride film 24 which is a gate insulating film.

In the step of forming the NiO film, the second group III nitride semiconductor layer 22 can be prevented from desorbing nitrogen because it is covered with the silicon nitride film.
Furthermore, since the silicon nitride film is oxygen impermeable, it is possible to prevent the surface of the second group III nitride semiconductor layer 22 from being oxidized during the heat treatment in the oxidizing atmosphere after the NiO film is formed. As a result, variation in transistor characteristics due to surface oxidation can be prevented.

  In addition, after vapor-depositing a NiO film containing Ag by the PLD method, heat treatment may be performed in an oxygen atmosphere using another apparatus.

Further, after forming a NiO film by a PLD method using NiO as a target, Ag is formed by a PLD method using Ag as a target to form a laminated film of NiO and Ag, and Ag is put into the NiO film by heat treatment. A p-type NiO film 25 diffused and doped with Ag may be formed. The Ag concentration can be variably controlled depending on the film thickness of Ag to be formed.
In this case, the heat treatment for diffusing Ag does not need to be performed in an oxygen atmosphere, and may be performed in a vacuum or a nitrogen atmosphere in order to prevent oxidation of Ag in the upper layer. However, after diffusion of Ag by heat treatment in a non-oxidizing atmosphere, heat treatment is performed in an oxygen atmosphere to increase the hole concentration of the NiO film and promote p-type formation.

The laminated film can be formed by the PLD method using independent Ag and NiO targets alternately. Further, the present invention is not limited to the above, and the NiO film and the Ag oxidation may be performed by a PLD method in an oxygen atmosphere targeting Ni or Ni oxynitride and a PLD method in an oxygen atmosphere targeting Ag or Ag oxynitride. A laminated film with a film may be formed.
Formation of the NiO film by the PLD method in an oxidizing atmosphere can promote the oxidation of NiO and increase the hole concentration.
The laminated structure is not limited to a two-layer structure, and may be a multilayer film of three or more layers in which different films are alternately formed.

The NiO film is an oxide semiconductor with a large band gap, but becomes a p-type semiconductor by doping Ag as described above, and the work function of the NiO film can be adjusted by the concentration of Ag to be doped.
The NiO film has characteristics of an electron affinity of 2.5 [eV] and a band gap of 4.0 [eV]. The work function of a semiconductor is equal to the sum of the electron affinity and the energy difference from the conduction band to the Fermi level, but since the Fermi level is near the valence band, the p-type semiconductor has a sum of the electron affinity and the band gap. A value close to.
The work function of the p-type NiO film containing Ag increases the p-type carrier concentration by increasing the concentration of Ag. As the carrier concentration increases, the Fermi level approaches the valence band and exceeds the density of states. Since it degenerates when doped, the energy difference from the conduction band to the Fermi level is equivalent to the band gap. Therefore, the work function of the p-type NiO film containing Ag is 6.5 [eV]. The value of this work function can realize a value larger than the largest Pt of 5.6 [eV] in metal.
As a result, by using a p-type NiO film containing Ag as a gate electrode, it is possible to realize an enhancement type FET that has been difficult to manufacture.
In addition to Ag, Li may be used as a p-type dopant for NiO. However, since Li has deliquescence, the use of Ag as a dopant facilitates the production of a deposition target.

In addition, you may comprise a p-type semiconductor by vapor-depositing oxide semiconductors other than NiO, and doping with Ag or other elements after that.
In the above embodiment, the FET using the p-type NiO film as the gate electrode has been described. However, a metal such as Ni or Pt may be used as the gate electrode. In this case, a gate electrode can be formed by forming a metal film on the silicon nitride film 24 that is a gate insulating film by a PLD method using a metal such as Ni, for example, and patterning.

  Next, as shown in FIG. 2D, the p-type NiO film 25 is patterned to form a NiO film pattern 25a. The p-type NiO film 25 can be patterned by dry etching using a photoresist as a mask by the lithography process. However, since the dry etching is performed on the silicon nitride film 24, the surface of the substrate 20 is dry etched. Damage from is not added.

When the p-type NiO film is wet-etched, the p-type NiO film can be etched by immersing the substrate in a mixed solution containing concentrated sulfuric acid and hydrogen peroxide water raised to 60 [° C.] or higher. .
As the above mixed solution, for example, a commercially available concentrated sulfuric acid having a concentration of 90 [%] and a commercially available hydrogen peroxide solution having a concentration of 35 [%] are mixed at a volume ratio of concentrated sulfuric acid: hydrogen peroxide solution 1: 1-3. The obtained liquid can be used.

When wet etching is performed, a patterned silicon oxide film can be used as an etching mask. In this case, a silicon oxide film is formed on the p-type NiO film by a CVD method or the like, and a resist pattern is formed on the silicon oxide film by a lithography method. Then, the silicon oxide film pattern can be formed by etching the silicon oxide film with hydrofluoric acid.
A silicon nitride film can be used instead of the silicon oxide film. When wet etching the silicon nitride film, hot phosphoric acid may be used.

Next, as shown in FIG. 3A, for example, a silicon oxide film is formed by a CVD method or the like, and a mask 26 is formed by a combination of lithography and etching. Thereafter, using the mask 26 as an etching mask, the silicon nitride film 24 is etched to expose the source (cathode) and drain (anode) regions 27a and 27b of the second group III nitride semiconductor layer 22. At this time, the silicon nitride film 24 may be left on the element isolation region (not shown) without being removed.
Although the mask 26 is formed of a silicon oxide film, other materials may be used as long as the film can be used as a mask for the lift-off process.

  When the mask 26 is formed, the silicon nitride film 24 may be etched after the silicon oxide film is etched using the photoresist as a mask. However, by etching the silicon nitride film 24 using the mask 26 as a mask instead of the photoresist, the surface of the substrate 20 can be prevented from being oxidized by the ashing process for removing the photoresist.

Next, as shown in FIG. 3B, a first metal film 28 for forming a contact electrode, for example, a laminated film of Ti and Al is formed in this order by vapor deposition or the like.
Thereafter, the substrate 20 on which the first metal film 28 is formed is subjected to heat treatment and brought into ohmic contact. For example, Ti / Au, Hf / Ni / Au, or Y / Ni / Au can be used as the first metal film 28 in addition to Ti20 [nm] / Al200 [nm].

  Before forming the first metal film 28, the surface of the second group III nitride semiconductor layer 22 is heated while being irradiated with nitrogen radicals, so that the second group III nitride semiconductor layer 22 is dry etched. Crystal defects generated on the surface may be recovered. As a result, a contact resistance with a lower resistance can be realized.

  Next, as shown in FIG. 3C, the mask 26 made of a silicon oxide film is removed by, for example, a wet etching method using hydrofluoric acid or the like, and the first metal film 28 on the mask 26 is removed by a lift-off method. As a result, the first metal film 28 on the source / drain regions 27a and 27b is left.

  Next, as shown in FIG. 3D, a second metal film 29 for gate wiring, for example, Ni 20 [nm] / Au 200 [nm], is formed on the NiO film pattern 25a by a lift-off method. Since the lift-off method is the same as the process described with reference to FIGS. 3A, 3B, and 3C, details are omitted.

  Through the above steps, a gate insulating FET can be obtained. Thereafter, if necessary, an interlayer insulating film that covers the FET is formed, and contact holes and wirings are formed.

  Note that the thickness of the silicon nitride film may be determined as appropriate in order to achieve a desired breakdown voltage and dielectric constant of the gate insulating film. In the above embodiment, a silicon nitride film is used as the gate insulating film. However, a silicon oxide film, an aluminum oxide film, a hafnium (Hf) oxide film, a zirconium (Zr) oxide film, and an HfZr oxide film are formed on the silicon nitride film. By forming another insulating film such as a film, the withstand voltage and dielectric constant of the gate insulating film may be adjusted.

  The mask used in the lift-off method may use a photoresist other than the silicon oxide film.

  In the above embodiment, the source and drain electrodes are formed after forming the gate electrode made of the NiO film. However, after forming the source and drain electrodes by the lift-off method, the gate electrode made of the NiO film and the Ni / Au film are made. A gate wiring may be formed.

  When a NiO film is directly formed on a group III nitride semiconductor and used as a gate electrode, the NiO film is a p-type semiconductor with a large band gap, and a hetero PN junction with many interface defects is formed. As a result, there arises a problem that leakage current (off current) increases. However, leakage current can be reduced by providing a silicon nitride film as in the above-described embodiment.

  FIG. 4 shows the gate voltage (source-gate voltage) dependence of the drain current (Id) of the FET obtained by this embodiment. 4A shows a case where the substrate temperature at the time of forming the silicon nitride film 24 which is a gate insulating film is room temperature, and FIG. 4B shows a case where the silicon nitride film 24 which is a gate insulating film is formed. The drain current (Id) characteristics when the substrate temperature is 200 [° C.] are shown.

As shown in FIG. 4A, when the substrate temperature when the silicon nitride film 24 is formed is room temperature, there is a hysteresis in the Id when the gate voltage is raised and lowered, and the gate voltage shift amount is 450 [mV]. ].
On the other hand, as shown in FIG. 4B, when the substrate temperature at the time of forming the silicon nitride film 24 is 200 [° C.], the hysteresis of Id at the time of step-up and step-down of the gate voltage is not confirmed. The amount of gate voltage shift is as good as 100 [mV] or less. This result means that the interface state between the second group III nitride semiconductor layer 22 and the silicon nitride film 24 can be suppressed by forming the silicon nitride film 24 at a substrate temperature of 200 [° C.]. .
Unlike the case where the film formation temperature of the silicon nitride film 24 is 200 [° C.], when the film formation temperature of the silicon nitride film 24 is room temperature, a clear hysteresis is observed. Means that activation energy corresponding to a temperature of 200 [° C.] is required.

  Note that a p-type group III nitride semiconductor may be formed between the gate insulating film 24 and the second group III nitride semiconductor layer 22 to form a so-called gate injection transistor which is a kind of FET in a broad sense.

  In the above-described embodiment, after performing heat treatment while irradiating the substrate with nitrogen radicals, the film was continuously formed on the substrate by the PLD method in the same chamber, but a multi-chamber apparatus was used. Thus, it is possible to process the substrates in different chambers, and transfer the substrates between the chambers using a vacuum transfer system.

(Embodiment 2)
Hereinafter, another embodiment of the present invention will be described with reference to FIGS. 5, 6, and 7.
By utilizing surface defect generation prevention and defect recovery effect due to nitrogen desorption of group III nitride semiconductor by heat treatment in nitrogen radical atmosphere, group III nitride is epitaxially grown in the source and drain regions of the FET, The performance of the FET can be improved.
Hereinafter, an N-channel Schottky gate type FET will be described as an example, but the insulated gate FET disclosed in the first embodiment can also be suitably applied.

A substrate 20 having a second group III nitride semiconductor layer 22, for example, an AlGaN layer formed on the first group III nitride semiconductor layer 21, for example, a GaN layer, is prepared, as shown in FIG. A silicon oxide film 30 is formed on the second group III nitride semiconductor layer 22 by a CVD method or the like.
It should be noted that a silicon oxide film may be formed while irradiating oxygen radicals using a target of Si after recovering crystal defects on the surface of the substrate 20 by using a PLD apparatus and irradiating nitrogen radicals while heating. Good.

Next, as shown in FIG. 5B, the silicon oxide film 30 on the regions to be the source region 31a and the drain region 31b of the FET is dry-etched using a photoresist as a mask by a combination of lithography and etching techniques, and then The photoresist 30 is removed by ashing or the like to form a mask 30a. Next, using the mask 30a as a mask, the substrate 20 in the region to be the source region 31a and the drain region 31b is dry-etched to expose the first group III nitride semiconductor layer 21 on the surface.
A region sandwiched between the source region 31a and the drain region 31b becomes a channel region 31c. Strictly speaking, the channel region of the FET is a region whose electric conduction is controlled by an electric field generated by the gate electrode. However, in this specification, a region sandwiched between the source region 31a and the drain region 31b is defined as a channel. This is referred to as a region 31c.

  Next, as shown in FIG. 5C, while irradiating the nitrogen radical 32, for example, heating to 200 [° C.] to recover crystal defects near the surface of the substrate 20.

  Next, as shown in FIG. 5 (d), while irradiating nitrogen radicals by a PLD method using Ga containing 2 [mol%] of an IV group element such as germanium (Ge) as an n-type dopant, The third group III nitride semiconductors 33a and 33b, which are n-type GaN layers doped with Ge, are epitaxially grown on the source and drain regions 31a and 31b with the first group III nitride semiconductor layer 21 exposed on the surface. . On the other hand, since the mask 30a is composed of a silicon oxide film, a polycrystalline group III nitride semiconductor 33c, which is a polycrystalline GaN layer grown in an island shape, is not epitaxially grown on the mask 30a.

  FIG. 6 is a surface SEM photograph after the step of FIG. The polycrystalline group III nitride semiconductor 33c having surface irregularities is formed on the mask 30a, whereas the third group III nitride semiconductors 33a and 33b are epitaxial growth films having smooth surfaces. I understand that.

Next, as shown in FIG. 7A, nitrogen radical irradiation is stopped, and C12A7 films 34a, 34b, and 34c are formed with a film thickness of, for example, 10 to 20 [nm] by the PLD method using C12A7 as a target.
During the film formation of the C12A7 film by the PLD method, the oxygen atmosphere may be switched. Further, Ti can be continuously laminated by the PLD method after the C12A7 film is formed.

  The polycrystalline group III nitride semiconductor 33c may be etched by TMAH (tetramethylammonium hydroxide) after the step of FIG. 5D and before the step of FIG. 7A. As described below, the third group III nitride semiconductors 33a and 33b epitaxially grown are not etched by TMAH, and the polycrystalline group III nitride semiconductor 33c is selectively etched. Therefore, the mask 30a under the group III nitride semiconductor 33c is exposed, and etching of the mask 30a in the next lift-off process is further facilitated.

  TMAH heated to 50 [° C.] or more (aqueous solution with a weight concentration of 2.38 [%]) has an etching effect on the a-plane and m-plane of the GaN crystal, but does not etch the c-plane. . Since the surface of the epitaxially grown GaN (third group III nitride semiconductor 33a, 33b) is a c-plane, it is not etched. On the other hand, since the GaN film formed on the mask 30a (silicon oxide film) is polycrystalline (polycrystalline group III nitride semiconductor 33c), there are grains having a-plane and m-plane on the surface. As a result, only polycrystalline GaN (polycrystalline group III nitride semiconductor 33c) is selectively etched.

  Next, as shown in FIG. 7B, the mask 30a is selectively removed by wet etching using, for example, hydrofluoric acid, and the polycrystalline group III nitride semiconductor 33c and the C12A7 film 34c on the mask 30a are removed. Then, the third group III nitride semiconductors 33a and 33b and the C12A7 films 34a and 34b are left in the source / drain regions 31a and 31b.

Next, as shown in FIG. 7C, for example, a Ti / Al film is deposited, and third metals 35a and 35b containing Ti are formed on the C12A7 films 34a and 34b by a lift-off method. Thereafter, heat treatment is performed in a vacuum at a temperature of 200 [° C.] or higher, and Ti is supplied from the third metals 35a and 35b to the C12A7 films 34a and 34b by thermal diffusion.
As will be described below, the C12A7 films 34a and 34b can have high electrical conductivity by supplying Ti and performing heat treatment.

  The C12A7 film includes free oxygen ions in a cage structure formed by a crystal lattice skeleton. By reducing the included free oxygen ions with Ti and replacing them with electrons, the C12A7 film can have high conductivity. Note that Al can also function as a reducing material.

  The third metal 35a, 35b may be an alloy containing Ti, but a laminated film having a Ti layer in the lower layer, such as a Ti / Al film, is more efficient for Ti to the C12A7 films 34a, 34b. Can be supplied.

  C12A7 has a special effect of reducing contact resistance because it has a high electrical conductivity and a work function as low as 2.4 [eV]. That is, since C12A7 has a small work function and is smaller than the electron affinity of the GaN surface, no potential barrier is generated between C12A7 and GaN. As a result, the contact resistance has an effect that the contact resistance can be reduced as compared with a conventionally used contact electrode of a metal material.

In addition, you may use C12A7 which heat-processed previously with reducing materials, such as Ti and Al, as a target of C12A7 film | membrane deposited by PLD method. Thereby, it is not necessary to supply the reducing material from the third metals 35a and 35b, and high electrical conductivity can be obtained.
In the case of the PLD method, free oxygen can be efficiently reduced by the energy of the laser beam.
In addition, after the C12A7 film is deposited by the PLD method, heat treatment is performed while irradiating hydrogen radicals, or C12A7 is deposited while irradiating hydrogen radicals. May be replaced.

  Next, as shown in FIG. 7D, a gate electrode 36 made of, for example, a Ni / Au film is formed by, for example, a lift-off method using a photoresist as a mask.

  Before forming the Ti / Al film shown in FIG. 7C and the Ni / Au film shown in FIG. 7D, the substrate 20 is irradiated with nitrogen radicals using the PLD apparatus. The substrate may be heated while it is being heated. After recovering the crystal defects on the surface of the substrate 20, a Ti / Al film or a Ni / Au film can be formed to reduce contact resistance and stabilize the threshold voltage.

In the present embodiment, since the group III nitride semiconductor is formed in the source and drain regions after recovering crystal defects by the PLD method, epitaxial growth can be performed while suppressing the generation of crystal defects. As a result, the contact resistance of the source and drain regions decreases, and the on-resistance of the FET decreases. As a result, the on-current of the FET increases.
In addition, by using a C12A7 film that is in ohmic contact with the epitaxially grown group III nitride semiconductor as a contact electrode, the contact resistance with the group III nitride semiconductor can be further reduced, and the on-current of the FET can be reduced. It can be further increased.

Note that the step shown in FIG. 7A is omitted, and the third group III nitride of the source and drain regions 31a and 31b is directly formed by using a metal film such as a Ti / Al film, for example, without interposing the C12A7 film. The semiconductor electrodes 33a and 33b may be in ohmic contact and used as contact electrodes.
In this case, compared with the said embodiment, although a contact resistance increases, manufacturing cost reduces.

(Embodiment 3)
Although the N-channel FET has been described in the second embodiment, it is possible to manufacture a P-channel FET by using the film formation pretreatment and the film formation process of the present invention. Hereinafter, a method for manufacturing a P-channel FET will be described with reference to FIGS.

A first group III nitride semiconductor layer 21, for example, a GaN layer, a second group III nitride semiconductor layer 22, for example, an AlGaN layer, and a fourth group III nitride semiconductor layer 41, for example, a GaN layer are formed in this order. A substrate 40 is prepared.
The fourth group III nitride semiconductor layer 41 is heterojunction with the second group III nitride semiconductor layer 22, and a two-dimensional hole gas is formed in the fourth group III nitride semiconductor layer 41.

  As shown in FIG. 8A, a silicon oxide film is formed on the fourth group III nitride semiconductor layer 41 by a CVD method or the like. Thereafter, a mask 42 having an opening 43 is formed in a region to be a channel region of the P-channel FET by a combination of lithography technology and etching technology.

  Next, as shown in FIG. 8B, a p-type group III nitride semiconductor is used for the substrate 40 by using a Ga target containing, for example, Mg as a p-type dopant by a PLD method while irradiating nitrogen radicals. A fifth group III nitride semiconductor 44 such as Mg-containing GaN is epitaxially grown. On the other hand, since epitaxial growth does not occur on the mask 42, a polycrystalline group III nitride semiconductor 45, for example, Mg-containing polycrystalline GaN is formed.

  Next, as shown in FIG. 8C, the surface of the polycrystal group III nitride semiconductor 45 is wet-etched to reduce the film thickness or remove minute crystals. Etching is performed using, for example, TMAH, so that the polycrystalline group III nitride semiconductor 45 is selectively etched, and the fifth group III nitride semiconductor 44 epitaxially grown is not etched. As a result, the exposed area of the mask 42 increases, and the mask removal in the next process is further facilitated.

  Next, as shown in FIG. 8D, the mask 42 is wet-etched, and the fifth group III nitride semiconductor 45 on the mask 42 is removed by a lift-off method.

  Next, as shown in FIG. 9A, a silicon oxide film is formed by a CVD method or the like, and a mask 46 is formed so as to cover the fifth group III nitride semiconductor 44 by a combination of lithography technology and etching technology. To do.

  Next, as shown in FIG. 9B, the substrate 40 is etched using the mask 46 as an etching mask to expose the surface of the first group III nitride semiconductor layer 21.

  Next, as shown in FIG. 9C, while irradiating nitrogen radicals, the substrate 40 is heated to 200 [° C.] or higher to recover crystal defects, and then Ga containing 2 [mol%] of Mg is added. A sixth group III nitride semiconductor 47, which is a p-type group III nitride semiconductor, is epitaxially grown on the exposed surface of the first group III nitride semiconductor layer 21 by a target PLD method. At this time, a polycrystalline group III nitride semiconductor 48 is formed on the mask 46.

  Thereafter, irradiation with nitrogen radicals is stopped, the target is changed, and, for example, on the sixth group III nitride semiconductor 47 and the polycrystalline group III nitride semiconductor 48 by a PLD method using NiO containing Ag as a target. For example, p-type contact conductive films 49 and 50 made of a p-type NiO film doped with Ag are formed. Thereafter, the electrical conductivity of the contact conductive films 49 and 50 can be increased by performing heat treatment at 200 [° C.] or higher in an oxygen atmosphere.

  Note that heat treatment in an oxygen atmosphere can be performed in a PLD apparatus, but heat treatment may be performed in a separate heat treatment apparatus.

  Next, as shown in FIG. 9D, the mask 46 is wet-etched, and the polycrystalline group III nitride semiconductor 48 and the contact conductive film 50 formed on the mask 46 are removed by a lift-off method.

  Next, as shown in FIG. 10, a mask made of photoresist is used to deposit a conductive film for electrodes, for example, Ni / Al, and the source, drain electrode 51 and gate electrode 52 are formed by a lift-off method.

In this embodiment, when forming a group III nitride semiconductor to be formed in the source and drain regions, a heat treatment is performed while irradiating nitrogen radicals to recover the crystal, and p-type group III having good crystallinity. A sixth group III nitride semiconductor 47, which is a nitride semiconductor, can be formed.
Further, in order to make ohmic contact between the sixth group III nitride semiconductor 47 and the source and drain electrodes and to reduce contact resistance, a p-type NiO film contact conductive film 49 is interposed. The work function of the NiO film can be adjusted by the amount of Ag doping, and the contact resistance between the NiO film and the p-type sixth group III nitride semiconductor 47 can be reduced by Ag doping.

In the above-described embodiment, the p-type NiO film containing Ag is used as a contact electrode with the source and drain regions. However, it is formed so as to be in contact with the fifth group III nitride semiconductor 44 and is used as a gate electrode. May be used.
After the step of FIG. 9D, a p-type NiO film containing Ag may be formed on the fifth group III nitride semiconductor 44 again by the lift-off method. Note that the method for forming a p-type NiO film containing Ag is the same as the step shown in FIG.
An enhancement type transistor can be realized by using a p-type NiO film containing Ag having a large work function and conductivity as a gate electrode of a Schottky field effect transistor. Further, the threshold value of the transistor can be adjusted by adjusting the Ag concentration.

(Embodiment 4)
By combining nitrogen radical irradiation according to the present invention and film formation by the PLD method, a group III nitride having good crystallinity can be formed while suppressing crystal defects due to nitrogen vacancies.
Hereinafter, a regrowth technique for a group III nitride semiconductor capable of further reducing the contact resistance will be described.

  A substrate 20 is prepared in which a second group III nitride semiconductor layer 22, such as an AlGaN layer, is formed on a first group III nitride semiconductor layer 21, such as a GaN layer. 5A to 5C, the first group III nitride semiconductor layer 21 in the source and drain regions is exposed, and heat treatment is performed while irradiating nitrogen radicals. Recover surface defects.

Next, as shown in FIG. 11A, compared with the first group III nitride semiconductor layer 21, n-type seventh group III nitride semiconductors 53a and 53b having a large band gap are respectively formed in the source region. Epitaxial growth is performed on 31a and the drain region 31b, and a polycrystalline group III nitride semiconductor 54 is formed on the mask 30a.
The seventh group III nitride semiconductors 53a and 53b and the polycrystalline group III nitride semiconductor 54 are formed by a PLD method using, for example, AlGaN containing Ge as a target.

  Next, as shown in FIG. 11B, the mask 30a is wet-etched, and the polycrystalline group III nitride semiconductor 54 is removed by a lift-off method.

  Next, as shown in FIG. 11C, a source electrode 55a and a drain electrode 55b made of a Ti / Al film are formed by, for example, a lift-off method using a photoresist as a mask.

Next, as shown in FIG. 11D, for example, a channel region where the first group III nitride semiconductor layer 21 and the second group III nitride semiconductor layer 22 are heterojunction by a lift-off method using a photoresist as a mask. A gate electrode 56 made of a Ni / Au film is formed on 31c.
The channel region 31c is in contact with the source / drain regions 31a and 31b.

In the present embodiment, due to the heterojunction between the first group III nitride semiconductor layer 21 and the second group III nitride semiconductor layer 22, most of the two-dimensional electron gas is the first group III nitride semiconductor layer 21. Is generated.
The seventh group III nitride semiconductor 53a formed in the source region 31a has a larger band gap than the first group III nitride semiconductor 21, and has an electron affinity (energy from the vacuum level to the bottom of the conduction band). ) Is small.
Therefore, an energy difference is generated between the conduction band of the seventh group III nitride semiconductor 53a in the source region 31a and the conduction band of the first group III nitride semiconductor 21 in the channel region 31c.
Electrons injected from the conduction band of the seventh group III nitride semiconductor 53a in the source region into the conduction band of the first group III nitride semiconductor 21 in the channel region are given kinetic energy corresponding to the energy difference. , Increase speed.
Accordingly, it is sufficient that the seventh group III nitride semiconductor 53a having a larger band gap than that of the first group III nitride semiconductor 21 is formed at least in the source region 31a.

  As a result, in the FET of the present embodiment, as compared with the case where the same group III nitride semiconductor as the first group III nitride semiconductor layer 21 is used as the seventh group III nitride semiconductor 53a in the source region 31a, The operation speed of the FET can be increased.

In the above embodiment, in the step shown in FIG. 11A, the n-type seventh group III nitride semiconductors 53a and 53b having a large band gap as compared with the first group III nitride semiconductor layer 21 are used. In comparison with the first group III nitride semiconductor layer 21, a group III nitride semiconductor having a small band gap is formed as, for example, Ge as the n-type seventh group III nitride semiconductors 53a and 53b. Epitaxial growth may be performed by a PLD method using InGaN containing N as a target.
In this case, electrons injected from the conduction band of the first group III nitride semiconductor 21 in the channel region 31c into the conduction band of the seventh group III nitride semiconductor 53b in the drain region 31b are converted into the first group III nitride. Kinetic energy corresponding to the energy difference between the conduction band of the semiconductor 21 and the conduction band of the seventh group III nitride semiconductor 53b is given, and the speed increases.
As a result, it is possible to increase the operation speed of the FET as compared with the case where the same group III nitride semiconductor as the first group III nitride semiconductor layer 21 is used as the seventh group III nitride semiconductor 53b in the drain region 31b. it can.
Therefore, in this case, it is sufficient that the seventh group III nitride semiconductor 53b having a smaller band gap as compared with the first group III nitride semiconductor 21 is formed at least in the drain region 31b.

  In addition, although the said embodiment demonstrated Schottky gate type FET, it can apply also to the group III nitride semiconductor of the source | sauce and drain region of insulated gate type FET, and is suitable also for insulated gate type FET shown in Embodiment 1 especially. Applicable.

(Embodiment 5)
In the present embodiment, the high-speed operation of the FET can be enhanced by forming a group III nitride semiconductor having a small band gap in the drain region.

  As shown in FIG. 12A, the silicon oxide film 30 is exposed by combining the lithography technique and the etching technique to expose a region to be the FET source region 31a by the same method as in the step of FIG. Is patterned to form a mask 30b. Thereafter, using the mask 30b as a mask, the substrate 20 in the region to be the source region 31a is dry-etched to expose the first group III nitride semiconductor layer 21.

Next, as shown in FIG. 12B, while irradiating with nitrogen radicals, the substrate is heated to, for example, 200 [° C.] to recover crystal defects near the surface of the substrate 20. Thereafter, an n-type seventh group III nitride semiconductor 53a having a larger band gap than that of the first group III nitride semiconductor layer 21 is epitaxially grown on the source region 31a, and a polycrystalline group III is formed on the mask 30b. A nitride semiconductor 54 is formed.
The seventh group III nitride semiconductor 53a and the polycrystalline group III nitride semiconductor 57 are formed by, for example, a PLD method using AlGaN as a target.

  Next, as shown in FIG. 12C, the mask 30b is wet-etched, and the polycrystalline group III nitride semiconductor 57 is removed by a lift-off method.

  Next, as shown in FIG. 12D, a mask 58 that exposes a region to be the drain region 31b of the FET is formed by the same method as in FIG.

Next, as shown in FIG. 12E, the substrate 20 is etched using the mask 58 as a mask to expose the first group III nitride semiconductor layer 21 in the region to be the drain region 31b.
Thereafter, while irradiating with nitrogen radicals, for example, heating is performed to 200 [° C.] to recover crystal defects on the surface of the substrate 20. After that, an n-type eighth group III nitride semiconductor 59 having a smaller band gap than that of the first group III nitride semiconductor layer 21 is epitaxially grown on the drain region 31b, and a polycrystalline group III group is formed on the mask 58. A nitride semiconductor 60 is formed.
The eighth group III nitride semiconductor 59 and the polycrystalline group III nitride semiconductor 60 are formed, for example, by a PLD method using InGaN containing Ge as a target.

  Next, as shown in FIG. 13A, the mask 58 is wet-etched, and the polycrystalline group III nitride semiconductor 60 is removed by a lift-off method.

Next, as shown in FIG. 13B, similarly to the steps of FIGS. 11C and 11D, a source electrode 55a and a drain electrode 55b made of a Ti / Al film are formed by a lift-off method, and then lift-off is performed. A gate electrode 56 made of a Ni / Au film is formed on the channel region 31c by the method.
The channel region 31c is in contact with the source / drain regions 31a and 31b.

In the present embodiment, the eighth group III nitride semiconductor 59 formed in the drain region has a smaller band gap and a higher electron affinity (from the vacuum level to the conduction band) than the first group III nitride semiconductor 21. The energy up to the bottom is large. Therefore, an energy difference is generated between the conduction band of the first group III nitride semiconductor 21 in the channel region and the eighth group III nitride semiconductor 59 conduction band in the drain region.
Electrons injected from the conduction band of the first group III nitride semiconductor 21 in the channel region into the conduction band of the eighth group III nitride semiconductor 59 in the drain region are given kinetic energy corresponding to the energy difference. , Increase speed.
As a result, in the FET of this embodiment, the operation speed of the FET can be further increased as compared to the fourth embodiment.

  In the present embodiment, the eighth group III nitride semiconductor 59 is formed in the drain region 31b after the seventh group III nitride semiconductor 53a is formed in the source region 31a. After the eighth group III nitride semiconductor 59 is formed on 31b, the seventh group III nitride semiconductor 53a may be formed on the source region 31a.

  Although the above description is about the Schottky gate type FET, it can also be applied to an insulated gate type FET, and can be preferably applied to the insulated gate type FET shown in the first embodiment.

1 Chamber 2 Substrate Support Device 3 Target Support Device
4 Substrate 5a, 5b Target container 6a, 6b Target 7 Light transmission window 8 Laser irradiation device 20 Substrate 20
21 First group III nitride semiconductor layer 22 Second group III nitride semiconductor layer 23 Nitrogen radical 24 Silicon nitride film 25 P-type NiO film 25a NiO film pattern 26 Mask 27a Source region 27b Drain region 28 First metal film 29 Second metal film 30 Silicon oxide film 30a, 30b Mask 31a Source region 31b Drain region 31c Channel region 32 Nitrogen radical 33a, 33b Third group III nitride semiconductor 33c Polycrystalline group III nitride semiconductors 34a, 34b, 34c C12A7 film 35a, 35b Ti / Al film 36 Ni / Au film 40 Substrate 41 Fourth group III nitride semiconductor layer 42 Mask 43 Opening portion 44 Group III nitride semiconductor 45 Polycrystalline group III nitride semiconductor 46 Mask 47 Sixth Group III Nitride Semiconductor 48 Polycrystalline II Nitride semiconductor 49 conductive film 50 conductive film 51 source contact contact, a drain electrode 52 gate electrode 52
53a, 53b Seventh group III nitride semiconductor 54 Polycrystalline group III nitride semiconductor 55a Source electrode 55b Drain electrode 56 Gate electrode 57 Polycrystalline group III nitride semiconductor 58 Mask 59 Eighth group III nitride semiconductor 60 Polycrystalline group III nitride semiconductor

Claims (20)

A method of manufacturing a semiconductor device, comprising: performing a nitrogen radical treatment on a substrate having a group III nitride semiconductor on the surface thereof, wherein the substrate surface is heated while being irradiated with nitrogen radicals. The semiconductor device is a transistor,
A first step of performing the nitrogen radical treatment;
After the first step, a silicon nitride film is formed on the substrate surface by a PLD method using silicon as a target while continuously irradiating the surface of the substrate with nitrogen radicals, thereby forming a gate insulating film. And the process of
A third step of forming a gate electrode on the silicon nitride film;
The method of manufacturing a semiconductor device according to claim 1, further comprising: a fourth step of removing the silicon nitride film on the regions to be the source region and the drain region, and forming the source electrode and the drain electrode. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the gate electrode formed in the third step is made of metal. In the third step, the NiO film containing Ag is formed by the PLD method in an oxygen atmosphere using Ag or Ag oxynitride and Ni or Ni oxynitride as a target mixed on the silicon nitride film. A NiO film and an Ag oxide film by a PLD method in an oxygen atmosphere targeting Ni or Ni oxynitride and a PLD method in an oxygen atmosphere targeting Ag or Ag oxynitride Forming a laminated film with
A step of forming a p-type NiO film by heat-treating the NiO film containing Ag or a stacked film of the NiO film and an Ag oxide film in an oxygen atmosphere at a temperature of 200 [° C.] or higher;
The method of manufacturing a semiconductor device according to claim 2, further comprising: patterning the p-type NiO film to form a gate electrode. In the step of patterning the p-type NiO film and forming a gate electrode,
The step of etching the p-type NiO film by immersing the substrate in a mixed solution containing concentrated sulfuric acid and aqueous hydrogen peroxide at a temperature of 60 [° C.] or higher is provided. 5. A method for manufacturing a semiconductor device according to 4. The semiconductor device is a transistor,
A first step of forming an etching mask having openings in regions serving as a source region and a drain region on a substrate having a group III nitride semiconductor on the surface;
A second step of etching the regions to be the source region and the drain region of the substrate using the etching mask as a mask;
A third step of performing the nitrogen radical treatment;
After the third step, an n-type group III nitride semiconductor is converted into the source region and the drain region by a PLD method targeting a group III element containing a group IV element while continuously irradiating nitrogen radicals. A fourth step of epitaxially growing the region;
The method of manufacturing a semiconductor device according to claim 1, further comprising a fifth step of forming a conductive film on the epitaxially grown n-type group III nitride semiconductor. The fifth step is a step of forming 12CaO.7Al ₂ O ₃ on the substrate by a PLD method;
Forming a film containing Ti on the substrate;
The method for manufacturing a transistor according to claim 6, further comprising a step of heat-treating the substrate in a vacuum at a temperature of 200 ° C. or higher. The semiconductor device is a transistor,
A first step of forming an etching mask having a region serving as a source region and a drain region on a substrate having a group III nitride semiconductor on the surface; and the source region and the drain of the substrate using the etching mask as a mask A second step of etching a region to be a region;
A third step of performing the nitrogen radical treatment;
After the third step, a p-type group III nitride semiconductor is formed in the source region and the drain region by a PLD method using a group III element containing Mg as a target while continuously irradiating nitrogen radicals. A fourth step of epitaxially growing
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a fifth step of forming a source electrode and a drain electrode on the epitaxially grown p-type group III nitride semiconductor. In the fifth step, a NiO film containing Ag is formed on the substrate by a PLD method using NiO containing Ag as a target, or a PLD method using NiO as a target and a PLD method using Ag as a target. Forming a laminated film of NiO and Ag by:
A step of heat-treating the substrate at a temperature of 200 ° C. or higher in an oxygen atmosphere so that the NiO film containing Ag or the stacked film of NiO and Ag is a p-type NiO film;
Patterning the p-type NiO film and leaving it on the epitaxially grown p-type group III nitride semiconductor;
The method of manufacturing a transistor according to claim 8, comprising:   10. The method of manufacturing a semiconductor device according to claim 6, wherein the substrate is immersed in a TMAH solution of 50 ° C. or higher after the fourth step. 11. The semiconductor device is a transistor,
Etching at least a region serving as a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor; A first step of exposing one group III nitride semiconductor;
A second step of performing the nitrogen radical treatment;
After the second step, the n-type having a smaller electron affinity than the first group III nitride semiconductor is formed on the exposed first group III nitride semiconductor while continuously irradiating nitrogen radicals. A third step of forming a third group III nitride semiconductor by a PLD method;
The method of manufacturing a semiconductor device according to claim 1, further comprising a fourth step of forming a contact electrode on the third group III nitride semiconductor. The semiconductor device is a transistor,
Etching at least a region to be a drain region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor; A first step of exposing one group III nitride semiconductor;
A second step of performing the nitrogen radical treatment;
After the second step, the n-type having higher electron affinity than the first group III nitride semiconductor is formed on the exposed first group III nitride semiconductor while continuously irradiating nitrogen radicals. A third step of forming a fourth group III nitride semiconductor by a PLD method;
The method of manufacturing a semiconductor device according to claim 1, further comprising a fourth step of forming a contact electrode on the third group III nitride semiconductor. The semiconductor device is a transistor,
Etching a region to be a source region of a substrate having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor; A first step of exposing the group III nitride semiconductor of
A second step of performing the nitrogen radical treatment;
After the second step, the n-type having a smaller electron affinity than the first group III nitride semiconductor is formed on the exposed first group III nitride semiconductor while continuously irradiating nitrogen radicals. A third step of forming a third group III nitride semiconductor by a PLD method;
Etching a region to be a drain region of the substrate to expose the first group III nitride semiconductor;
A fifth step of performing the nitrogen radical treatment;
After the fifth step, the n-type having higher electron affinity than the first group III nitride semiconductor is formed on the exposed first group III nitride semiconductor while continuously irradiating nitrogen radicals. A sixth step of forming a fourth group III nitride semiconductor by a PLD method;
The method of manufacturing a semiconductor device according to claim 1, further comprising: a seventh step of forming a contact electrode on the third group III nitride semiconductor and the fourth group III nitride semiconductor. The step of forming the contact electrode includes a step of forming a metal or a C12A7 film by a PLD method, a step of forming Ti by a PLD method, and a step of heating the substrate in a vacuum.
The method for manufacturing a semiconductor device according to claim 11, comprising the semiconductor devices in this order.   15. The method of manufacturing a semiconductor device according to claim 2, wherein the PLD method is a PLD method using a pulse laser having a pulse width on the order of picoseconds. A transistor using a group III nitride semiconductor,
A gate insulating film made of a silicon nitride film is provided on the group III nitride semiconductor,
A transistor comprising a NiO gate electrode containing Ag on the gate insulating film. An n-channel transistor using a group III nitride semiconductor, comprising an n-type group III nitride semiconductor epitaxially grown in a source region and a drain region,
An electrode is provided on the epitaxially grown n-type group III nitride semiconductor,
2. The transistor according to claim 1, wherein the electrode includes a C12A7 film in contact with the n-type group III nitride semiconductor epitaxially grown. A p-channel transistor using a group III nitride semiconductor, comprising a p-type group III nitride semiconductor epitaxially grown in a source region and a drain region,
An electrode is provided on the epitaxially grown p-type group III nitride semiconductor,
2. The transistor according to claim 1, wherein the electrode includes a NiO film containing Ag in contact with the epitaxially grown p-type group III nitride semiconductor. An n-channel transistor using a group III nitride semiconductor,
A channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor;
The source region in contact with the channel region has a third group III nitride semiconductor containing an n-type impurity having an electron affinity smaller than that of the first group III nitride semiconductor.
The third group III nitride semiconductor is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor. An n-channel transistor using a group III nitride semiconductor,
A channel region having a first group III nitride semiconductor and a second group III nitride semiconductor heterojunctioned on the first group III nitride semiconductor;
The drain region in contact with the channel region has a fourth group III nitride semiconductor containing an n-type impurity having an electron affinity larger than that of the first group III nitride semiconductor.
The fourth group III nitride semiconductor is in contact with the first group III nitride semiconductor and the second group III nitride semiconductor.

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