JP2018195720A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2018195720A JP2018195720A JP2017098654A JP2017098654A JP2018195720A JP 2018195720 A JP2018195720 A JP 2018195720A JP 2017098654 A JP2017098654 A JP 2017098654A JP 2017098654 A JP2017098654 A JP 2017098654A JP 2018195720 A JP2018195720 A JP 2018195720A
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- lead
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- sealing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000011347 resin Substances 0.000 claims abstract description 95
- 229920005989 resin Polymers 0.000 claims abstract description 95
- 238000005520 cutting process Methods 0.000 claims abstract description 71
- 238000007789 sealing Methods 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 12
- 230000008878 coupling Effects 0.000 abstract 2
- 238000010168 coupling process Methods 0.000 abstract 2
- 238000005859 coupling reaction Methods 0.000 abstract 2
- 238000005538 encapsulation Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】リード表面とリード間に充填される封止樹脂5表面との間に段差が生じている半導体装置を個片化する際、段差に密着する凹凸を備えたワーク受けダイ9でリード2を隙間なく挟持し、段差のない裏面側から切断パンチ11を用いてリード連結部7を切断する。
【選択図】図1
Description
Claims (3)
- 半導体素子搭載領域とリードがリード連結部により複数連結されたリードフレームを用意し、前記半導体素子搭載領域にそれぞれ半導体素子を搭載すると共に、各半導体素子を前記リードに接続する半導体素子搭載工程と、
前記半導体素子と前記リードを封止樹脂で封止し、前記リードの一部を露出させた樹脂封止体を形成する樹脂封止工程と、
前記リード連結部を切断して個々の半導体装置に個片化する切断工程と、を含み、
前記樹脂封止工程は、前記露出するリード及び前記リード連結部のリード間に前記封止樹脂を充填し、少なくとも一方の面の前記リード間の封止樹脂表面が、前記一方の面の前記リード表面より低くなるように段差が形成される工程であることと、
前記切断工程は、前記段差が形成された前記封止樹脂表面と前記リード表面とを隙間なく挟持し、該隙間なく挟持された前記一方の面の裏面側から、該裏面側の前記封止樹脂表面と前記リード表面に同時に接触する切断パンチを用いて切断する工程であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、前記切断工程は、前記段差を有する前記封止樹脂表面と前記リード表面とを隙間なく挟持する凹凸形状を表面に備えた金型により挟持する工程であることを特徴とする半導体装置の製造方法。
- 請求項1又は2いずれか記載の半導体装置の製造方法において、前記切断工程は、前記切断パンチが接触する部分の前記裏面側の前記封止樹脂表面及び前記リード表面の一部を除去し、前記切断パンチの先端が、前記裏面側の前記封止樹脂表面及び前記リード表面に同時に接触する工程であることを特徴とする半導体装置の製造方法。
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JP2017098654A JP6856199B2 (ja) | 2017-05-18 | 2017-05-18 | 半導体装置の製造方法 |
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JP2018195720A true JP2018195720A (ja) | 2018-12-06 |
JP6856199B2 JP6856199B2 (ja) | 2021-04-07 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019006538A1 (de) | 2018-10-17 | 2020-04-23 | Suzuki Motor Corporation | Abgasvorrichtung |
JP2020107815A (ja) * | 2018-12-28 | 2020-07-09 | 新日本無線株式会社 | 半導体装置およびその製造方法 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019006538A1 (de) | 2018-10-17 | 2020-04-23 | Suzuki Motor Corporation | Abgasvorrichtung |
JP2020107815A (ja) * | 2018-12-28 | 2020-07-09 | 新日本無線株式会社 | 半導体装置およびその製造方法 |
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