JP2018182325A5 - - Google Patents

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JP2018182325A5
JP2018182325A5 JP2018076139A JP2018076139A JP2018182325A5 JP 2018182325 A5 JP2018182325 A5 JP 2018182325A5 JP 2018076139 A JP2018076139 A JP 2018076139A JP 2018076139 A JP2018076139 A JP 2018076139A JP 2018182325 A5 JP2018182325 A5 JP 2018182325A5
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Japan
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gas
silanol
concave feature
substrate
sio
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JP2018076139A
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Japanese (ja)
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JP7113651B2 (ja
JP2018182325A (ja
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JP2018076139A 2017-04-11 2018-04-11 逆行的なプロファイルを有する凹状フィーチャのボイドのない充填方法 Active JP7113651B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762484343P 2017-04-11 2017-04-11
US62/484,343 2017-04-11

Publications (3)

Publication Number Publication Date
JP2018182325A JP2018182325A (ja) 2018-11-15
JP2018182325A5 true JP2018182325A5 (cg-RX-API-DMAC7.html) 2021-05-20
JP7113651B2 JP7113651B2 (ja) 2022-08-05

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JP2018076139A Active JP7113651B2 (ja) 2017-04-11 2018-04-11 逆行的なプロファイルを有する凹状フィーチャのボイドのない充填方法

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US (1) US10453737B2 (cg-RX-API-DMAC7.html)
JP (1) JP7113651B2 (cg-RX-API-DMAC7.html)
KR (1) KR102545882B1 (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102553117B1 (ko) * 2017-05-15 2023-07-06 도쿄엘렉트론가부시키가이샤 첨단 패턴화 적용을 위한 원위치의 선택적 증착 및 에칭
TWI790372B (zh) 2018-04-09 2023-01-21 日商東京威力科創股份有限公司 具有用於低電容內連線之氣隙的半導體元件形成方法
US20200232098A1 (en) * 2019-01-22 2020-07-23 Averatek Corporation Pattern formation using catalyst blocker

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940000906B1 (ko) * 1988-11-21 1994-02-04 가부시키가이샤 도시바 반도체장치의 제조방법
US6355567B1 (en) * 1999-06-30 2002-03-12 International Business Machines Corporation Retrograde openings in thin films
WO2002027063A2 (en) 2000-09-28 2002-04-04 President And Fellows Of Harward College Vapor deposition of oxides, silicates and phosphates
EP1490529A1 (en) 2002-03-28 2004-12-29 President And Fellows Of Harvard College Vapor deposition of silicon dioxide nanolaminates
US7098128B2 (en) 2004-09-01 2006-08-29 Micron Technology, Inc. Method for filling electrically different features
US7625820B1 (en) * 2006-06-21 2009-12-01 Novellus Systems, Inc. Method of selective coverage of high aspect ratio structures with a conformal film
KR20090095391A (ko) * 2008-03-05 2009-09-09 주식회사 하이닉스반도체 반도체 소자의 컨택 플러그 형성방법
JP5131240B2 (ja) * 2009-04-09 2013-01-30 東京エレクトロン株式会社 成膜装置、成膜方法及び記憶媒体
US9349637B2 (en) * 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill

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