JP2018160674A - Solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging device having excellent moisture resistance and a manufacturing method of the same.SOLUTION: The solid-state imaging device includes: a first substrate 308 having a pixel unit 301 including a plurality of photoelectric conversion units; a second substrate 309 having at least a part of a peripheral circuit 120 including a reading circuit and a control circuit for reading signals on the basis of charges of the plurality of photoelectric conversion units; and a wiring structure disposed between the first substrate 308 and the second substrate 309 and having a pad portion 312A electrically connected to the peripheral circuit 120 through lead wiring and an insulating layer. At least part of the wiring structure has seal rings 150A, 150B, 150C, 151A each arranged so as to surround the photoelectric conversion unit and the periphery of the peripheral circuit 120.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state imaging device configured by bonding a plurality of members.

  In a solid-state imaging device, a configuration in which a photoelectric conversion unit and a peripheral circuit unit are separately formed on different substrates and are electrically connected by micro bumps or the like is known.

  Patent Document 1 discloses a first semiconductor substrate including a pixel provided with a photoelectric conversion unit and a readout circuit for signal readout, and a second semiconductor substrate including a peripheral circuit for processing a signal read from the pixel. And a back-illuminated solid-state imaging device.

JP 2009-170448 A

  A semiconductor substrate having various circuits needs to protect the element from moisture and ions entering from the atmosphere around the semiconductor substrate. Therefore, in a solid-state imaging device having a first semiconductor substrate and a second semiconductor substrate as described in Patent Document 1, protection from moisture and ions entering from the surrounding atmosphere or the like has been demanded.

  Accordingly, an object of the present invention is to provide a solid-state imaging device with improved moisture resistance.

  The solid-state imaging device of the present invention includes a plurality of pixels each having a photoelectric conversion unit and a readout circuit for processing a signal generated in the photoelectric conversion unit or reading the signal, and a signal for reading the signals of the plurality of pixels A plurality of photoelectric conversion units arranged on a first member, at least a part of the readout circuit, and the peripheral circuit arranged on a second member, and a signal from the photoelectric conversion unit The solid-state imaging device is configured such that the first member and the second member are bonded together so that the readout circuit disposed on the second member receives, and from the outside of the solid-state imaging device, A plurality of pixels and a seal portion that suppresses intrusion of moisture into the peripheral circuit, the seal portion being a first seal portion disposed on the first member and a second portion disposed on the second member; And a first sealing portion. And a portion is in contact part and the second sealing portion of Lumpur portion.

  According to the present invention, for example, it is possible to provide a solid-state imaging device in which intrusion of moisture from the outside is suppressed.

1 is a perspective view and a plan view of a solid-state imaging device according to Embodiment 1. FIG. 1 is a circuit diagram of a solid-state imaging device in Embodiment 1. FIG. 3 is a schematic plan view illustrating a planar layout of the solid-state imaging device according to Embodiment 1. FIG. 1 is a schematic cross-sectional view of a solid-state imaging device in Embodiment 1. FIG. 1 is a schematic cross-sectional view of a solid-state imaging device in Embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the solid-state imaging device according to Embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the solid-state imaging device according to Embodiment 1. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the solid-state imaging device according to Embodiment 1. FIG. 6 is a schematic cross-sectional view of a solid-state imaging device according to Embodiment 2. FIG. FIG. 6 is a schematic cross-sectional view of a solid-state imaging device in Embodiment 3. 6 is a schematic cross-sectional view of a solid-state imaging device according to Embodiment 3. FIG. 6 is a schematic cross-sectional view of a solid-state imaging device in Embodiment 4. FIG. FIG. 10 is a schematic cross-sectional view of a solid-state imaging device in Example 5.

  Hereinafter, the present invention will be described in detail with reference to the drawings. In the description of the embodiments, one main surface of the first substrate and one main surface of the second substrate are substrate surfaces on which photoelectric conversion units or transistors are arranged. The opposite surfaces facing the main surface are the back surface of the first substrate and the back surface of the second substrate. In particular, the upper direction is the direction from the back surface to the main surface, and the lower direction and the depth direction are The direction is from the main surface to the back surface of the substrate.

  In the present invention, a seal ring will be described as an example of a seal portion that suppresses intrusion of moisture from the outside. However, the present invention is not limited to the ring shape as long as it has a function of suppressing intrusion of moisture and the like.

Example 1
A first embodiment of the present invention will be described with reference to FIGS.

  1A and 1B show a solid-state imaging device according to a first embodiment. FIG. 1A is a perspective view of the solid-state imaging device, and FIG. 1B shows light incident on the solid-state imaging device of FIG. As shown in FIG. 1A which is a plan view seen from the side, the solid-state imaging device according to the present embodiment includes a first member 308 having a structure in which a first member 308 and a second member 309 are bonded to each other. The two members 309 each have a first substrate and a second substrate, and a wiring structure is disposed between the first substrate and the second substrate, and preferably the wiring structure includes a plurality of wiring layers. In the case where A and B are given as subscripts, for the sake of convenience, A is given to the configuration arranged on the first member 308, and B is given to the configuration arranged on the second member 309.

  The first member 308 is arranged closer to the light incident side than the second member 309. In FIG. 1B, the left half of the drawing shows the first member 308, and the right half is the portion where the first member 308 exists. The first member 308 showing the second member 309 is not shown, and the right half not shown can be laid out similarly to the left half.

  In FIG. 1, a pixel unit 301 </ b> A, which is a pixel unit, 301 </ b> A and 301 </ b> B is provided with a plurality of photoelectric conversion units corresponding to the pixels 118, and a microlens 118, which is a microlens, transmits light to each photoelectric conversion unit. The main part of the peripheral circuit 120 in which various circuits for reading signals of the pixel unit 301 that is a peripheral circuit are arranged is arranged on the second member 309, but a part of the peripheral circuit 120 is arranged. It can also be arranged on the first member 308.

  Reference numeral 312A denotes a pad portion. A plurality of pads 313 are arranged on the pad portion 312A. The plurality of pads 313 may include an input pad for exchanging signals and the like with an external circuit and an output pad (hereinafter referred to as a pad). For example, a conductive pattern that is a part of a wiring structure can be formed by a conductive pattern. Normally, a conductive pattern that forms a wiring is surrounded by an insulator. However, in order to electrically connect a pad and an external circuit, An opening 100 is disposed in the insulator.

  In the first member 308 in which the seal rings 150A, 151A, 152A, and 150B for suppressing the ingress of moisture from the outside are arranged, the seal ring 150A is arranged on the outermost periphery of the first member 308, and the seal Inside the ring 150A, the seal ring 152A is disposed between the pad portion 312A and the pixel portion 301A. Further, the seal ring 151A is disposed so as to surround each pad 313 disposed on the pad portion 312A. Further, the seal ring 150B is arranged on the outermost periphery of the second member 309, that is, the first member 308 has a first seal portion including the seal rings 150A to 152A, and the second member has 150B. The seal ring having the second seal portion configured to include mainly water from the outside with respect to the members on which the seal rings are arranged. As described later, a part of the first seal part and a part of the second seal part are in contact with each other, more specifically, a surface facing the second member 309 of the first seal part, A surface of the second seal portion facing the first member 308 is in contact.

  Here, the seal ring according to the present invention, which will be described in more detail with respect to the seal ring, can be classified into four types according to the arrangement, and in the following embodiments, these four types of seal rings are appropriately combined to constitute the seal portion.

  First, as a first classification, seal rings 150A and 150B in which the reference numerals 150A and 150B are shaken in the following embodiments, which are seal rings arranged on the outermost peripheral portion of each member, are included in each pixel. The outer peripheral circuit portion and the pad portion are disposed outside.

  As a second classification, reference numerals 151A and 151B are given in the following embodiments, which are seal rings arranged around each pad arranged in the pad portion and arranged so as to surround the pad.

  As a third category, reference numerals 152A and 152B are assigned in the following embodiments, which are seal rings arranged between the pad portion and the pixel portion or between the pad and the peripheral circuit portion.

  As a fourth category, this seal portion, which is a seal portion formed of an insulator disposed on the bonding surface of each member, can be used as a passivation layer. Specifically, SiN or SiON is used. Since these are capable of absorbing moisture as compared with SiO2, they have a high sealing function.

  In the present invention, the seal portion is configured by appropriately combining the seal rings classified into the above four, and more specifically, the first seal portion disposed on the first member and the second seal disposed on the second member. In order to enhance the sealing function in which the parts are in contact with each other to form the seal part, it is preferable to contact the seal rings of the same classification among the seal parts arranged in the respective members.

  Next, an equivalent circuit diagram of the solid-state imaging device according to the first embodiment will be described with reference to FIG. 2. In this embodiment, the solid-state imaging device 300 in FIG. A pixel unit 301 in which a plurality of pixels having a readout circuit for processing or reading out signals generated in the unit and the photoelectric conversion unit are arranged, and a peripheral circuit unit 302 for reading out signals from the plurality of pixels A plurality of peripheral circuits 120 shown in FIG.

  The pixel unit 301 includes a photoelectric conversion unit 303, a transfer transistor 304, an amplification transistor 306, and a single photoelectric conversion unit 303 in which a plurality of reset transistors 307 are arranged. In the pixel, the source of the transfer transistor 304 including the photoelectric conversion unit 303, the transfer transistor 304, the amplification transistor 306, and the reset transistor 307 is connected to the photoelectric conversion unit 303, and the drain of the transfer transistor 304 is connected to the amplification transistor 306. The source of the reset transistor 307 whose node is the same node as the gate of the amplification transistor 306 connected to the gate is connected to the node 305, and the potential of the node 305 is set to an arbitrary potential (for example, reset potential). Reset transistor 307 The drain can be supplied with a reset voltage. The amplification transistor 306 is a part of a source follower circuit, and a node 305 that outputs a signal corresponding to the potential of the node 305 to the signal line RL is a floating diffusion. Can be configured.

  The peripheral circuit unit 302 is provided with a plurality of peripheral circuits, for example, a vertical scanning circuit VSR for supplying a control signal to the gate of the transistor of the pixel unit 301, and a signal output from the pixel unit 301 is amplified or added, or The peripheral circuit unit 302 includes a readout circuit RC that performs signal processing such as AD conversion. The peripheral circuit unit 302 includes a horizontal scanning circuit HSR that supplies pulses for sequentially outputting signals from the readout circuit RC.

  Here, in the solid-state imaging device according to the first embodiment, the plurality of photoelectric conversion units 303 are arranged on the first member 308, and at least a part of the pixel readout circuit and the peripheral circuit are arranged on the second member 309. Specifically, the photoelectric conversion unit 303 and the transfer transistor 304 are the pixel unit 301A arranged on the first member 308, and the other pixel components are the pixel unit arranged on the second member 309. The arrangement of the transistors in the pixel portion of the first substrate and the second substrate is not limited to the above-described configuration, and can be appropriately changed according to the situation.

  The connection unit 310 is a specific configuration of the connection unit 310 that is a node for electrically connecting the gate of the transfer transistor 304 disposed on the first substrate and the peripheral circuit 120 disposed on the second member. To do.

  The charge generated in the photoelectric conversion unit 303 may include a configuration in which the drain of the transfer transistor 304, that is, the node 305 read out to the node 305, is disposed on the first member 308 and a configuration disposed on the second member 309. Specifically, the configuration included in the first member 308 includes the floating diffusion and the configuration included in the second member 309 which is a part of the first wiring structure electrically connected to the floating diffusion, the source of the reset transistor 307. , A part of the second wiring structure that electrically connects the gate of the amplification transistor 306 and these and a part of the first wiring structure.

  Such a configuration makes it possible to increase the area of the photoelectric conversion unit 303 and improve sensitivity compared to the case where all of the pixel unit and the peripheral circuit unit are arranged on one conventional member (that is, one substrate). In addition, if the area of the photoelectric conversion unit is the same as that of the conventional configuration, a large number of photoelectric conversion units 303 can be provided, and the number of pixels can be increased. A part of the first wiring structure of the member 308 and a part of the second wiring structure of the second member 309 can constitute a seal portion that suppresses moisture entering from the outside of the solid-state imaging device.

  A specific planar layout of the solid-state imaging device will be described with reference to the schematic plan view of the solid-state imaging device in FIG. 3. FIG. 3A is a top view illustrating the planar layout of the first member 308. (B) is a top view for showing a planar layout of the second member 309. Parts having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  3A, the first member 308 includes a pixel portion 301A in which a plurality of photoelectric conversion units 303 are disposed and a pixel portion 301A in which a pad portion 312A in which a plurality of pads 313 are disposed is disposed. A plurality of photoelectric conversion units 303 and transfer transistors 304 are arranged, and a connection unit 314A for electric connection with the second member 309 is arranged at the same position as the pad 313 in a plane. Can be constituted by a conductive pattern formed in the same layer as the wiring layer included in the wiring structure.

  When the pad 313 is an input pad, a signal or a power supply voltage input to the pad 313 is supplied to the circuit of the second member 309 via the connection portion 314A. The signal from the second member 309 is transmitted to the pad 313 via the connection portion 314A. Note that the pad is an electrode pad or a semiconductor substrate disposed in the wiring layer and electrically connected to an external circuit. An electrode pad connected to a through electrode penetrating from one surface of the other to the opposite surface is included.

  Next, in FIG. 3B, the pad itself is not disposed on the pad portion 312B where the pixel portion 301B, the peripheral circuit portion 302B, and the pad portion 312B are disposed on the second member 309. In the second member 309, the pixel portion 301B, which is a region where a conductive pattern for electrical connection with the pad 313 is provided, is provided with a transistor that constitutes a pixel readout circuit. For example, the amplification transistor in FIG. 306 and a plurality of reset transistors 307 are arranged in the peripheral circuit section 302. The horizontal scanning circuit HSR, the vertical scanning circuit VSR, and the pad section 312B in which the readout circuit RC is arranged are connected to the first member 308. A horizontal scanning circuit HSR, a vertical scanning circuit VSR in which a connection unit 314B for connection with the unit 314A is arranged, and readout And the circuit RC, are electrically connected through the lead wires 316 and the connecting portion 314B corresponding to each.

  The first member 308 and the second member 309 having the planar layout shown in FIGS. 3A and 3B are the solid-state imaging device of this embodiment in which the two members shown in FIG. 1 are bonded together. Specifically, the pixel portion 301A and the pixel portion 301B are arranged so as to overlap each other, and the connection portion 314A and the connection portion 314B are connected. In FIG. A part of the scanning circuit may be arranged in the peripheral circuit portion 302A in which the region of the first member 308 corresponding to the peripheral circuit portion 302B of the two members 309 is shown as the peripheral circuit portion 302A, or circuit elements may be arranged. Note that the first member 308 has at least a photoelectric conversion unit in relation to the roles of the first member 308 and the second member 309, and the second member 309 has at least one of a pixel readout circuit or a peripheral circuit. Having.

  Next, in the following description describing the seal portion of the first member 308, the first member 308 showing the arrangement in the case where the seal portion is vertically projected onto the first substrate 101 from the second member 309 side is: The seal ring 150A is disposed on the outermost periphery. Here, the outermost periphery refers to, for example, that no circuit element is disposed outside or a conductive pattern is disposed on the outer periphery. In the plurality of pads 313 arranged around the periphery of 301, a seal ring 151A is arranged so as to surround each pad 313. The seal ring 151A is a semiconductor region arranged on the pad 313 and the first substrate 101. It is possible to form an electrostatic breakdown protection circuit including a semiconductor region to which the seal ring 151A is connected. An example of the electrostatic discharge protection circuit is by a seal ring 151A, which can be used a protective diode, it is possible to suppress the infiltration of water from the pad opening 100, it is possible to suppress the influence of noise from outside.

  When the seal ring 151A in which the seal ring 152A is disposed between the pad portion 312A and the pixel portion 301 is provided, the seal ring 152A includes the end portion on the pixel portion side of the seal ring 151A and the pixel portion. Preferably, the seal ring 152 </ b> A surrounds the periphery of the pixel portion 301.

  Next, the arrangement in the following explanation for explaining the seal portion of the second member 309 shows the arrangement when projected from the first member 308 side perpendicularly onto the second substrate 121.

  When the seal ring 150B of the second member 309 has a plurality of lead wires 316 for electrically connecting the peripheral circuits 120 arranged on the outermost peripheral portion of the second member 309 and the connection portions 314B. The seal ring 150B is preferably arranged outside the plurality of lead wires 316. Preferably, the seal ring 150B is arranged so as to surround the plurality of lead wires 316 as shown. When the pad 313 is disposed on the pad portion 312B, a seal ring 151B (not shown) disposed in the same manner as the seal ring 151A of the first member 308 may be provided.

  When the first member 308 and the second member 309 are bonded to each other, the positional relationship of the seal ring in each member can be either overlapping or non-overlapping. In particular, the passivation layer is disposed on the surface side of the wiring structure. In this case, the seal rings of the first and second members do not have to overlap. This is because the passivation layer forms a part of the seal portion. As a specific material that is preferably made of a material having higher hygroscopicity than the film, a material containing nitrogen is used, and SiN, SiON, or the like can be used.

  Further, by disposing the first member 308 and the second member 309 so that the seal rings made of a conductor are in contact with each other, the moisture resistance is improved, and further, the reliability is improved. In this case, it is possible to form a seal portion by bringing the seal rings formed of the conductors of the members into contact with each other and integrating them continuously. In this case, the wafer of the first member 308 and the wafer of the second member 309 are combined. When dicing later, the expansion of the chipping range can be suppressed by the seal ring, and the yield and reliability are improved.

  4 is a schematic cross-sectional view taken along the line XX ′ of FIG. 1, and is a diagram illustrating the solid-state imaging device having the circuit and planar layout shown in FIGS. 2 and 3. In FIG. The same components as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the solid-state imaging device of this embodiment, the first substrate having the first substrate, the second substrate, and the wiring structure disposed between the first substrate and the second substrate is preferably a semiconductor substrate, The second substrate included in the first member 308 is preferably a semiconductor substrate and included in the second member 309.

  The wiring structure preferably has a structure in which a plurality of wiring layers are stacked with an insulating layer interposed therebetween. Also, in the wiring structure, the first member 308 has the first wiring structure and the second member. 309 may be configured to have a second wiring structure. In this case, both the first wiring structure and the second wiring structure have a structure in which a plurality of wiring layers are stacked via an insulating layer. Alternatively, only one of the first and second members may have a wiring structure.

  The first member 308 includes a first wiring structure having at least an insulating layer and a wiring layer and a first substrate 101. The first substrate 101 is, for example, a semiconductor substrate, and has a main surface 102 and a back surface 103. The first substrate 101 in FIG. 2 is an n-type silicon semiconductor substrate. The first wiring structure in which the photoelectric conversion portion 303 is disposed on the main surface 102 of the first substrate includes an interlayer insulating film 104 to 106, a gate electrode, and a gate. In addition, the interlayer insulating film 106 including the gate electrode layer 107 including the wiring and further including the wiring layers 109 and 111 including the plurality of wirings and the plug layers 108 and 110 including the plurality of contact plugs or via plugs has the first wiring structure. In this embodiment, which is a passivation layer disposed on the outermost surface, an insulating film having SiN is used as the passivation layer.

  The first substrate 101 is provided with an n-type semiconductor region 112 that constitutes the photoelectric conversion unit 303, an n-type semiconductor region 114 that is a drain of the transfer transistor, that is, a floating diffusion, and an element isolation structure 119. The element isolation structure 119 may be configured using an insulator, or PN junction isolation may be used without using an insulator, or a combination of both may be used. And the n-type semiconductor region 114 and the gate electrode 113 included in the gate electrode layer 107. Here, the charge of the n-type semiconductor region 112 is driven by the driving pulse supplied to the gate electrode 113. The potential based on the charge transferred to the n-type semiconductor region 114 transferred to the region 114 is the plug layer 108 and the wiring layer 1. 9, part of the conductive pattern included in the wiring layer 111 transmitted to the second member 309 via the plug layer 110 and the wiring layer 111 constitutes the connection portion 311A. Note that the photoelectric conversion unit 303 further includes a light receiving surface. It may be a buried photodiode having a p-type semiconductor region on the side or a photogate, and can be changed as appropriate.

  On the back surface 103 side of the first substrate 101 of the pixel portion 301A, a planarization layer 115, a color filter layer 116 including a plurality of color filters, a planarization layer 117, and a microlens layer 118 including a plurality of microlenses are arranged in this order. In FIG. 4, the plurality of color filters and the plurality of microlenses each correspond to one photoelectric conversion unit, that is, are arranged for each pixel, but are provided for each of the plurality of pixels. The solid-state imaging device according to the present embodiment may be a so-called back-illuminated solid-state imaging device in which light enters from the microlens layer 118 side and is received by the photoelectric conversion unit.

  The pad portion 312A of the first member 308 is provided with a pad 313 and an opening 100 that exposes the pad 313, and a connection portion 314A that is electrically connected to the pad 313 is disposed. The part 314 </ b> A is configured by a conductive pattern included in the wiring layer 111.

  The seal rings 150A, 151A, and 152A in which the seal ring is configured by a part of the first wiring structure of the first member 308 can be formed by a conductive pattern formed in the same process as the wiring layer and the plug layer.

  A region obtained by projecting the seal ring 150A perpendicularly from the second member 309 side to the first substrate 101 is disposed on the outermost periphery of the first member. Therefore, a region where a plurality of photoelectric conversion units of the first substrate are disposed, that is, a pixel. The part 301A is provided outside the pixel part 301A and the pad part 312A and surrounds the whole of the pixel part 301A and the pad part 312A.

  A region in which the seal ring 152A is vertically projected from the second member 309 side to the first substrate 101 is disposed between the pixel portion 302 and the pad portion 312A. More preferably, the seal ring 152A surrounds the pixel portion 301A. Yes.

  This arrangement relationship can be more easily understood with reference to FIGS. 4 and 3A, and the seal rings 150A and 152A are arranged from the main surface 102 of the first substrate 101 to the first substrate 101 of the interlayer insulating film 106. In other words, in the seal rings 150A and 152A, the conductor is continuously arranged from the semiconductor substrate to the surface in contact with the second member 309 of the interlayer insulating film 106 functioning as a passivation film. Structure.

  In this embodiment, a seal ring 151A is further provided around each pad 313 disposed on the pad portion 312A.

  If at least one of the seal rings 150A and 152A is provided, the moisture intrusion path from the end portion of the solid-state imaging device and the pad opening to the element in the solid-state imaging device becomes narrow, so that moisture resistance can be ensured.

  In addition, each seal ring is arranged in the first substrate 101, and the substrate potential is supplied through, for example, semiconductor regions 114 ′ and 112 ′ having the same conductivity type as the first substrate 101. Then, the influence of external noise can be suppressed.

  The second member 309 includes the second wiring structure and the second substrate 121. The second substrate 121 is, for example, a semiconductor substrate, and a transistor is disposed on the main surface 122 of the second substrate having the main surface 122 and the back surface 123. The second wiring structure includes an interlayer insulating films 124 to 127, a gate electrode layer 128 including a gate electrode and wiring, wiring layers 130, 132, and 134 including a plurality of wirings, and a plug including a plurality of contacts or vias. In addition, the conductive pattern included in the wiring layer 134 that is the uppermost wiring layer includes the layers 129, 131, and 133, and the interlayer insulating film 127 that includes the electrical connection portion with the first member 308 is the uppermost layer of the second wiring structure. Here, SiN or SiON containing nitrogen can be used as the passivation layer which is a passivation layer disposed on the surface.

  In the pixel portion 301B of the second substrate 121, a p-type semiconductor region 135 that provides a channel of the amplification transistor 306, an n-type source region and drain region 138 of the amplification transistor 306, and an element isolation structure 136 are arranged. The amplification transistor 306 includes a gate electrode 137 included in the gate electrode layer 128, a source region, and a drain region 138. Here, the connection portion 311A of the first member 308 and the gate electrode 137 of the amplification transistor are different from each other. 2 are electrically connected through the wiring layer 134, the plug layer 133, the wiring layer 132, the plug layer 131, the wiring layer 130, and the plug layer 129. Here, the node 305 in FIG. 2 is the n-type semiconductor in FIG. The region 114, the wiring of the wiring layers 109, 111, 134, 132, 130, and the plug layers 108, 110, 133, 13 A contact plug or via plug 129, the other circuit of the pixel portion 301B configured to include a gate electrode 137, a (e.g., the reset transistor) are not shown.

  In FIG. 4 in which the horizontal scanning circuit HSR and the vertical scanning circuit VSR are arranged in the peripheral circuit portion 302 of the second member 309, n-type transistors and p-type transistors of arbitrary circuits included in the peripheral circuit portion 302 Is configured to include a gate electrode 140 included in the gate electrode layer 128, an n-type source region and a drain region 141 disposed in the P-type semiconductor region 139, and p The type transistor includes a gate electrode 143 included in the gate electrode layer 128 and a p-type source region and drain region 144 disposed in the n-type semiconductor region 142.

  The seal ring 150B can be configured by using a part of the wiring layer and plug layer constituting the second wiring structure, and the region in which the seal ring 150B is vertically projected from the first member 308 side onto the second substrate 121 is the first region. This arrangement relationship arranged on the outermost peripheral part of the two members 309 or arranged outside the peripheral circuit part 302 including various peripheral circuits can be understood more easily with reference to FIGS. 4 and 3B. The seal ring 150B is arranged from the main surface 122 of the second substrate 121 to the surface of the interlayer insulating film 127 that functions as a passivation film on the side opposite to the second substrate 121. In other words, the seal ring 150B is This is a structure in which conductors are continuously arranged from the semiconductor substrate to the surface in contact with the first member 308 of the interlayer insulating film 106 functioning as a passivation film.

  As shown in FIG. 4, the seal rings 150A and 150B are in contact with each other. More specifically, the conductive pattern of the wiring layer 111 constituting the outermost surface of the seal ring 150A on the second member 309 side, and the seal ring 150B The conductive pattern of the wiring layer 134 constituting the outermost surface on the first member 308 side is in contact.

  The seal ring 150B is supplied with the substrate potential through the semiconductor regions 138 ′ and 139 ′ having the same conductivity type as that of the second substrate 121 and disposed in the second substrate 121. The influence of can be suppressed.

  As described above, the main surface 102 of the first substrate 101 and the main surface 122 of the second substrate 121 face each other, and the first member 308 and the second member 309 are bonded together (opposite arrangement) to constitute a solid-state imaging device. doing.

  With such a configuration, moisture can be prevented from entering the pixel portion 301A of the first member 308 and the element region including the pixel portion 301B and the peripheral circuit portion 302B of the second member 309.

  In addition, since the exposed surface of the pad 313 is disposed on the back surface side of the first member 308, electrical connection from an external circuit to the pad 313 is facilitated, and connection failure is suppressed.

  Here, the solid-state imaging device of FIG. 5A described with reference to FIGS. 5A and 5B of the schematic cross-sectional views showing the modification of the solid-state imaging device of FIG. The difference from the device is that the insulating layer 106 'whose function as a passivation layer is smaller than SiN or the like is disposed on the outermost surfaces of the first and second wiring structures, and has the same function as the structure of FIG. The same reference numerals are given to the parts having the same and detailed description is omitted.

  Further, in the configuration of FIG. 5A, even in this case where the seal ring 152A is not provided, it is possible to ensure a certain moisture resistance by the seal ring 151A, whereas the seal rings 150A and 150B are With this arrangement, the possibility of intrusion of moisture and the like from the outermost surfaces of the first and second members 308 and 309 due to the absence of the passivation layer can be suppressed.

  Next, the solid-state imaging device of FIG. 5B for explaining the solid-state imaging device of FIG. 5B is different from the solid-state imaging device of FIG. 4 in that the seal rings 150A and 151A are not provided. In the case of such a structure in which the seal rings 152A and 150B in which the interlayer insulating films 106 ′ and 127 ′ functioning as passivation layers are disposed on the outermost surfaces of the first and second members 308 and 309 are disposed. The conductive pattern of the first member 308 and the conductive pattern of the second member 309 for establishing electrical connection between the pad 313 and the second member 309 also constitute a part of the seal portion. Each seal ring capable of suppressing intrusion of moisture or the like from the cross section of the first wiring structure at 100 is a conductive pattern made of the same material as the wiring layer and plug layer included in the wiring structure. It has the laminated structure.

  Next, the manufacturing method of the solid-state imaging device of FIG. 4 according to the present embodiment will be described with reference to FIGS. 6 to 8. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the first member 308, and FIG. FIG. 8 is a schematic cross-sectional view showing the manufacturing process of the member 309, and FIG. 8 is a schematic cross-sectional view showing the manufacturing process after the first member 308 and the second member 309 are joined.

  The manufacturing process of the first member 308 in FIG. 4 will be described with reference to FIG. 6. In FIG. 6, the configuration to be the first member 308 in FIG. , Pad portions 312 and regions to be circuit elements are 301 ′, 302 ′ and 312 ′, and regions to be seal rings 150A, 151A and 152A are seal rings 150A ′, 151A ′ and 152A ′.

  First, a semiconductor substrate 401 is prepared, and an element is formed on the semiconductor substrate 401. The semiconductor substrate 401 has a main surface 402 and a back surface 403, and the main material constituting the semiconductor substrate 401 whose thickness is D3 is silicon.

  The element isolation structure 119 for forming the element isolation structure 119 on the semiconductor substrate 401 has an insulator, for example, a LOCOS or STI structure, or a structure having both PN junction isolation and insulator and PN junction isolation. Then, semiconductor regions (not shown) that function as P-type and N-type wells are formed on the semiconductor substrate 401, and then n-type semiconductor regions 112 and 114 that constitute a photoelectric conversion unit are formed, and a seal ring is also formed. The n-type semiconductor regions 112 ′ and 114 ′ that form the n-type semiconductor regions 112 ′ and 114 ′ that are electrically connected to the conductor can have the same conductivity type as the substrate.

  Next, the gate electrode layer 107 for forming the gate electrode layer 107 is formed of, for example, polysilicon, and may include not only the gate electrode but also wiring. Here, a method for forming the gate electrode, element isolation, and semiconductor region is generally described. Thus, the structure shown in FIG. 6A can be obtained.

  Next, the first wiring structure 321 that forms the first wiring structure 321 on the main surface of the semiconductor substrate 401 includes the interlayer insulating films 104, 105, 106, the plug layers 108, 110, and the wiring layers 109, 111. Here, the interlayer insulating film is formed of a silicon oxide film, a silicon nitride film, an organic resin, or the like, and the wiring layer is an outermost interlayer insulating film made of a wiring mainly composed of aluminum or a conductor mainly composed of copper. When the interlayer insulating film 106 is a passivation film, a contact plug that can be formed of a silicon oxynitride film or a silicon nitride film is formed of, for example, tungsten, and a via plug is formed of copper as a wiring material formed of tungsten. As a so-called damascene structure, copper can be the main component of the material constituting the via plug. Here, the wiring layer 111 is formed. As the material of the conductive pattern in which the connection portion 314A is configured by the conductive pattern to be formed, copper can be the main component. In addition, the pad material in which the pad 313 is configured by the conductive pattern included in the wiring layer 109 is mainly aluminum. The wiring layer, the plug layer, and the interlayer insulating film, which are the components, can be formed by a general semiconductor process, and detailed description thereof is omitted, whereby the configuration shown in FIG. 6B is obtained.

  Next, the manufacturing process of the second member 309 in FIG. 4 will be described with reference to FIG. 7. In FIG. 7, the configuration to be the second member 309 in FIG. The regions that become the peripheral circuit portion 302B and the pad portion 312B are 301 ′, 302 ′, and 312 ′, and the regions that become the seal ring 150B are 150B ′.

  First, a semiconductor substrate 404 is prepared, and an element is formed on the semiconductor substrate 404. The semiconductor substrate 404 has a main surface 405 and a back surface 406, and its thickness is D4. The semiconductor substrate 404 is formed using a LOCOS or STI structure. An element isolation structure 136 is formed, and P-type semiconductor regions 135 and 139 that function as p-type wells and an n-type semiconductor region 142 that functions as an n-type well are formed in a semiconductor substrate 404. Thereafter, transistors are formed. The n-type semiconductor regions 138 and 141 and the p-type semiconductor region 144 that can serve as the source region and the drain region, and the semiconductor region that constitutes the protective diode are formed, and is electrically connected to the conductor that constitutes the seal ring. The n-type semiconductor regions 138 ′ and 139 ′ forming the n-type semiconductor regions 138 ′ and 139 ′ have the same conductivity as the substrate. A gate electrode layer 128 including transistor gate electrodes 137, 140, 143 and wiring (resistance) is formed by deposition and patterning of a polysilicon layer. Here, the gate electrode, element isolation, and semiconductor region are formed. The formation method can be performed by a general semiconductor process, and the detailed description thereof is omitted. Thus, the structure in FIG. 7A is obtained.

  Next, the wiring structure for forming the second wiring structure 322 on the main surface of the semiconductor substrate 404 includes interlayer insulating films 124 to 127, plug layers 129, 131, 133, and wiring layers 130, 132, 134. Here, the interlayer insulating film is formed of a silicon nitride film that is a silicon oxide film, an organic resin, or the like, and the wiring layer is formed of wiring mainly composed of aluminum or wiring mainly composed of copper. The connection portion 314B is configured by the conductive pattern of the above, and the interlayer insulating film 106, which is the outermost interlayer insulating film made of a material mainly composed of copper, is a silicon oxynitride film or silicon nitride film so as to function as a passivation film. The manufacturing method of these wiring layers, plug layers, and interlayer insulating films formed of films can be formed by a general semiconductor process, and detailed description thereof is omitted. Above by the configuration shown in FIG. 7 (B) is obtained.

  Next, the first member 308 ′ and the second member 309 ′ shown in FIGS. 6B and 7B are bonded so that the main surface 402 and the main surface 405 of the semiconductor substrates face each other. That is, the uppermost surface of the wiring structure of the first member 308 ′ and the uppermost surface of the wiring structure of the second member 309 ′ are joined. Here, the first connection portions 311, 314, and 801 are conductive materials mainly composed of copper. Since it is composed of a pattern, the conductive pattern on the outermost surface that is in direct contact with the seal ring 150B of the seal ring 150A and the seal ring 150A of the seal ring 151B can be directly in contact with each other when bonding is performed by copper metal bonding. The conductive pattern on the outermost surface constitutes the connection portion 152. The wiring is formed by the first wiring structure 321 shown in FIG. 6B and the second wiring structure 322 shown in FIG. Concrete 320 is formed.

  After the first member 308 ′ and the second member 309 ′ are joined, the thickness of the first member 308 ′ may be reduced by removing the back surface 403 side of the semiconductor substrate 401. That is, the first member 308 ′ is a thin film. Alternatively, the thickness of the second member 309 ′ may be reduced by removing the back surface 406 side of the semiconductor substrate 404, that is, the second member 309 ′ is thinned. The semiconductor substrate 401 becomes the semiconductor substrate 101, and the thickness is changed from D3 to D1 (D1 <D3) (FIG. 8A). Thus, the semiconductor substrate 401 is thinned in this way. Thus, the semiconductor substrate 404 that allows incident light to efficiently enter the photoelectric conversion portion later becomes the semiconductor substrate 121, and the thickness changes from D4 to D2 (D2 <D4). (FIG. 8A) At this time, if the second member 309 ′ is not thinned such that the thickness D1 of the semiconductor substrate 101 <the thickness D2 of the semiconductor substrate 121, the thickness D1 of the semiconductor substrate 101 <the semiconductor substrate 101 The thickness D4 is 404.

  Next, a planarizing layer 115 made of resin, a color filter layer 116, a planarizing layer 117 made of resin, and a microlens layer 118 are formed in this order on the back surface 408 of the semiconductor substrate 101. The manufacturing method of the microlens layer can be formed by a general semiconductor process, and detailed description thereof is omitted. Here, the microlens layer may be formed up to the region of 312 ′ serving as the pad portion. Thus, the configuration of FIG. 8B is obtained.

  Then, an opening 100 for exposing the surface of the pad 313 is formed. Here, a photoresist mask having an arbitrary opening is provided on the microlens layer 118 using a photolithography technique, and a dry etching technique is used. The microlens layer 118, the planarization layer 117, the color filter layer 116, the planarization layer 115, the semiconductor substrate 101 and the interlayer insulating film 104 ′ are removed, an opening 100 exposing the pad 313 is formed, and the microlens layer 118, Through the above steps in which the planarization layers 117 and 115, the color filter layer 116, the semiconductor substrate 101, and the interlayer insulating film 104 are formed, the configuration in FIG. 8C, that is, the same configuration as that in FIG. 4 is obtained.

  As described above, the seal rings 150A, 151A, 152A, and 150B can be formed in the same process as the wiring of the wiring structure. Note that the pad 313 can function as an etching stopper during etching.

  The present invention is not limited to the steps described in the manufacturing method of the present embodiment, the order of the steps may be changed, and the second member 309 may be formed following the first member 308. Alternatively, the first member 308 and the second member 309 can be purchased and bonded to each other. An SOI substrate is applied to the semiconductor substrates 401 and 402. It is also possible.

(Example 2)
Embodiment 2 of the present invention will be described with reference to FIG. 9. FIGS. 9A, 9 B, and 9 C are schematic cross-sectional views of the solid-state imaging device, and the solid state shown in FIG. 4 respectively. In FIG. 9, which is a cross-sectional view showing a modification of the imaging device, the same components as those in FIG.

  In the present embodiment, the difference from the first embodiment is an electric path from the pad 313 to the second member. In the first embodiment, the pad 313 arranged on the first member is vertically projected in the second member direction. Plugs and wires were placed on the wires, and after the electrical path was formed up to the wiring layer below the second member, electrical connection was made so that signals could be received with the circuit elements of the second member. .

  In contrast, in the present embodiment, an electrical path is provided from the pad 313 to the peripheral circuit portion in the first member, and then the electrical connection with the second member is performed through a plug or the like.

  As shown in FIG. 9A, the first member 808 has a lead wire 316 extending in the horizontal direction from the pad 313 to the peripheral circuit portion, and the second member 809 is horizontal by the lead wire 316 of the first member 808. The seal rings 150A, 151A, 152A, and 150B each having a connecting portion in a region extending in the direction have the same configuration as that of the first embodiment, and the solid-state imaging device in FIG. 9A is provided with the seal ring 151A. Therefore, it is sufficient that at least one of the seal rings 150A and 152A is disposed. However, the configuration in which 150A and 152A are continuously disposed is effective as a moisture-proof effect and a countermeasure against chipping as described in the first embodiment. As long as the pad 313 is disposed on the first member 808 side of the main surface 122 of the second member 809, the pad 313 is disposed at any position. It may be.

  Next, the difference from the solid-state imaging device of FIG. 9A in FIG. 9B, which describes FIG. 9B, is that there is no passivation layer as a passivation layer on the outermost surface of the wiring structure. In this case, since the insulating layer 106 ′ having a smaller function than SiN or the like is disposed, the seal ring 151A is provided, and therefore the seal ring 152A is not necessarily required as shown in FIG. The rings 150A and 151B are arranged and the conductive patterns constituting the outermost surfaces are in contact with each other, so that moisture from each outermost surface of the first and second members due to the absence of the passivation layer, etc. Further, the seal ring 150B of the second member 809 can be suppressed from entering the peripheral circuit portion inside the pad portion and outside the pad portion. In the solid-state imaging device may be disposed 9 (B) until parts are a similar effect is obtained as in FIG. 9 by the seal ring 150B is disposed in the outermost periphery of the second member (A).

  Next, the solid-state imaging device shown in FIG. 9C, which describes the solid-state imaging device shown in FIG. 9C, is different from the solid-state imaging device shown in FIG. In this case, in which the layers are disposed on the outermost surfaces of the first and second members, the seal rings 150A and 150B are not necessarily required, but the seal ring 152A is disposed and such a configuration is a passivation. It can also be said that the layer forms part of the seal ring.

  With this configuration, it is possible to suppress intrusion of moisture or the like from the cross section of the wiring structure at the opening of the pad portion.

(Example 3)
Embodiment 3 of the present invention will be described with reference to FIGS. 10 and 11. FIGS. 10A, 10 </ b> B, and 10 </ b> C are schematic cross-sectional views of the solid-state imaging device. FIG. 11 which is a cross-sectional view showing a modification of the solid-state imaging device shown in FIG. 10 is a further modification of the solid-state imaging device of FIG. 10, and in FIG. 10 and FIG. The description is omitted.

  In the present embodiment, the configuration different from the first embodiment is the arrangement of pads.

  10A is different from the solid-state imaging device of FIG. 4 in that the conductive pattern constituting the pad 1013 is disposed on the second member 909 and the first member corresponding to the pad portion of the first member 908. A part of 908 is penetrated. Further, the second member 909 can use the same configuration as that of the first embodiment for the seal ring having the lead wiring 316 that leads from the pad 313 in the horizontal direction. The influence of external noise can also be suppressed. Since the solid-state imaging device in FIG. 10A has the seal ring 151A, 150A and 150B that only need to have at least one of the seal rings 150A and 152A are connected around the entire circumference. As described in the first embodiment, the configuration is effective as a moisture-proof effect and a countermeasure against chipping.

  Next, FIG. 10B is different from the solid-state imaging device of FIG. 10A in that it does not have a passivation layer and has an insulating function smaller than SiN or the like as a passivation layer on the outermost surface of the wiring structure. In this case, which is an embodiment similar to FIG. 9B in which the layer 106 ′ is arranged, the seal ring 151 A is provided with the seal rings 151 A and 151 B. Therefore, the seal ring 152 A as shown in FIG. Although not necessarily required, this configuration in which the seal rings 150A and 150B are arranged suppresses the possibility of intrusion of moisture and the like from the outermost surfaces of the first and second members due to the absence of the passivation layer. Further, the seal ring of the second member 809 may be arranged outside the peripheral circuit portion inside the pad portion and between the outer peripheral portion outside the pad portion. 10 In the solid-state imaging device (B) can be obtained the same effect 10 (A) and by placing a seal ring 150A on the outer peripheral portion.

  Next, FIG. 10C, which describes the solid-state imaging device of FIG. 10C, is different from the solid-state imaging device of FIG. 10A in that it does not have the seal ring 151A and the passivation layer is first and first. In this case, which is an embodiment having the same concept as the configuration of FIG. 9C, which is a configuration disposed on each outermost surface of the two members, the seal ring 150 </ b> A is not necessarily required, but the seal rings 152 </ b> A, 150 </ b> B, 151 </ b> B. With this arrangement, the intrusion of moisture or the like from the cross section of the wiring structure at the opening of the pad portion can be suppressed. The seal rings 150A and 150B may not be connected over the entire circumference.

  FIG. 11 is a modification of the solid-state imaging device of FIG. 10, in which a pad 313 is arranged on the second member 1009 and a through electrode 317 penetrating the second substrate from the back side of the second substrate with respect to the pad 313 is shown. The pad 313 having the same conductive pattern as that of the wiring layer is an electrode pad connected to the through electrode 317 penetrating from one surface of the semiconductor substrate to the other surface facing the semiconductor substrate, and has been described in the other embodiments. Since it is not necessary to form the seal ring 151A of the pad portion and it is only necessary to have the seal rings 150A and 150B, the back surface of the solid-state imaging device can be connected to another circuit board, so that the solid-state imaging device can be downsized.

Example 4
Embodiment 4 of the present invention will be described with reference to FIG. 12. FIGS. 12A, 12 B, and 12 C are schematic cross-sectional views of a solid-state imaging device, and the solid state shown in FIG. 4 respectively. In FIG. 12, which is a cross-sectional view showing a modification of the imaging device, the same components as those in FIG.

  In the present embodiment, the configuration different from the first embodiment is the arrangement of the lead-out wiring 316 and the pad portion. Note that FIG. 12 shows the first member on the pad for wire bonding as in the solid-state imaging device shown in FIG. 1108 and a part of the second member 1109 are removed.

  FIG. 12A is different from the solid-state imaging device of FIG. 4 in that the portion corresponding to the pad portion of the first member 1108 is removed and the second member 1109 has a pad 313. In order to electrically connect the pad 313 of the member 1109 and the peripheral circuit portion, a lead wiring 316 disposed on the first member 1108 is provided.

  The first member 1108 is provided with seal rings 150A, 151A, 152A as first seal portions, and the second member 1109 is provided with 150B, 151B, 152B as second seal portions, similar to the previous embodiments. The first seal portion and the second seal portion may have a function of suppressing the influence of external noise. The seal ring 152B of the second member 1109 is disposed between the pad portion and the peripheral circuit. Furthermore, the seal ring 152B is preferably arranged so as to surround the periphery of the peripheral circuit portion when projected from the first member 1108 side onto the second substrate of the second member 1109 perpendicularly. Since the solid-state imaging device A) includes the seal ring 151A, it is sufficient that at least one of the seal rings 150A and 152A is disposed. Since having 1B, at least one of the seal rings 150B and 152B may be disposed.

  Next, the structure of FIG. 12B for explaining the solid-state imaging device of FIG. 12B is different from the solid-state imaging device of FIG. 12A in that it does not have a passivation layer. In this case, which is an embodiment having the same concept as FIG. 9 (B) and FIG. 10 (B), in which an insulating layer 106 ′ having a function as a passivation layer smaller than SiN is disposed on the outermost surface of FIG. Since the rings 151A and 151B are provided, the seal ring 152A is not necessarily required as shown in FIG. 12B, but the seal ring 150A is disposed.

  With this configuration, the possibility of intrusion of moisture from the outermost surfaces of the first and second members can be suppressed even when the passivation layer is not disposed. The seal rings 150B and 151B are disposed. In this case, the seal ring 152B is not always necessary, but if the seal ring 152B is provided, the moisture resistance is further improved.

  Next, the configuration of FIG. 12C for explaining the solid-state imaging device of FIG. 12C is different from the solid-state imaging device of FIG. 12A in that the wiring structure does not have the seal ring 151A. The seal ring 150A and the seal ring 152A, in which the passivation layer is arranged on the outermost surfaces of the first and second members, are arranged, and the seal ring 152B is also arranged, whereby the pad portion Infiltration of moisture or the like from the cross section of the wiring structure at the opening can be suppressed. Note that when the pad 313 is disposed on the outermost surface of the second member, the seal ring 152B may not be disposed. If it is arranged, the moisture resistance is further improved.

  The solid-state imaging device in which the first member and the second member are overlapped and connected has been described above. However, the seal rings 150A and 150B of the first member and the second member are electrically connected, and each is a substrate. When the semiconductor regions are connected to each other, the semiconductor regions should have the same conductivity type.

  When the seal ring of the first member and the seal ring of the second member are not connected and arranged independently, it is possible to use semiconductor substrates of different conductivity types. Whether the semiconductor substrate of the member or the second member is of the same conductivity type or different conductivity type, when noise is mixed in one of the members, the other substrate has an effect that it is not easily affected. .

(Example 5)
The solid-state imaging device according to the fifth embodiment, which will be described with reference to FIG. 13, is different from the solid-state imaging devices according to the first to fourth embodiments. The seal rings formed of the body are not in contact with each other, and the passivation layers disposed on the outermost surfaces of the first member and the second member are in contact with each other.

  The first member 1308 has a seal ring 152A made of a conductor. The second member 1309 has a seal ring 150B made of a conductor. The seal rings 152A and 150B are offset in the horizontal direction. However, the conductive patterns constituting the outermost surfaces of each other are not in contact with each other, but the sealing properties are maintained by disposing passivation layers 1301A and 1301B having high hygroscopicity on the outermost surfaces.

  Hereinafter, as an application example of the solid-state imaging device according to each of the above-described embodiments, the imaging system that exemplarily describes an imaging system in which the solid-state imaging device is incorporated is not limited to a device such as a camera that is mainly used for shooting. For example, a camera includes a solid-state imaging device according to the present invention and a processing unit that processes a signal output from the solid-state imaging device. For example, the processing unit may include an A / D converter and a processor that processes digital data output from the A / D converter.

  As described above, according to the solid-state imaging device of the present invention, moisture can be prevented from entering the photoelectric conversion unit and the peripheral circuit unit. Also, according to the manufacturing method of the present invention, the first member and the first member Since the seal ring can be joined simultaneously with the joining by the connecting portion with the two members, it is possible to improve moisture resistance and suppress chipping without increasing the time required for the manufacturing process.

  Note that the present invention is not limited to the structure described in the specification, and the conductivity type and the circuit can be changed to the opposite conductivity type, and the region where the connection portion is different from the pixel portion (for example, the peripheral circuit portion) ), The present invention can be applied and the configurations of the embodiments can be appropriately combined.

301 Pixel Unit 302 Peripheral Circuit Unit 308 First Member 309 Second Member 150 Seal Ring 151 Seal Ring 152 Seal Ring

Claims (20)

A first semiconductor substrate having a first transistor and an opening;
A second semiconductor substrate having a second transistor and overlapping the first semiconductor substrate;
A first layer including a first conductive pattern disposed between the first semiconductor substrate and the second semiconductor substrate and connected to the first transistor;
A second layer including a second conductive pattern disposed between the first layer and the second semiconductor substrate and connected to the second transistor,
The device includes a first portion including the first transistor and the second transistor in a plan view, a second portion positioned between the opening and the second semiconductor substrate, and a seal portion.
The seal portion includes at least a third conductive pattern included in the first layer and a fourth conductive pattern included in the second layer,
The third conductive pattern and the fourth conductive pattern surround the second portion;
A part of the third conductive pattern is located between the second part and the first conductive pattern, and a part of the fourth conductive pattern is located between the second part and the second conductive pattern. A device characterized by that. A first semiconductor substrate having a first transistor and an opening;
A second semiconductor substrate having a second transistor and overlapping the first semiconductor substrate;
A first layer including a first conductive pattern disposed between the first semiconductor substrate and the second semiconductor substrate and connected to the first transistor;
A second layer including a second conductive pattern disposed between the first layer and the second semiconductor substrate and connected to the second transistor,
The device includes a first portion including the first transistor and the second transistor in a plan view, a second portion positioned between the opening and the second semiconductor substrate, and a seal portion.
The seal portion includes at least a third conductive pattern included in the first layer and a fourth conductive pattern included in the second layer,
The third conductive pattern surrounds the first conductive pattern, the fourth conductive pattern surrounds the second conductive pattern;
A part of the third conductive pattern is located between the second part and the first conductive pattern, and a part of the fourth conductive pattern is located between the second part and the second conductive pattern. A device characterized by that.   The apparatus according to claim 1, wherein a thickness of the first semiconductor substrate is smaller than a thickness of the second semiconductor substrate.   4. The device according to claim 1, wherein the second portion includes a fifth conductive pattern located between the opening and the second semiconductor substrate. 5.   The device according to claim 4, wherein an opening is provided in an insulator disposed between the first semiconductor substrate and the second semiconductor substrate between the opening and the fifth conductive pattern.   The apparatus according to claim 4 or 5, wherein a wiring connected to the fifth conductive pattern is provided between the fifth conductive pattern and the second semiconductor substrate. The second portion includes a fifth conductive pattern located between the opening and the second semiconductor substrate,
The third conductive pattern is located between the fifth conductive pattern and the first semiconductor substrate;
The apparatus of claim 1. The second portion includes a fifth conductive pattern located between the opening and the second semiconductor substrate,
The apparatus according to claim 2, wherein the part of the third conductive pattern is located between the first conductive pattern and the fifth conductive pattern.   The apparatus of claim 8, wherein the fifth conductive pattern is included in the first layer.   The apparatus according to claim 4, wherein a distance between the fifth conductive pattern and the second semiconductor substrate is larger than a distance between the second conductive pattern and the second semiconductor substrate.   The apparatus according to claim 4, wherein a distance between the fifth conductive pattern and the second semiconductor substrate is smaller than a distance between the second conductive pattern and the second semiconductor substrate.   The third layer according to claim 1, further comprising a third layer that is disposed between the second layer and the second semiconductor substrate and includes a sixth conductive pattern joined to the second conductive pattern. Equipment.   The third layer includes a seventh conductive pattern surrounding the second portion, and a part of the seventh conductive pattern is located between the second portion and the sixth conductive pattern. The device described.   The first layer includes a conductive pattern surrounding the first conductive pattern and the third conductive pattern, and the second layer includes a conductive pattern surrounding the second conductive pattern and the fourth conductive pattern. 14. The apparatus according to any one of items 13.   The apparatus according to claim 4, wherein a main component of the first conductive pattern is copper, and a main component of the fifth conductive pattern is aluminum.   The device according to claim 1, wherein the first semiconductor substrate has a photoelectric conversion unit.   The device according to claim 16, wherein the first transistor is a transfer transistor that transfers a charge of the photoelectric conversion unit.   The apparatus according to claim 1, further comprising a circuit that performs AD conversion. An apparatus according to any of claims 1 to 18,
And a processing unit for processing a signal output from the device. A camera comprising the apparatus according to claim 1,
A camera in which the device is a back-illuminated solid-state imaging device.

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