JP4354398B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4354398B2
JP4354398B2 JP2004377734A JP2004377734A JP4354398B2 JP 4354398 B2 JP4354398 B2 JP 4354398B2 JP 2004377734 A JP2004377734 A JP 2004377734A JP 2004377734 A JP2004377734 A JP 2004377734A JP 4354398 B2 JP4354398 B2 JP 4354398B2
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substrate
electrode
bonding material
sealing
device portion
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JP2006186091A (en
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太郎 和田
健介 井手
正宏 舩山
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Mitsubishi Heavy Industries Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase or the like in manufacturing costs, and to obtain high junction properties and an improved sealing state in a semiconductor device, such as a multilayer semiconductor device, and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device comprises a first substrate 2 that has a first device 1 while a first bump electrode 6 is formed on the surface; a second substrate 4 that has a second device 3 while a second bump electrode 10 is formed on the surface, and the first bump electrode 6 is joined to the second bump electrode 10 for lamination on the first substrate 2; and a first sealing jointing material 8 and a second sealing joining material 12 that are interposed between the first substrate 2 and the second substrate 4 for joining them while surrounding the first bump electrode 6 and the second bump electrode 10 in the joined state, and seal the internal space in an airtight state. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は、デバイスが形成された基板を積層してなる多層半導体デバイス等の半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device such as a multilayer semiconductor device formed by stacking substrates on which devices are formed, and a method for manufacturing the same.

近年、半導体集積回路の高集積化及び高性能化に伴い、素子の微細化技術に加え、垂直方向にも配線を施して３次元的な配線構造を有する３次元半導体集積回路技術の研究が進められている。この３次元半導体集積回路では、積層された複数層にそれぞれ形成された半導体素子や配線の電気的接続を層間配線を用いて行い、平面方向だけでなく垂直方向においても配線接続することで、平面的な従来の配線構造に比べ、配線自由度が高く、かつ、配線長の短縮化を図ることができる。これにより、素子の微細化に伴って生じる配線抵抗や寄生容量の増大を抑制することが可能になる。   In recent years, along with higher integration and higher performance of semiconductor integrated circuits, research on three-dimensional semiconductor integrated circuit technology that has a three-dimensional wiring structure by wiring in the vertical direction is advanced in addition to element miniaturization technology. It has been. In this three-dimensional semiconductor integrated circuit, electrical connection of semiconductor elements and wirings respectively formed in a plurality of stacked layers is performed by using interlayer wiring, and wiring connection is performed not only in the planar direction but also in the vertical direction. Compared with a typical conventional wiring structure, the degree of freedom of wiring is high and the wiring length can be shortened. As a result, it is possible to suppress an increase in wiring resistance and parasitic capacitance caused by the miniaturization of elements.

この３次元半導体集積回路の技術としては、貼り合わせによる製造方法が提示されている。例えば、特許文献１には、半導体集積回路が形成された複数のウェーハ同士を貼り合わせて複数層の半導体集積回路を積層形成すると共に、互いの半導体集積回路を、バンプを介して垂直方向に層間接続することで、３次元半導体集積回路を構築する技術が提案されている。この技術では、貼り合わせたウェーハの接合部に絶縁エポキシ接着剤等の絶縁性接着剤を注入している。   As a technique of this three-dimensional semiconductor integrated circuit, a manufacturing method by bonding is proposed. For example, in Patent Document 1, a plurality of semiconductor integrated circuits are laminated by laminating a plurality of wafers on which semiconductor integrated circuits are formed, and the semiconductor integrated circuits are stacked in layers in the vertical direction via bumps. A technique for constructing a three-dimensional semiconductor integrated circuit by connecting them has been proposed. In this technique, an insulating adhesive such as an insulating epoxy adhesive is injected into a bonded portion of bonded wafers.

このように絶縁性接着剤を注入するのは、バンプ等による電極での接合だけでは、接合強度が不十分であり、長期安定性や信頼性に欠けてしまうためである。すなわち、絶縁性接着剤でウェーハの接合部（層間接合部）を封止することで、ウェーハの接合性を高めている。併せて、この技術では、絶縁性接着剤が電気的接続部を外界から遮断するため、外部からのガス等の侵入による電気的接続部の汚染や変質を抑制する効果が得られる。   The reason why the insulating adhesive is injected in this manner is that the bonding strength is insufficient only by bonding with electrodes such as bumps, and long-term stability and reliability are lacking. That is, the bonding property of the wafer is enhanced by sealing the bonding portion (interlayer bonding portion) of the wafer with an insulating adhesive. In addition, in this technique, since the insulating adhesive shields the electrical connection portion from the outside, an effect of suppressing contamination and deterioration of the electrical connection portion due to intrusion of gas or the like from the outside can be obtained.

特開平１１−２６１００１号公報（特許請求の範囲、図２、図３）Japanese Patent Laid-Open No. 11-261001 (Claims, FIGS. 2 and 3)

上記従来の技術には、以下の課題が残されている。
従来のように接合後に絶縁性接着剤等の絶縁体を層間接合部に注入して封止を行う場合、絶縁体注入工程の追加により、接着剤の引き込みや硬化の時間を要し、タクトの低下、製造コストの増大を生ずる。また、従来のように貼り合わせ工程後に真空吸引等により層間接合部に絶縁体を導入する方法では絶縁材の充填にむらを生じやすく、このため歩留まりの低下等が生じてしまう。さらに、接着剤が誘導電荷を持つため、信号交雑や信号遅延の問題が発生するおそれもある。また、配線にＣｕ等の金属を用いた場合、絶縁性接着剤を介して金属拡散による汚染が生じるおそれがあると共に、絶縁性接着剤からのコンタミネーションが少なからず生じるという不都合もある。 The following problems remain in the conventional technology.
In the case where sealing is performed by injecting an insulator such as an insulating adhesive into the interlayer joint after bonding as in the conventional case, the addition of the insulator injection process requires time for drawing in the adhesive and curing, Decreases and increases manufacturing costs. In addition, in the conventional method of introducing an insulator into the interlayer junction by vacuum suction or the like after the bonding process, unevenness in filling of the insulating material is likely to occur, resulting in a decrease in yield. Furthermore, since the adhesive has an induced charge, there is a risk of problems of signal hybridization and signal delay. In addition, when a metal such as Cu is used for the wiring, there is a possibility that contamination due to metal diffusion may occur through the insulating adhesive, and there is a disadvantage that contamination from the insulating adhesive is not a little.

本発明は、前述の課題に鑑みてなされたもので、貼り合わせによる多層半導体デバイスの層間配線技術において、タクトや歩留まりの低下を抑え、層間配線部の安定維持に充分な強固な接合強度を得るとともに層間配線部の劣化によるデバイスの劣化を抑制することでデバイスの長期安定性・信頼性を維持する半導体装置及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above-described problems. In the interlayer wiring technology of a multilayer semiconductor device by bonding, a decrease in tact and yield is suppressed, and a strong bonding strength sufficient for stable maintenance of the interlayer wiring portion is obtained. Another object of the present invention is to provide a semiconductor device that maintains the long-term stability and reliability of the device by suppressing the deterioration of the device due to the deterioration of the interlayer wiring portion, and a manufacturing method thereof.

本発明は、前記課題を解決するために以下の構成を採用した。すなわち、本発明の半導体装置は、第１のデバイス部を有し第１のデバイス部の電極が表面に形成された第１の基板と、第２のデバイス部を有し第２のデバイス部の電極が表面に形成されていると共に第１のデバイス部の電極と第２のデバイス部の電極とを接合させた状態で第１の基板上に積層された第２の基板と、接合状態の第１のデバイス部の電極と第２のデバイス部の電極とを包囲した状態で第１の基板と第２の基板との間に介在してこれらを接合し、内部の空間を気密状態に封止する封止接合材と、を備え、第１のデバイス部の電極及び第２のデバイス部の電極の少なくとも一方が封止接合材よりも低剛性の導電性材料で形成され、封止接合材は、導電性材料で形成されている第１のデバイス部の電極及び第２のデバイス部の電極の少なくとも一方よりも高剛性であることを特徴とする。 The present invention employs the following configuration in order to solve the above problems. That is, the semiconductor device of the present invention includes a first substrate having a first device portion and an electrode of the first device portion formed on the surface, and a second device portion having a second device portion. A second substrate stacked on the first substrate in a state where the electrode is formed on the surface and the electrode of the first device unit and the electrode of the second device unit are bonded together; The electrode of the first device part and the electrode of the second device part are surrounded and joined between the first substrate and the second substrate to seal the internal space in an airtight state. And at least one of the electrode of the first device portion and the electrode of the second device portion is formed of a conductive material having a rigidity lower than that of the sealing bonding material, and the sealing bonding material is The electrodes of the first device portion and the second device portion formed of a conductive material. Characterized in that it is a more rigid than one even without.

また、本発明の半導体装置の製造方法は、第１のデバイス部を有し第１のデバイス部の電極を表面に形成した第１の基板を作製する工程と、第２のデバイス部を有し第２のデバイス部の電極を表面に形成した第２の基板を作製する工程と、第１のデバイス部の電極と第２のデバイス部の電極とを接合させて第１の基板上に第２の基板を積層する工程と、を備え、接合時に第１のデバイス部の電極及び第２のデバイス部の電極を包囲した状態で第１の基板と第２の基板との間に介在してこれらを接合し、内部を気密状態に封止する封止接合材を、第１の基板及び第２の基板の少なくとも一方に形成しておき、第１のデバイス部の電極及び第２のデバイス部の電極の少なくとも一方が封止接合材よりも低剛性の導電性材料で形成され、封止接合材は、導電性材料で形成されている第１のデバイス部の電極及び第２のデバイス部の電極の少なくとも一方よりも高剛性であることを特徴とする。 In addition, the method for manufacturing a semiconductor device of the present invention includes a step of manufacturing a first substrate having a first device portion and an electrode of the first device portion formed on the surface, and a second device portion. A step of producing a second substrate having the electrode of the second device portion formed on the surface, and joining the electrode of the first device portion and the electrode of the second device portion to the second substrate on the first substrate And laminating the first substrate and the second device in a state of surrounding the electrodes of the first device portion and the second device portion at the time of bonding. joining, the sealing joint material for sealing the internal airtight, it can be formed on at least one of the first and second substrates, the electrode and the second device of the first device part At least one of the electrodes is formed of a conductive material having a rigidity lower than that of the sealing bonding material, and the sealing bonding material , Characterized in that at least one of which more rigid than the first device portion of the electrode and a second device portion of the electrode which is formed of a conductive material.

これらの半導体装置及びその製造方法では、電極部のみによる接合ではなく、封止接合材によって、第１の基板と第２の基板との接合がなされることにより、第１の基板と第２の基板との接合強度が高まると共に、電極部を含む内部空間の気密封止がなされることにより、外部からのガス等の侵入による内部の汚染・変質を防ぐことができる。このように、封止接合材は、デバイス部が配置された内部空間の気密を維持するガスバリアとして機能すると共に、第１の基板と第２の基板との接合を強固に保つ接合部材として機能する。
また、この半導体装置の製造方法では、第１の基板と第２の基板とを積層する際に同時に封止接合材で封止を行うため、封止工程を別個に必要とせず、タクトの低下を回避し、高い生産性を得ることができる。 In these semiconductor devices and manufacturing methods thereof, the first substrate and the second substrate are bonded by the bonding between the first substrate and the second substrate by the sealing bonding material instead of bonding by only the electrode portion. By increasing the bonding strength with the substrate and hermetically sealing the internal space including the electrode portion, it is possible to prevent internal contamination and alteration due to intrusion of gas or the like from the outside. As described above, the sealing bonding material functions as a gas barrier that maintains the airtightness of the internal space in which the device portion is disposed, and also functions as a bonding member that firmly maintains the bonding between the first substrate and the second substrate. .
Further, in this method of manufacturing a semiconductor device, when the first substrate and the second substrate are stacked, sealing is performed with a sealing bonding material at the same time, so that a separate sealing step is not required and the tact is reduced. Can be avoided and high productivity can be obtained.

本発明の半導体装置は、封止接合材で封止した内部の空間が、真空状態又は不活性ガスが充填された状態であることが好ましい。また、本発明の半導体装置の製造方法は、上記接合を真空中又は不活性ガス中で行うことが好ましい。すなわち、これらの半導体装置及びその製造方法では、封止接合材で包囲された内部空間が、真空状態又は不活性ガス充填状態で気密とされるので、当該内部空間内へ外部から侵入する反応性ガスに起因する汚染や変質を抑制することができる。   In the semiconductor device of the present invention, the internal space sealed with the sealing bonding material is preferably in a vacuum state or a state filled with an inert gas. In the method for manufacturing a semiconductor device of the present invention, it is preferable that the bonding is performed in a vacuum or in an inert gas. That is, in these semiconductor devices and manufacturing methods thereof, the internal space surrounded by the sealing bonding material is hermetically sealed in a vacuum state or filled with an inert gas, and therefore, the reactivity that enters the internal space from the outside. Contamination and alteration caused by gas can be suppressed.

また、本発明の半導体装置の製造方法は、上記封止接合材の接合を常温接合で行うことを特徴とする。すなわち、この半導体装置の製造方法では、常温接合により封止接合材の接合を行うので、熱負荷によるデバイス部へのダメージ等を防ぐことができる。   In addition, a method for manufacturing a semiconductor device according to the present invention is characterized in that the sealing bonding material is bonded at room temperature. That is, in this semiconductor device manufacturing method, since the sealing bonding material is bonded by room temperature bonding, damage to the device portion due to a thermal load can be prevented.

また、本発明の半導体装置の製造方法は、第１のデバイス部の電極及び第２のデバイス部の電極の少なくとも一方を封止接合材よりも低剛性の導電性材料でかつ突出した高さで形成し、第１の基板と第２の基板とを圧接して上記の積層を行うことを特徴とする。すなわち、この半導体装置の製造方法では、低剛性の電極を封止接合材よりも突出した高さに設定するので、荷重を加えた状態で第１の基板と第２の基板とを接合すると、封止接合材による接合と同時に、低剛性の電極が変形して圧着され、電極の接合を確実に行うことができる。   In the semiconductor device manufacturing method of the present invention, at least one of the electrode of the first device portion and the electrode of the second device portion is made of a conductive material having a rigidity lower than that of the sealing bonding material and has a protruding height. And the above-described lamination is performed by press-contacting the first substrate and the second substrate. That is, in this method of manufacturing a semiconductor device, since the low-rigidity electrode is set to a height protruding from the sealing bonding material, when the first substrate and the second substrate are bonded with a load applied, Simultaneously with the bonding with the sealing bonding material, the low-rigidity electrode is deformed and pressure-bonded, and the electrode can be reliably bonded.

本発明によれば、以下の効果を奏する。
すなわち、本発明に係る半導体装置及びその製造方法によれば、封止接合材によって、第１の基板と第２の基板との接合及びデバイス部が配置された空間の気密封止がなされることにより、第１の基板と第２の基板との接合強度が高まると共に、外部からのガス等の侵入による内部の汚染・変質を防ぐことができ、高い接合性及び良好な封止状態を得ることによりデバイスの長期安定性・信頼性を維持することができる。また、本発明の半導体装置の製造方法によれば、封止工程を別個に必要とすることなく、高い接合性及び良好な封止状態を得ることができる。したがって、安定した特性及び信頼性を有し、高い生産性で強固に封止された積層構造の半導体装置を得ることができる。 The present invention has the following effects.
That is, according to the semiconductor device and the method of manufacturing the same according to the present invention, the sealing bonding material joins the first substrate and the second substrate and hermetically seals the space where the device portion is arranged. As a result, the bonding strength between the first substrate and the second substrate can be increased, and internal contamination and alteration due to intrusion of gas or the like from the outside can be prevented, and high bondability and a good sealing state can be obtained. As a result, the long-term stability and reliability of the device can be maintained. Moreover, according to the manufacturing method of the semiconductor device of this invention, a high bondability and a favorable sealing state can be obtained, without requiring a sealing process separately. Therefore, it is possible to obtain a semiconductor device having a laminated structure which has stable characteristics and reliability and is firmly sealed with high productivity.

以下、本発明に係る半導体装置及びその製造方法の一実施形態を、図１から図４を参照しながら説明する。   Hereinafter, an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS.

本実施形態の半導体装置は、図１の（ａ）に示すように、複数のトランジスタ等からなる第１のデバイス部１が形成された第１の基板２と、複数のトランジスタ等からなる第２のデバイス部３が形成された第２の基板４とを、図１の（ｂ）に示すように、積層してなる半導体集積回路等の多層半導体デバイスＳＤである。   As shown in FIG. 1A, the semiconductor device according to the present embodiment includes a first substrate 2 on which a first device unit 1 including a plurality of transistors and the like, and a second substrate including a plurality of transistors and the like. As shown in FIG. 1B, a multilayer semiconductor device SD such as a semiconductor integrated circuit is formed by stacking the second substrate 4 on which the device section 3 is formed.

上記第１の基板２は、例えばＳｉ（シリコン）基板であって、内部に第１のデバイス部１が形成されていると共に第１のデバイス部１に接続された第１の貫通配線５が表裏に貫通して形成されている。この第１の貫通配線５の一端は、内側表面に露出しており、先端にハンダ等の導電性材料からなる第１のバンプ電極（第１のデバイス部の電極）６が形成されている。また、第１の基板２には、その外側表面に第１の貫通配線５の他端に接続された第１の表面配線７が形成されている。さらに、この第１の基板２には、その内側表面に第１のバンプ電極６の周囲を包囲した矩形枠状の第１の封止接合材８が形成されている。   The first substrate 2 is, for example, a Si (silicon) substrate, in which the first device portion 1 is formed, and the first through wiring 5 connected to the first device portion 1 is front and back. It is formed to penetrate through. One end of the first through wiring 5 is exposed on the inner surface, and a first bump electrode (electrode of the first device portion) 6 made of a conductive material such as solder is formed at the tip. Further, a first surface wiring 7 connected to the other end of the first through wiring 5 is formed on the outer surface of the first substrate 2. Further, the first substrate 2 is formed with a rectangular frame-shaped first sealing bonding material 8 surrounding the periphery of the first bump electrode 6 on the inner surface thereof.

また、上記第２の基板４は、第１の基板２と同様に、例えばＳｉ基板であって、内部に第２のデバイス部３が形成されていると共に第２のデバイス部３に接続された第２の貫通配線９が表裏に貫通して形成されている。この第２の貫通配線９の一端は、内側表面に露出しており、先端にハンダ等の導電性材料からなる第２のバンプ電極（第２のデバイス部の電極）１０が形成されている。また、第２の基板４には、その外側表面に第２の貫通配線９の他端に接続された第２の表面配線１１が形成されている。さらに、この第２の基板４には、その内側表面に第２のバンプ電極１０の周囲を包囲した矩形枠状の第２の封止接合材１２が上記第１の封止接合材８の位置に対応して形成されている。
上記第１及び第２の封止接合材８、１２は、第１及び第２のバンプ電極６、１０よりも剛性の高い材料、例えばＳｉで形成されている。 Further, the second substrate 4 is, for example, a Si substrate, like the first substrate 2, and the second device unit 3 is formed therein and connected to the second device unit 3. The 2nd penetration wiring 9 is penetrated and formed in the front and back. One end of the second through wiring 9 is exposed on the inner surface, and a second bump electrode (electrode of the second device portion) 10 made of a conductive material such as solder is formed at the tip. The second substrate 4 has a second surface wiring 11 connected to the other end of the second through wiring 9 on the outer surface thereof. Further, the second sealing member 12 having a rectangular frame shape surrounding the periphery of the second bump electrode 10 on the inner surface of the second substrate 4 has a position of the first sealing member 8. It is formed corresponding to.
The first and second sealing bonding materials 8 and 12 are made of a material having rigidity higher than that of the first and second bump electrodes 6 and 10, for example, Si.

上記第２の基板４は、第１のバンプ電極６に第２のバンプ電極１０を接合させた状態で第１の基板２上に接合されている。また、互いに対向配置された第１の封止接合材８と第２の封止接合材１２とが接合されて、第１の基板２と第２の基板４とが積層状態とされている。すなわち、第１の封止接合材８及び第２の封止接合材１２は、第１の基板２と第２の基板４との間に介在してこれらを接合し、接合状態の第１のバンプ電極６と第２のバンプ電極１０とを包囲した状態で内部の空間を気密状態に封止している。第１の封止接合材８及び第２の封止接合材１２で封止した内部の空間は、真空状態又はＡｒ（アルゴン）等の不活性ガスが充填された状態とされている。   The second substrate 4 is bonded onto the first substrate 2 with the second bump electrode 10 bonded to the first bump electrode 6. In addition, the first sealing bonding material 8 and the second sealing bonding material 12 that are arranged to face each other are bonded to each other so that the first substrate 2 and the second substrate 4 are laminated. That is, the first sealing bonding material 8 and the second sealing bonding material 12 are interposed between the first substrate 2 and the second substrate 4 to bond them, and the first bonded bonding material 1 The inner space is sealed in an airtight state while surrounding the bump electrode 6 and the second bump electrode 10. The internal space sealed with the first sealing bonding material 8 and the second sealing bonding material 12 is in a vacuum state or a state filled with an inert gas such as Ar (argon).

次に、本実施形態の多層半導体デバイスＳＤの製造方法について、図２から図４を参照して説明する。   Next, a method for manufacturing the multilayer semiconductor device SD of the present embodiment will be described with reference to FIGS.

まず、図２の（ａ）に示すように、トランジスタ等の第１のデバイス部１が形成された第１のＳｉウェーハ１３の表面に、第１のデバイス部１の層間接続端子としてハンダ等で第１のバンプ電極６を形成する。同様に、トランジスタ等の第２のデバイス部３が形成された第２のＳｉウェーハ１４の表面に、第２のデバイス部３の層間接続端子としてハンダ等で第２のバンプ電極１０を形成する。これらの第１のバンプ電極６及び第２のバンプ電極１０は、それぞれ予め第１のＳｉウェーハ１３及び第２のＳｉウェーハ１４に形成された第１の貫通配線５（図示しない）の一端及び第２の貫通配線９（図示しない）の一端に形成される。   First, as shown in FIG. 2A, the surface of the first Si wafer 13 on which the first device portion 1 such as a transistor is formed is soldered as an interlayer connection terminal of the first device portion 1. A first bump electrode 6 is formed. Similarly, the second bump electrode 10 is formed by solder or the like as an interlayer connection terminal of the second device unit 3 on the surface of the second Si wafer 14 on which the second device unit 3 such as a transistor is formed. The first bump electrode 6 and the second bump electrode 10 are respectively connected to one end of the first through wiring 5 (not shown) and the first bump formed in the first Si wafer 13 and the second Si wafer 14 in advance. Two through wirings 9 (not shown) are formed at one end.

これらの第１のバンプ電極６及び第２のバンプ電極１０は、次に形成する第１の封止接合材８及び第２の封止接合材１２の高さよりも若干高く形成しておく。
なお、図示はしないが第１のＳｉウェーハ１３及び第２のＳｉウェーハ１４には、第１のバンプ電極６及び第２のバンプ電極１０と反対の表面に、それぞれ第１の表面配線７及び第２の表面配線１１を予め形成しておく。 The first bump electrode 6 and the second bump electrode 10 are formed slightly higher than the height of the first sealing bonding material 8 and the second sealing bonding material 12 to be formed next.
Although not shown, the first Si wafer 13 and the second Si wafer 14 have the first surface wiring 7 and the second Si wafer 14 on the surface opposite to the first bump electrode 6 and the second bump electrode 10, respectively. Two surface wirings 11 are formed in advance.

次に、図２の（ｂ）に示すように、第１のＳｉウェーハ１３及び第２のＳｉウェーハ１４の表面上にＳｉ膜１４をＣＶＤ等により所定厚さで成膜する。さらに、Ｓｉ膜１４の表面をＣＭＰ（Chemical Mechanical Polishing:化学的機械的研磨）により平坦化した後に、図２（ｃ）に示すように、マスクＭにより第１のバンプ電極６及び第２のバンプ電極１０を包囲する矩形枠状のパターンを施す。次に、図３の（ａ）に示すように、マスキングされていないＳｉ膜１４の不要部分をエッチングにより除去し、矩形枠状に第１の封止接合材８及び第２の封止接合材１２をそれぞれ第１のＳｉウェーハ１３及び第２のＳｉウェーハ１４の表面上に形成する。   Next, as shown in FIG. 2B, a Si film 14 is formed with a predetermined thickness on the surfaces of the first Si wafer 13 and the second Si wafer 14 by CVD or the like. Further, after planarizing the surface of the Si film 14 by CMP (Chemical Mechanical Polishing), as shown in FIG. 2C, the first bump electrode 6 and the second bump are masked by the mask M. A rectangular frame-shaped pattern surrounding the electrode 10 is applied. Next, as shown in FIG. 3A, unnecessary portions of the unmasked Si film 14 are removed by etching, and the first sealing bonding material 8 and the second sealing bonding material are formed into a rectangular frame shape. 12 are formed on the surfaces of the first Si wafer 13 and the second Si wafer 14, respectively.

次に、第１のＳｉウェーハ１３と第２のＳｉウェーハ１４とを対向させて位置決めすると共に、図３の（ｂ）に示すように、第１の封止接合材８と第２の封止接合材１２とを真空中又はＡｒ等の不活性ガス雰囲気中で互いに圧接して常温接合により接合を行う。この際、第１の封止接合材８と第２の封止接合材１２との接合と同時に、第１のバンプ電極６と第２のバンプ電極１０との接合が行われる。また、接合された第１の封止接合材８と第２の封止接合材１２とにより、真空状態又は不活性ガスが充填された状態で内部の空間が気密状態に封止される。なお、図３の（ｂ）では、わかり易くするために第２のＳｉウェーハ１４を図示していない。このように、第１の封止接合材８及び第２の封止接合材１２は、内部空間の気密を維持するガスバリアとして機能すると共に、第１のＳｉウェーハ１３と第２のＳｉウェーハ１４との接合を強固に保つ接合部材として機能する。   Next, the first Si wafer 13 and the second Si wafer 14 are positioned to face each other, and as shown in FIG. 3B, the first sealing bonding material 8 and the second sealing are used. The bonding material 12 is pressed against each other in vacuum or in an inert gas atmosphere such as Ar, and bonded by room temperature bonding. At this time, the first bump electrode 6 and the second bump electrode 10 are bonded simultaneously with the bonding of the first sealing bonding material 8 and the second sealing bonding material 12. Further, the inner space is sealed in an airtight state in a vacuum state or a state filled with an inert gas by the first sealing bonding material 8 and the second sealing bonding material 12 which are bonded. In FIG. 3B, the second Si wafer 14 is not shown for easy understanding. Thus, the first sealing bonding material 8 and the second sealing bonding material 12 function as a gas barrier that maintains the airtightness of the internal space, and the first Si wafer 13 and the second Si wafer 14 It functions as a joining member that keeps the joining firmly.

なお、常温接合を行う場合は、接合面となる第１の封止接合材８の端面及び第２の封止接合材１２の端面をそれぞれ活性化処理する。
すなわち、通常、接合面の表面には、大気中の酸素等との反応による酸化膜やフォトリソグラフィ工程中のエッチング材料の残渣やその他の不純物が存在する。そこで、高真空中において、中性原子ビーム、イオンビーム等を接合面表面に照射し、これらの不純物を接合面表面から排除して、接合面表面を清浄にする。さらに、同時に、接合面表面にダングリングボンドが存在する状態、つまり、接合面表面が活性化された状態にする。 In addition, when performing normal temperature bonding, the end surface of the 1st sealing bonding material 8 used as a bonding surface and the end surface of the 2nd sealing bonding material 12 are each activated.
In other words, the surface of the bonding surface usually contains an oxide film due to a reaction with oxygen in the atmosphere, a residue of an etching material during the photolithography process, and other impurities. In view of this, the surface of the bonding surface is irradiated with a neutral atom beam, an ion beam or the like in a high vacuum to remove these impurities from the surface of the bonding surface, thereby cleaning the surface of the bonding surface. Furthermore, at the same time, a state in which dangling bonds are present on the surface of the bonding surface, that is, a state in which the surface of the bonding surface is activated.

この活性化された状態で、第１の封止接合材８の端面と第２の封止接合材１２の端面とを互いに圧接して常温接合させる。この常温接合は、接合面同士が互いのダングリングボンド同士で結合を行うことになり、強い結合強度を得ることができると共に、室温において接合可能であるため、熱による歪みがなく、高精度かつ高効率な生産性の良好な接合法である。   In this activated state, the end surface of the first sealing bonding material 8 and the end surface of the second sealing bonding material 12 are pressed against each other and bonded at room temperature. In this room temperature bonding, the bonding surfaces are bonded with each other's dangling bonds, so that strong bonding strength can be obtained and bonding is possible at room temperature, so there is no distortion due to heat, high accuracy and This is a highly efficient joining method with good productivity.

また、第１のバンプ電極６と第２のバンプ電極１０とは、第１の封止接合材８及び第２の封止接合材１２よりも若干高く形成されていると共に、第１の封止接合材８及び第２の封止接合材１２よりも低剛性の導電性材料、すなわち第１の封止接合材８及び第２の封止接合材１２に比べて柔らかく展性に富む導電性材料で形成されている。このため、図４の（ａ）に示すように、第１の封止接合材８と第２の封止接合材１２との接合時に、第１のバンプ電極６と第２のバンプ電極１０とが荷重で変形して圧着され、確実な接合状態が得られる。   Further, the first bump electrode 6 and the second bump electrode 10 are formed slightly higher than the first sealing bonding material 8 and the second sealing bonding material 12, and the first sealing electrode Conductive material having lower rigidity than the bonding material 8 and the second sealing bonding material 12, that is, a conductive material that is softer and more malleable than the first sealing bonding material 8 and the second sealing bonding material 12. It is formed with. Therefore, as shown in FIG. 4A, when the first sealing bonding material 8 and the second sealing bonding material 12 are bonded, the first bump electrode 6 and the second bump electrode 10 Is deformed by the load and is crimped, and a reliable joining state is obtained.

このようにウェーハ単位で相互に接合及び封止を行った後、図３の（ｂ）に示すダイシングラインＤに沿ってダイシングすることにより、接合されて積層状態の第１のＳｉウェーハ１３及び第２のＳｉウェーハ１４を、図３の（ｃ）に示すように、第１の基板２と第２の基板４とが接合された多層半導体デバイスＳＤに分離切断することで、単体の多層半導体デバイスＳＤを得ることができる。   After bonding and sealing each other in units of wafers in this way, the first Si wafer 13 and the stacked first Si wafer 13 bonded and laminated by dicing along a dicing line D shown in FIG. As shown in FIG. 3C, the two Si wafers 14 are separated and cut into a multi-layer semiconductor device SD in which the first substrate 2 and the second substrate 4 are joined, so that a single multi-layer semiconductor device is obtained. SD can be obtained.

本実施形態では、接合された第１の封止接合材８及び第２の封止接合材１２によって、第１の基板２と第２の基板４との接合及び内部空間の気密封止がなされることにより、第１の基板２と第２の基板４との接合強度が高まると共に、外部からの腐食性ガス等の侵入による内部の汚染・変質を防ぐことができる。
また、第１の基板２となる第１のＳｉウェーハ１３と第２の基板４となる第２のＳｉウェーハ１４とを積層する際に、同時に第１の封止接合材８及び第２の封止接合材１２で封止を行うため、封止工程を別個に必要とせず、タクトの低下を回避し、高い生産性を得ることができる。そして、荷重を伴う接合の場合、第１の封止接合材８及び第２の封止接合材１２は、荷重を支えて内部構造を保護する支持材としての機能も担っている。 In the present embodiment, the first substrate 2 and the second substrate 4 are bonded and the internal space is hermetically sealed by the bonded first sealing bonding material 8 and the second sealing bonding material 12. As a result, the bonding strength between the first substrate 2 and the second substrate 4 is increased, and internal contamination / degeneration due to the invasion of corrosive gas or the like from the outside can be prevented.
Further, when the first Si wafer 13 to be the first substrate 2 and the second Si wafer 14 to be the second substrate 4 are laminated, the first sealing bonding material 8 and the second sealing are simultaneously formed. Since sealing is performed with the stop bonding material 12, a separate sealing step is not required, and a reduction in tact can be avoided and high productivity can be obtained. In the case of bonding with a load, the first sealing bonding material 8 and the second sealing bonding material 12 also have a function as a support material that supports the load and protects the internal structure.

さらに、第１の封止接合材８及び第２の封止接合材１２で包囲された内部空間が、真空状態又は不活性ガス充填状態とされるので、当該内部空間内の雰囲気ガスに起因する汚染や変質を抑制することができる。
また、常温接合により第１の封止接合材８と第２の封止接合材１２との接合を行うので、熱負荷による第１のデバイス部１及び第２のデバイス部３へのダメージ等を防ぐことができる。 Furthermore, since the internal space surrounded by the first sealing bonding material 8 and the second sealing bonding material 12 is in a vacuum state or filled with an inert gas, it is caused by the atmospheric gas in the internal space. Contamination and alteration can be suppressed.
In addition, since the first sealing bonding material 8 and the second sealing bonding material 12 are bonded by room-temperature bonding, damage to the first device unit 1 and the second device unit 3 due to a thermal load is caused. Can be prevented.

なお、本発明の技術範囲は上記各実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。   The technical scope of the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

例えば、本実施形態では、第１のバンプ電極６と第２のバンプ電極１０とを圧着して接合させているが、図４の（ｂ）に示すように、第１の貫通配線５及び第２の貫通配線９の一端にこれらのバンプ電極を形成せず、第１の貫通配線５及び第２の貫通配線９の一端を第１のＳｉウェーハ１３及び第２のＳｉウェーハ１４の内側表面から突出させ、互いに突き合わせて常温接合により接合させても構わない。この場合も、第１のバンプ電極６及び第２のバンプ電極１０と同様に、第１の封止接合材８及び第２の封止接合材１２よりも若干高く第１の貫通配線５及び第２の貫通配線９の一端を突出させると共に、第１の封止接合材８及び第２の封止接合材１２よりも低剛性の導電性材料で形成する。これにより、圧接時に第１の貫通配線５と第２の貫通配線９と一端が互いに変形して圧着し、確実な電極接合を得ることができる。
また、上記実施形態では、第１の封止接合材８及び第２の封止接合材１２とを第１のＳｉウェーハ１３及び第２のＳｉウェーハ１４に接合して設けているが、他のバリエーションとして、デバイス形成の前に、所定領域を予めエッチング等により壁部に囲まれた凹部としておき、該凹部内にデバイスを形成した後に、壁部を用いて封止する方法で構成しても構わない。この場合、壁部が、ウェーハ（基板）に一体に形成された封止接合材として機能するので、別個に封止接合材を作製しておく必要が無く、部材点数の低減等により、より低コスト化を図ることが可能になる。 For example, in the present embodiment, the first bump electrode 6 and the second bump electrode 10 are bonded by pressure bonding, but as shown in FIG. These bump electrodes are not formed at one end of the two through wirings 9, and the one end of the first through wiring 5 and the second through wiring 9 is connected to the inner surface of the first Si wafer 13 and the second Si wafer 14. You may make it protrude, but it may contact | abut each other and it may join by normal temperature joining. Also in this case, similarly to the first bump electrode 6 and the second bump electrode 10, the first through-wiring 5 and the second through-hole 5 are slightly higher than the first sealing bonding material 8 and the second sealing bonding material 12. One end of each of the two through-wirings 9 is protruded, and is formed of a conductive material having lower rigidity than the first sealing bonding material 8 and the second sealing bonding material 12. Thereby, at the time of press-contact, the 1st penetration wiring 5, the 2nd penetration wiring 9, and one end mutually deform and press-fit, and reliable electrode joining can be obtained.
Moreover, in the said embodiment, although the 1st sealing joining material 8 and the 2nd sealing joining material 12 are joined and provided in the 1st Si wafer 13 and the 2nd Si wafer 14, As a variation, it is possible to configure a method in which a predetermined region is previously formed as a recess surrounded by a wall by etching or the like before forming a device, and a device is formed in the recess and then sealed using the wall. I do not care. In this case, since the wall portion functions as a sealing bonding material formed integrally with the wafer (substrate), there is no need to prepare a sealing bonding material separately, and the lower the number of members. Cost can be reduced.

また、第１の封止接合材８及び第２の封止接合材１２をＳｉで形成したが、他の材料で形成しても構わない。例えば、ＳｉＯ2等の絶縁性材料やＡｌ等の金属材料でも良い。なお、上述した理由により、第１のバンプ電極６及び第２のバンプ電極１０よりも高い剛性を有する材料が好ましい。
また、第１の基板２に形成した第１の封止接合材８と第２の基板４に形成した第２の封止接合材１２とを突き合わせて接合を行っているが、第１の基板２又は第２の基板４の一方に、封止に必要な高さに設定した封止接合材を一つだけ形成しておき、これを他方の基板の表面に接合しても構わない。
さらに、本実施形態の製造方法では、ウェーハ単位で接合してダイシングにより単体の多層半導体デバイスＳＤを得ているが、単体の第１の基板２と第２の基板４とを接合して単体の多層半導体デバイスＳＤを製造しても構わない。 Moreover, although the 1st sealing bonding material 8 and the 2nd sealing bonding material 12 were formed with Si, you may form with another material. For example, an insulating material such as SiO 2 or a metal material such as Al may be used. For the reasons described above, a material having higher rigidity than the first bump electrode 6 and the second bump electrode 10 is preferable.
Further, the first sealing bonding material 8 formed on the first substrate 2 and the second sealing bonding material 12 formed on the second substrate 4 are abutted and bonded to each other. Only one sealing bonding material set to a height required for sealing may be formed on one of the two or second substrates 4 and bonded to the surface of the other substrate.
Furthermore, in the manufacturing method of the present embodiment, a single multilayer semiconductor device SD is obtained by dicing and bonding in units of wafers, but the single first substrate 2 and the second substrate 4 are bonded to each other. A multilayer semiconductor device SD may be manufactured.

また、隣接する第１の封止接合材８と第２の封止接合材１２との間でダイシングしたが、図５に示すように、ウェーハ状態では隣接する多層半導体デバイスＳＤで一つの第１の封止接合材８及び第２の封止接合材１２を共用し、ダイシングでこの第１の封止接合材８及び第２の封止接合材１２からなる封止接合材を２つに切り離して分割しても構わない。この場合、ダイシングにより個々の多層半導体デバイスＳＤに切り離されて分割された第１の封止接合材８及び第２の封止接合材１２は、内部空間の気密状態を確保・維持するのに十分な幅になるように設定される。   Further, although dicing is performed between the adjacent first sealing bonding material 8 and the second sealing bonding material 12, as shown in FIG. 5, one first multi-layer semiconductor device SD is adjacent to each other in the wafer state. The sealing bonding material 8 and the second sealing bonding material 12 are shared, and the sealing bonding material composed of the first sealing bonding material 8 and the second sealing bonding material 12 is separated into two by dicing. Can be divided. In this case, the first sealing bonding material 8 and the second sealing bonding material 12 separated into individual multilayer semiconductor devices SD by dicing are sufficient to ensure and maintain the airtight state of the internal space. It is set to be a wide width.

また、本実施形態では、第１の基板２及び第２の基板４とを接合して積層しているが、２つの基板に限らず、３つ以上の基板を同様にして接合し積層した多層半導体デバイスに適用しても構わない。この場合、互いに対向して接合し合う基板同士は、それぞれ第１の基板２及び第２の基板４と同様に、第１の封止接合材８及び第２の封止接合材１２に対応した同様の封止接合材が形成されることは言うまでもない。   In the present embodiment, the first substrate 2 and the second substrate 4 are bonded and stacked. However, the present invention is not limited to two substrates, but a multilayer in which three or more substrates are bonded and stacked in the same manner. You may apply to a semiconductor device. In this case, the substrates facing each other and bonded correspond to the first sealing bonding material 8 and the second sealing bonding material 12, respectively, similarly to the first substrate 2 and the second substrate 4, respectively. Needless to say, a similar sealing bonding material is formed.

本発明に係る一実施形態の半導体装置の製造方法を示す接合前後の断面図である。It is sectional drawing before and behind joining which shows the manufacturing method of the semiconductor device of one Embodiment which concerns on this invention. 本実施形態の半導体装置の製造工程において、バンプ電極形成工程からマスキング工程までを工程順に示す要部の斜視図である。In the manufacturing process of the semiconductor device of this embodiment, it is a perspective view of the principal part which shows from a bump electrode formation process to a masking process in order of a process. 本実施形態の半導体装置の製造工程において、封止接合材形成工程からダイシング後までを工程順に示す要部の斜視図である。In the manufacturing process of the semiconductor device of this embodiment, it is a perspective view of the principal part which shows from a sealing bonding material formation process to after dicing in order of a process. 本実施形態の半導体装置の製造工程において、バンプ電極の接合状態及び貫通配線の接合状態を示す要部の断面図である。In the manufacturing process of the semiconductor device of this embodiment, it is sectional drawing of the principal part which shows the joining state of a bump electrode, and the joining state of a penetration wiring. 本実施形態の半導体装置の製造工程において、ダイシング工程の他の例を示す断面図である。In the manufacturing process of the semiconductor device of this embodiment, it is sectional drawing which shows the other example of a dicing process.

符号の説明Explanation of symbols

１…第１のデバイス部、２…第１の基板、３…第２のデバイス部、４…第２の基板、６…第１のバンプ電極（第１のデバイス部の電極）、８…第１の封止接合材、１０…第２のバンプ電極（第２のデバイス部の電極）、１２…第２の封止接合材、１３…第１のＳｉウェーハ、１４…第２のＳｉウェーハ、ＳＤ…多層半導体デバイス   DESCRIPTION OF SYMBOLS 1 ... 1st device part, 2 ... 1st board | substrate, 3 ... 2nd device part, 4 ... 2nd board | substrate, 6 ... 1st bump electrode (electrode of 1st device part), 8 ... 1st DESCRIPTION OF SYMBOLS 1 Sealing bonding material, 10 ... 2nd bump electrode (electrode of 2nd device part), 12 ... 2nd sealing bonding material, 13 ... 1st Si wafer, 14 ... 2nd Si wafer, SD ... Multilayer semiconductor device

Claims (8)

第１のデバイス部を有し前記第１のデバイス部の電極が表面に形成された第１の基板と、
第２のデバイス部を有し前記第２のデバイス部の電極が表面に形成されていると共に前記第１のデバイス部の電極と前記第２のデバイス部の電極とを接合させた状態で前記第１の基板上に積層された第２の基板と、
接合状態の前記第１のデバイス部の電極と前記第２のデバイス部の電極とを包囲した状態で前記第１の基板と前記第２の基板との間に介在してこれらを接合し、内部の空間を気密状態に封止する封止接合材と、を備え、
前記第１のデバイス部の電極及び前記第２のデバイス部の電極の少なくとも一方が前記封止接合材よりも低剛性の導電性材料で形成され、
前記封止接合材は、前記導電性材料で形成されている前記第１のデバイス部の電極及び前記第２のデバイス部の電極の少なくとも一方よりも高剛性であることを特徴とする半導体装置。 A first substrate having a first device portion on which an electrode of the first device portion is formed;
The second device portion has the electrode of the second device portion formed on the surface, and the electrode of the first device portion and the electrode of the second device portion are joined together. A second substrate stacked on one substrate;
In a state of surrounding the electrode of the first device portion and the electrode of the second device portion in a bonded state, the electrodes are interposed between the first substrate and the second substrate, and are joined together. A sealing bonding material that seals the space in an airtight state ,
At least one of the electrode of the first device portion and the electrode of the second device portion is formed of a conductive material having a rigidity lower than that of the sealing bonding material,
The semiconductor device, wherein the sealing bonding material is higher in rigidity than at least one of the electrode of the first device portion and the electrode of the second device portion formed of the conductive material . 前記封止接合材で封止した内部の空間が、真空状態又は不活性ガスが充填された状態であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the internal space sealed with the sealing bonding material is in a vacuum state or a state filled with an inert gas. 前記封止接合材は、前記積層の方向における端面で前記接合がなされることを特徴とする請求項１又は２に記載の半導体装置。The semiconductor device according to claim 1, wherein the sealing bonding material is bonded at an end surface in the stacking direction. 第１のデバイス部を有し前記第１のデバイス部の電極を表面に形成した第１の基板を作製する工程と、
第２のデバイス部を有し前記第２のデバイス部の電極を表面に形成した第２の基板を作製する工程と、
前記第１のデバイス部の電極と前記第２のデバイス部の電極とを接合させて前記第１の基板上に前記第２の基板を積層する工程と、を備え、
前記接合時に前記第１のデバイス部の電極及び前記第２のデバイス部の電極を包囲した状態で前記第１の基板と前記第２の基板との間に介在してこれらを接合し、内部を気密状態に封止する封止接合材を、前記第１の基板及び前記第２の基板の少なくとも一方に形成しておき、
前記第１のデバイス部の電極及び前記第２のデバイス部の電極の少なくとも一方が前記封止接合材よりも低剛性の導電性材料で形成され、
前記封止接合材は、導電性材料で形成されている前記第１のデバイス部の電極及び前記第２のデバイス部の電極の少なくとも一方よりも高剛性であることを特徴とする半導体装置の製造方法。 Producing a first substrate having a first device part and having an electrode of the first device part formed on the surface;
Producing a second substrate having a second device portion and having the electrode of the second device portion formed on the surface;
Bonding the electrode of the first device portion and the electrode of the second device portion to laminate the second substrate on the first substrate,
At the time of bonding, the electrodes of the first device portion and the electrodes of the second device portion are surrounded so as to be interposed between the first substrate and the second substrate, and the inside is bonded. A sealing bonding material for sealing in an airtight state is formed on at least one of the first substrate and the second substrate ,
At least one of the electrode of the first device portion and the electrode of the second device portion is formed of a conductive material having a rigidity lower than that of the sealing bonding material,
The semiconductor device manufacturing method, wherein the sealing bonding material is higher in rigidity than at least one of the electrode of the first device portion and the electrode of the second device portion formed of a conductive material. Method. 前記第１のデバイス部の電極及び前記第２のデバイス部の電極の少なくとも一方を前記封止接合材よりも突出した高さで形成し、Forming at least one of the electrode of the first device portion and the electrode of the second device portion at a height protruding from the sealing bonding material;
前記第１の基板と前記第２の基板とを圧接して前記積層を行うことを特徴とする請求項４に記載の半導体装置の製造方法。The method for manufacturing a semiconductor device according to claim 4, wherein the stacking is performed by pressing the first substrate and the second substrate. 前記封止接合材の接合を、真空中又は不活性ガス中で行うことを特徴とする請求項４又は５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 4, wherein the sealing bonding material is bonded in a vacuum or in an inert gas. 前記封止接合材の接合を、常温接合で行うことを特徴とする請求項４〜６のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4, wherein the sealing bonding material is bonded by room-temperature bonding. 前記封止接合材の接合を、前記積層の方向における端面で行うことを特徴とする請求項４〜７のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4, wherein the sealing bonding material is bonded to an end face in the stacking direction .
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