JP2004146816A - Solid image pickup device and equipment using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small image pickup device having high a performance and an application product of the device by preventing influence of the noise superimposed on a timing-pulse supply line on the output of an image pickup chip. <P>SOLUTION: The image pickup device comprises two chips, an image pickup chip 101 including a sensor part 102 and an image processing chip 106 including an image processing circuit 110, wherein transistors in all the circuits of the image pickup chip 101 are composed of either one of nMOS or pMOS, and the image pickup chip 101 is stacked on the image processing chip 106. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a small-sized imaging device used in a mobile phone or the like, which is a solid-state imaging device in which three elements of ultra-small, low-cost, and high-performance are compatible at a high level. Equipment.

In recent years, small-sized imaging devices that can be mounted on small devices such as mobile phones have been developed. The conditions required for this type of imaging device are firstly ultra-small size and secondly low cost, and by using a general CMOS process for a logic LSI, connectivity to peripheral circuits can be improved. CMOS sensors, which can facilitate cost reduction and achieve cost reduction, have become mainstream. Further, since the CMOS sensor can be integrated into one chip with the logic unit, it can be integrated into one chip with the image processing unit, thereby realizing ultra-small size. FIG. 6 shows a configuration of a conventional one-chip CMOS sensor. The conventional one-chip CMOS sensor shown in FIG. 6 includes a sensor unit 507 for converting light into an electric signal, a vertical scanning circuit 506 for driving the sensor unit, a horizontal scanning circuit 508, a timing generation circuit (TG) 503, and a signal from the sensor unit. It comprises a gain control amplifier (GCA) 504 for amplifying a signal output, an AD conversion circuit (ADC) 505 for converting the output signal into a digital signal, and an image processing circuit 502.

However, in the future, not only ultra-small size and low cost, but also improvement in performance such as sensitivity has been required. In a small device such as a mobile phone, it is difficult to mount a lighting device such as a strobe, so that high sensitivity is particularly required. In the future, mobile phones may be used in place of digital still cameras, and higher performance has become an increasingly important development theme.

と Considering higher performance, the following problems occur in the conventional configuration. The required electrical performance is different between the logic circuit and the sensor unit, which is an analog circuit, but it is difficult to satisfy both performances because the integrated circuit is manufactured by the same process when integrated into one chip. That is, if a fine process is used, the performance of the sensor unit is deteriorated. If a non-fine process is used to secure the performance of the sensor unit, the logic unit becomes large, and the merit of one chip is lost. In order to avoid this, there has been proposed a method of adopting a two-chip configuration of an imaging chip including a sensor unit and an image processing chip including an image processing unit.

As a prior art related to the present invention, there is a method of stacking an imaging chip on an image processing chip to reduce a mounting area and realize miniaturization (for example, see Patent Document 1).
JP-A-5-268535

FIG. 7 shows a conventional imaging device composed of two chips, an imaging chip and an image processing chip. The conventional imaging apparatus shown in FIG. 7 includes a vertical scanning circuit 604 and a horizontal scanning circuit 605 for driving the sensor unit 603 of the imaging chip 601 to operate the imaging chip 601 independently of the type of the image processing chip 608. A timing pulse generation circuit 602 for generating pulses required for these scanning circuits, a gain control amplifier 606 for amplifying a signal output from the sensor unit 603, and an AD conversion circuit 607 for converting the output signal into a digital signal. It is mounted on the 601 side.

In the case of this configuration, since there is still a circuit, such as the timing pulse generating circuit 602, which is originally good at CMOS logic on the imaging chip side, there is a problem that the area of the sensor unit 603 becomes large when the performance of the sensor unit 603 is to be improved. .

This problem can be solved by mounting the timing pulse generation circuit 602, the gain control amplifier 606, and the analog-to-digital conversion circuit 607 on the image processing chip 608 side. In this case, the timing pulse from the image processing chip 608 to the imaging chip 601 is solved. The number of supply lines increases, noise is superimposed on the supply lines, and the noise is superimposed on the output of the imaging chip 601, thereby deteriorating the performance of the imaging chip.

雑 音 It has been found that this noise is mainly caused by fluctuations in current supplied to a scanning circuit for driving a pixel portion. The current fluctuation is caused by a so-called through current when the CMOS circuit switches when the scanning circuit is made of CMOS logic. Generally, a CMOS circuit is characterized by low current consumption, but it is well known that a very large current (through current) flows at the moment of switching. This is because both the nMOS and pMOS transistors are turned on for a moment of the switch, and the power supply and the ground are short-circuited. When the wiring for controlling the switch passes outside the chip, noise is superimposed on the wiring itself, or the pulse passing through the wiring is blunted, so that the power supply noise caused by the through current increases.

The present invention has been made in view of the above problems, and by preventing noise superimposed on the timing pulse supply line from affecting the output of the imaging chip, a small and high-performance imaging device and The purpose is to provide the applied product at low cost.

In order to achieve the above object, a solid-state imaging device according to the present invention includes an imaging semiconductor chip in which all transistors are formed of transistors of the same conductor, and an image processing semiconductor chip in which CMOS transistors are formed. And characterized in that:

According to the solid-state imaging device of the present invention, since all transistors of the imaging semiconductor chip are formed of transistors of the same conductor, a through current unique to a CMOS circuit is eliminated, and a timing pulse supply line is arranged outside the chip. Even in this case, the shaking noise superimposed on the power supply does not increase. Thus, the timing pulse generation circuit and the like can be provided not on the imaging semiconductor chip but on the image processing semiconductor chip which can use a finer manufacturing process. As a result, a compact and high-performance imaging device can be provided at low cost.

固体 In the solid-state imaging device according to the present invention, all the transistors of the imaging semiconductor chip are configured by transistors of the same conductor. It is preferable that the solid-state imaging device further has a configuration in which the imaging semiconductor chip is stacked on the image processing semiconductor chip. As a result, the length of the wiring connecting the imaging semiconductor chip and the image processing semiconductor chip can be reduced, the superimposition of noise on the timing pulse supply line can be reduced, and higher performance can be realized. By stacking these chips, the length of the wiring can be reduced, and noise superimposed on the video signal output from the imaging semiconductor chip can be reduced. When all the transistors of the imaging semiconductor chip are formed of the same conductor, it is difficult to form an amplifier having a high amplification factor. Therefore, the effect of adopting a configuration in which chips are stacked in the present solid-state imaging device is even more than the effect of employing a configuration in which a conventional imaging semiconductor chip formed of CMOS is stacked on an image processing semiconductor chip. It is big. Further, the mounting area can be made equal to or less than that of the case of a one-chip configuration, and ultra-miniaturization can be realized. As a result, an ultra-small, low-cost, high-performance imaging device can be realized, and it is possible to contribute to ultra-miniaturization, low cost, and high performance of various application products having an imaging function.

In the present solid-state imaging device, it is preferable that all the transistors of the imaging semiconductor chip are formed of either an n-channel MOS transistor or a p-channel MOS transistor. In particular, when all the transistors are constituted by n-channel MOS transistors, there is an advantage that the speed can be easily increased.

The solid-state imaging device may be configured such that the imaging semiconductor chip and the image processing semiconductor chip are electrically connected by a bonding wire, or a through electrode is formed in the imaging semiconductor chip, and the through electrode is formed on the imaging semiconductor chip. The imaging semiconductor chip and the image processing semiconductor chip may be electrically connected via the connected wiring. According to the former mode, a general method called wire bonding can be used, which is advantageous in terms of cost and reliability. On the other hand, according to the latter aspect, there is an advantage that further miniaturization can be achieved. It is more preferable that the through electrode is a Si through electrode.

In the solid-state imaging device, it is preferable that the image processing semiconductor chip includes a timing pulse generation circuit that supplies a timing pulse to the imaging semiconductor chip, a gain control amplifier, and an analog-to-digital conversion circuit. This is because the size can be further reduced.

In the solid-state imaging device, it is preferable that the timing pulse output terminal of the image processing semiconductor chip is arranged near the timing pulse input terminal of the imaging semiconductor chip. This is because by reducing the wiring length of the timing pulse supply line as much as possible, it is possible to further reduce noise and contribute to higher performance of the imaging device.

In the solid-state imaging device, it is preferable that the video signal input terminal of the image processing semiconductor chip is disposed near the video signal output terminal of the imaging semiconductor chip. This is because by reducing the wiring length of the video signal line as much as possible, noise superimposed on the video signal can be reduced, which can contribute to an improvement in the performance of the imaging device. As described above, when all the transistors of the imaging semiconductor chip are formed of the same conductor, it is difficult to configure an amplifier having a high amplification factor, and the video signal output from the imaging semiconductor chip has a very small level. Becomes more susceptible to noise. Therefore, the effect of reducing the wiring length of the video signal is particularly great in the present solid-state imaging device.

In addition, the solid-state imaging device according to the present invention is applied to a device including an image processing unit that processes a still image or a moving image captured by the solid-state imaging device, so that a small and high-performance A type information terminal, a digital still camera, or the like can be realized at low cost.

Hereinafter, more specific embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 show an embodiment of the imaging apparatus of the present invention. FIG. 1 is a perspective view illustrating a schematic configuration of an imaging device according to the present embodiment, and FIG. 2 is a plan view illustrating a configuration of the imaging device. The imaging apparatus according to the present embodiment includes two chips, an imaging chip (semiconductor chip for imaging) 101 and an image processing chip (semiconductor chip for image processing) 106, and the imaging chip 101 is stacked on the image processing chip 106. Have been. The imaging chip 101 includes a sensor unit 102 for converting light into an electric signal, a vertical scanning circuit 103 and a horizontal scanning circuit 104 for driving the sensor unit 102, and an amplifier 105 for amplifying a signal from the sensor unit 102. As shown in FIG. 2, the imaging chip 101 includes a timing pulse input terminal 112 to which a timing pulse is input from a timing pulse generation circuit (TG: Timing Generator) 107, and a video signal output for outputting a captured video signal. And a plurality of terminals including the terminal 113. In FIG. 2, only some of the plurality of terminals are shown, and other terminals are not shown. In FIG. 1, illustration of the terminals is omitted.

The transistors used in these circuits in the imaging chip 101 are all made of the same conductor, that is, all nMOS or all pMOS. The scanning circuits 103 and 104 are dynamic circuits. As a result, a through current peculiar to the CMOS circuit is not generated, and even when the timing pulse generation circuit 107 is provided outside the imaging chip 101, the influence of noise superimposed on the timing pulse supply line on the output of the imaging chip 101 is small. Become.

The image processing chip 106 includes a timing pulse generation circuit 107 for generating a signal for driving the imaging chip 101, a gain control amplifier (GCA: Gain Control Amplifier) 108 for adjusting the magnitude of a signal from the imaging chip 101, An AD conversion circuit (ADC: Analog / Digital Converter) 109 for converting the signal into a digital signal and an image processing circuit 110 for generating a luminance signal and a color signal from the signal of the imaging chip converted into the digital signal are provided. The transistors used in these circuits are of the CMOS type combining nMOS and pMOS used in conventional logic circuits. Further, as shown in FIG. 2, the image processing chip 106 includes a plurality of timing pulse output terminals 111 for outputting timing pulses, and a plurality of video signal input terminals 114 to which a video signal captured by the imaging chip 101 is input. It has terminals.

(4) The timing pulse output terminal 111 is arranged near the timing pulse input terminal 112, specifically, at a position closest to the timing pulse input terminal 112 as compared with other terminals of the image processing chip 106. That is, the timing pulse generation circuit 107 is arranged near the timing pulse input terminal 112. The timing pulse input from the timing pulse input terminal 112 is sent to the scanning circuits 103 and 104 and used to drive the sensor unit 102.

The video signal input terminal 114 is disposed near the video signal output terminal 113, specifically, at a position closest to the video signal output terminal 113 as compared with other terminals of the image processing chip 106. That is, the gain control amplifier 108 is arranged near the video signal output terminal 113. A video signal imaged by the imaging chip 101 is input to the image processing chip 106 via a video signal input terminal 114, and is converted into a digital signal through a gain control amplifier 108 and an AD conversion circuit 109. At 110, image processing is performed. Further, in the image processing chip 106, it is more preferable that the noise superimposed on the video signal is reduced not only outside the chip but also inside the chip by bringing the gain control amplifier 108 as close as possible to the video signal input terminal 114.

FIGS. 3A and 3B show two examples of a method of laminating the imaging chip 101 and the image processing chip 106. FIG.

FIG. 3A shows an image pickup chip 101 and an image processing chip 106 connected by wire bonding. The pads of the imaging chip 101 are connected to the pads of the image processing chip 106 by wires 201. Wire bonding itself is a method generally used in mass production processes, and is advantageous in terms of cost and reliability.

In this case, the gain control amplifier 108 is provided near the pad by providing a pad in a portion where the imaging chip 101 is not stacked.

FIG. 3B shows a method in which a through silicon electrode 202 is provided on the imaging chip 101, an electrode is drawn out from the bottom surface, and a bump 203 is provided thereon to connect to the image processing chip 106. The Si through electrode 202 is advantageous in that it can be downsized most, and may become mainstream in the future.

In this case, the video signal input terminal 114 and the gain control amplifier 108 of the image processing chip 106 are provided directly below the video signal output terminal 113 of the imaging chip 101.

The following effects can be obtained by adopting the above configuration.

First, since the entire circuit of the imaging chip 101 is formed of an nMOS or a pMOS, a through current peculiar to a CMOS circuit is eliminated, and even if a timing pulse supply line is arranged outside the imaging chip 101, the timing pulse supply line is superimposed on a power supply. The noise does not increase. Thus, the timing pulse generation circuit 107 and the AD conversion circuit 109 can be provided not on the imaging chip 101 but on the image processing chip 106 that can use a finer manufacturing process, and the chip area as a whole can be reduced. Cost reduction is possible. Secondly, since all circuits of the imaging chip 101 are formed of nMOS or pMOS, the manufacturing process is simplified, and the number of masks used in the manufacturing process is reduced, so that cost can be further reduced. Third, since all the circuits of the imaging chip 101 are formed of nMOSs or pMOSs, the number of manufacturing steps is reduced, and the factor of deteriorating the electrical characteristics of the analog section is reduced. Thereby, high performance can be achieved.

Fourth, by stacking the imaging chip 101 on the image processing chip 106, the length of the wiring connecting them can be shortened, the superposition of noise on the timing pulse supply line can be reduced, and higher performance can be achieved. Can be realized. Fifth, by arranging the video output terminal 113 of the imaging chip 101 and the video input terminal 114 of the image processing chip 106 near each other, and arranging the gain control amplifier 108 near the video input terminal 114, The superimposed noise can also be reduced. In the case where it is difficult to form an amplifier having a large amplification factor as in the present invention in which all the transistors are formed of the same conductor, a particularly large effect can be obtained. Sixth, by stacking the imaging chip 101 on the image processing chip 106, the mounting area can be made equal to or less than that in the case of a one-chip configuration, and ultra-miniaturization can be realized.

As described above, according to the present invention, an ultra-small, low-cost, high-performance imaging device can be realized. For this reason, many valuable application products can be produced by using this imaging device. For example, it is most desirable for a mobile phone to be small in size, but in addition to the high performance, particularly the high sensitivity, it is possible to shoot even in a dark scene without using a lighting device such as a strobe. Since a lighting device such as a strobe increases power consumption, it is extremely difficult to mount the lighting device on a mobile phone.

FIG. 4 shows an example of a configuration in a case where the imaging device according to the present invention is applied to a mobile phone. The mobile phone illustrated in FIG. 4 includes a microphone 301, an audio encoding unit 302, a system control unit 303, a communication control unit 304, an antenna 305, a speaker 306, a display control unit 307, and a display device 308. These are components provided in a conventional mobile phone.

This mobile phone further includes an imaging device 309 according to the present invention, and an image encoding unit 310 that encodes an image signal output from the imaging device 309. As shown in FIGS. 1 and 2, the imaging device 309 is mounted in a two-chip configuration including an imaging chip and an image processing chip.

に お い て In the mobile phone shown in FIG. 4, the voice input from the microphone 301 is encoded and compressed by the voice encoding unit 302. The compressed audio data is transferred by the system control unit 303 to the communication control unit 304, where modulation processing and the like for communication are performed, and transmitted from the antenna 305. In the case of reception, sound is output from the speaker 306 via the reverse route. In addition, the system control unit 303 controls the display control unit 307 as necessary, and displays necessary information on the display device 308. As described above, a camera-equipped mobile phone can be realized only by adding the imaging device 309 of the present invention and the image encoding unit 310 for encoding an image signal output from the imaging device 309 to a conventional mobile phone. .

In the case of a still image, the decoding of the image can be performed by the system control unit 303. Encoding of an image can also be performed by the system control unit 303, and in some cases, the image encoding unit 310 can be omitted. However, since the encoding of a moving image requires a large amount of processing, it is preferable to provide the image encoding unit 310 when the specification is such that the moving image can be handled. Although the decoding can be performed by the system control unit 303 as described above, it is preferable to provide a dedicated decoding circuit in the case of a specification that handles moving images.

The imaging device according to the present invention can be incorporated not only in a mobile phone but also in a portable information terminal having a similar configuration, such as a so-called PDA, with a similar configuration. By using the imaging apparatus of the present invention, a high-performance camera can be mounted on these small portable information terminals, and can be used instead of a digital still camera.

FIG. 5 shows an example of a configuration in which the imaging apparatus according to the present invention is applied to a digital still camera. The digital still camera shown in FIG. 5 includes, in addition to the imaging device 401 of the present invention, a system control unit 402 for controlling the whole, an image encoding / decoding unit 403 for compressing and expanding images, and a recording medium 405. A recording medium control unit 404 for recording the compressed image data, a display control unit 406 for displaying, and a display device 407 are provided.

(1) As shown in FIGS. 1 and 2, the imaging device 401 is mounted in a two-chip configuration including an imaging chip and an image processing chip. As shown by a dotted line in FIG. 5, a system control unit 402, an image encoding / decoding unit 403, a recording medium control unit 404, and a display control unit 406 are configured to be mounted on an image processing chip of the imaging device 401. Is also good.

(4) In the case of a digital still camera, an imaging chip with high pixels is required, so that the size of the imaging chip is inevitably larger than that of a mobile phone or the like. Therefore, the size of the image processing chip is inevitably increased, and it is preferable to integrate circuits other than the image processing unit.

The biggest effect of applying the imaging device of the present invention to a digital still camera is the point of miniaturization, but using the imaging device of the present invention also improves the performance of the digital camera as described below. Can contribute.

The conventional digital still camera uses a CCD type imaging chip as an imaging chip, but has the following problems. In the CCD type imaging chip, the sensor unit includes a photoelectric conversion element that converts light into electric charges and a CCD element that carries electric charges. Since the CCD element carries charges generated by the photoelectric conversion element, its size cannot be made much smaller than that of the photoelectric conversion element. That is, in the conventional digital still camera, the area ratio of the photoelectric conversion element cannot be increased.

On the other hand, in the digital still camera of the present embodiment, since the sensor portion of the imaging chip includes the photoelectric conversion element and the transistor, the size of the transistor can be smaller than that of the photoelectric conversion element. The ratio can be increased. Therefore, there is a possibility that the sensitivity can be made higher than that of the CCD type imaging chip. It has been said that the so-called MOS sensor used in the present invention has inferior performance to a CCD type imaging chip due to factors such as variations in transistors of each pixel. However, in recent years, techniques capable of overcoming these factors have been developed, and in addition, the imaging chip of the present invention has a reduced number of manufacturing steps due to the fact that all circuits are formed of nMOS or pMOS, and the analog section The cause of the deterioration of the electrical characteristics is reduced. As a result, there is a good possibility that the image quality can be improved as compared with a digital still camera using a conventional CCD imaging chip. Further, since the sensitivity is easily improved, a great effect can be obtained even when applied to a surveillance camera. Since the imaging device of the present invention can be extremely miniaturized while having high sensitivity, it can also contribute to miniaturization of the surveillance camera, and can realize a surveillance camera that can hide the location where it is difficult to know that the surveillance camera is being monitored. is there.

As described above, the present invention is useful as a solid-state imaging device having a small chip area as a whole and capable of reducing costs, and a device using the same.

1 is a perspective view illustrating a configuration of an embodiment of an imaging device according to the present invention. FIG. 1 is a plan view of the imaging device illustrated in FIG. 1. 1A and 1B show a chip laminating method in an imaging device of the present invention, wherein FIG. 1A is a cross-sectional view of a wire bonding method, and FIG. FIG. 2 is a block diagram illustrating a configuration of a mobile phone using the imaging device of the present invention. FIG. 2 is a block diagram illustrating a configuration of a digital still camera using the imaging device of the present invention. FIG. 2 is a block diagram showing a configuration of a conventional one-chip CMOS camera. FIG. 2 is a block diagram showing a configuration of a conventional two-chip CMOS camera.

Explanation of reference numerals

Reference Signs List 101 imaging chip 102 sensor unit 103 horizontal scanning circuit 104 vertical scanning circuit 105 amplifier 106 image processing chip 107 timing pulse generation circuit 108 gain control amplifier 109 AD conversion circuit 110 image processing circuit 111 timing pulse output terminal 112 timing pulse input terminal 113 video signal Output terminal 114 Video signal input terminal 301 Microphone 302 Audio encoding unit 303 System control unit 304 Communication control unit 305 Antenna 306 Speaker 307 Display control unit 308 Display device 309 Imaging device 310 Image encoding unit 401 Imaging device 402 System control unit 403 Image Encoding / decoding unit 404 Recording media control unit 405 Recording media 406 Display control unit 407 Display device 501 One-chip CMOS sensor 502 Image processing Path 503 Timing pulse generation circuit 504 Gain control amplifier 505 AD conversion circuit 506 Vertical scanning circuit 507 Sensor unit 508 Horizontal scanning circuit 601 Imaging chip 602 Timing pulse generation circuit 603 Sensor unit 604 Vertical scanning circuit 605 Horizontal scanning circuit 606 Gain control amplifier 607 AD Conversion circuit 608 Image processing chip

Claims (15)

An imaging semiconductor chip in which all transistors are formed of transistors of the same conductor,
A solid-state imaging device, comprising: an image processing semiconductor chip formed of a CMOS transistor. The solid-state imaging device according to claim 1, wherein the imaging semiconductor chip is stacked on the image processing semiconductor chip. 2. The solid-state imaging device according to claim 1, wherein all the transistors of the imaging semiconductor chip are configured by n-channel MOS transistors. The solid-state imaging device according to claim 1, wherein all transistors of the imaging semiconductor chip are configured by p-channel MOS transistors. The solid-state imaging device according to claim 1, wherein the imaging semiconductor chip includes a photoelectric conversion unit that converts light into electric charge, and an amplifier that amplifies a signal corresponding to the electric charge generated in the photoelectric conversion unit. The solid-state imaging device according to claim 1, wherein the imaging semiconductor chip and the image processing semiconductor chip are electrically connected by a bonding wire. The through-electrode is formed in the imaging semiconductor chip, and the imaging semiconductor chip and the image processing semiconductor chip are electrically connected to each other via a wiring connected to the through-electrode. Solid-state imaging device. The solid-state imaging device according to claim 7, wherein the through electrode is a Si through electrode. The solid-state imaging device according to claim 1, further comprising a timing pulse generation circuit that supplies a timing pulse to the imaging semiconductor chip, a gain control amplifier, and an analog-to-digital conversion circuit. The image processing semiconductor chip has a plurality of terminals including a timing pulse output terminal that outputs a timing pulse,
The imaging semiconductor chip has a plurality of terminals including a timing pulse input terminal to which the timing pulse is input,
The solid-state imaging device according to claim 2, wherein the imaging semiconductor chip is stacked on the image processing semiconductor chip such that the timing pulse input terminal and the timing pulse output terminal are arranged near each other. The imaging semiconductor chip has a plurality of terminals including a video signal output terminal for outputting a captured video signal,
The image processing semiconductor chip has a plurality of terminals including a video signal input terminal to which the video signal is input,
The solid-state imaging device according to claim 2, wherein the imaging semiconductor chip is stacked on the image processing semiconductor chip such that the video signal output terminal and the video signal input terminal are arranged near each other. An apparatus comprising: the solid-state imaging device according to claim 1; and an image processing unit that processes a still image or a moving image captured by the solid-state imaging device. 13. The device according to claim 12, which is a mobile phone. The device according to claim 12, which is a portable information terminal. 13. The device according to claim 12, which is a digital still camera.

Images