JP2018152754A5 - - Google Patents
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- JP2018152754A5 JP2018152754A5 JP2017048291A JP2017048291A JP2018152754A5 JP 2018152754 A5 JP2018152754 A5 JP 2018152754A5 JP 2017048291 A JP2017048291 A JP 2017048291A JP 2017048291 A JP2017048291 A JP 2017048291A JP 2018152754 A5 JP2018152754 A5 JP 2018152754A5
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- voltage
- operational amplifier
- frequency
- conversion
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- 238000006243 chemical reaction Methods 0.000 claims 19
- 230000000051 modifying Effects 0.000 claims 13
- 238000001514 detection method Methods 0.000 claims 2
- 238000009499 grossing Methods 0.000 claims 1
Claims (14)
入力データに基づいて前記複数の電圧から電圧選択を行い、選択電圧として第Ｋの電圧と第Ｌの電圧（Ｋ及びＬは互いに異なる１以上の整数）を出力する電圧選択回路と、
前記第Ｋの電圧が入力される第１の演算増幅器と、
前記第Ｌの電圧が入力される第２の演算増幅器と、
を含み、
前記第１、第２の演算増幅器は、チョッパー型の演算増幅器であることを特徴とするＤ／Ａ変換回路。 A voltage generation circuit that generates a plurality of voltages;
A voltage selection circuit that performs voltage selection from the plurality of voltages based on input data, and outputs a Kth voltage and an Lth voltage (K and L are different integers of one or more) as selection voltages;
A first operational amplifier to which the K-th voltage is input,
A second operational amplifier to which the L-th voltage is input,
Including
The D / A conversion circuit, wherein the first and second operational amplifiers are chopper-type operational amplifiers.
前記電圧生成回路と前記電圧選択回路とにより構成される第１のＤ／Ａ変換器と、
第２のＤ／Ａ変換器と、
を含み、
前記第１のＤ／Ａ変換器の前記電圧選択回路は、
前記入力データの上位側ビットに基づいて電圧選択を行い、
前記第２のＤ／Ａ変換器は、
前記第１の演算増幅器の第１の出力電圧と前記第２の演算増幅器の第２の出力電圧の間を電圧分割した複数の電圧を生成する第２の電圧生成回路と、
前記入力データの下位側ビットに基づいて、前記第２の電圧生成回路からの前記複数の電圧から電圧選択を行う第２の電圧選択回路と、
を含むことを特徴とするＤ／Ａ変換回路。 The D / A conversion circuit according to claim 1,
A first D / A converter including the voltage generation circuit and the voltage selection circuit;
A second D / A converter;
Including
The voltage selection circuit of the first D / A converter includes:
Performing voltage selection based on the upper bits of the input data;
The second D / A converter includes:
A second voltage generation circuit that generates a plurality of voltages obtained by voltage dividing between a first output voltage of the first operational amplifier and a second output voltage of the second operational amplifier;
A second voltage selection circuit that selects a voltage from the plurality of voltages from the second voltage generation circuit based on a lower bit of the input data;
A D / A conversion circuit comprising:
前記第２の電圧選択回路の出力電圧が入力される第３の演算増幅器を含み、
前記第３の演算増幅器は、チョッパー型の演算増幅器であることを特徴とするＤ／Ａ変換回路。 The D / A conversion circuit according to claim 2,
A third operational amplifier to which an output voltage of the second voltage selection circuit is input,
The D / A conversion circuit according to claim 3, wherein the third operational amplifier is a chopper type operational amplifier.
前記電圧生成回路は、
高電位側電源電圧と低電位側電源電圧を抵抗分割する第１のラダー抵抗回路と、
前記高電位側電源電圧と前記低電位側電源電圧を抵抗分割する第２のラダー抵抗回路を含み、
前記電圧選択回路は、
前記第１のラダー抵抗回路の複数の分割電圧から選択された電圧を、前記第Ｋの電圧として前記第１の演算増幅器に出力し、
前記第２のラダー抵抗回路の複数の分割電圧から選択された電圧を、前記第Ｌの電圧として前記第２の演算増幅器に出力することを特徴とするＤ／Ａ変換回路。 The D / A conversion circuit according to claim 2,
The voltage generation circuit,
A first ladder resistance circuit that resistance-divides the high-potential-side power supply voltage and the low-potential-side power supply voltage;
A second ladder resistor circuit for dividing the high-potential-side power supply voltage and the low-potential-side power supply voltage by resistance;
The voltage selection circuit,
Outputting a voltage selected from a plurality of divided voltages of the first ladder resistance circuit to the first operational amplifier as the Kth voltage;
A D / A conversion circuit, wherein a voltage selected from a plurality of divided voltages of the second ladder resistor circuit is output to the second operational amplifier as the L-th voltage.
前記第１のラダー抵抗回路の第ｓ（ｓは１以上の整数）の分割電圧が、前記第Ｋの電圧として前記第１の演算増幅器に供給される第１の場合において、前記第２のラダー抵抗回路の第ｔ（ｔは１以上の整数）の分割電圧が、前記第Ｌの電圧として前記第２の演算増幅器に供給され、
前記第１の場合に対して前記入力データが切り替わった第２の場合において、前記第１のラダー抵抗回路の第ｓ＋１の分割電圧が、前記第Ｋの電圧として前記第１の演算増幅器に供給され、前記第２のラダー抵抗回路の前記第ｔの分割電圧が、前記第Ｌの電圧として前記第２の演算増幅器に供給され、
前記第１の場合及び前記第２の場合に対して前記入力データが切り替わった第３の場合において、前記第１のラダー抵抗回路の前記第ｓ＋１の分割電圧が、前記第Ｋの電圧として前記第１の演算増幅器に供給され、前記第２のラダー抵抗回路の第ｔ＋１の分割電圧が、前記第Ｌの電圧として前記第２の演算増幅器に供給されることを特徴とするＤ／Ａ変換回路。 The D / A conversion circuit according to claim 4,
Wherein (in s 1 or more integer) first s of the first ladder resistor circuit divided voltage, In no event first supplied to the first operational amplifier as a voltage of the first K, the second The t-th (t is an integer equal to or greater than 1) divided voltage of the ladder resistance circuit is supplied to the second operational amplifier as the L-th voltage,
In the second case where the input data is switched with respect to the first case, the s + 1-th divided voltage of the first ladder resistance circuit is supplied to the first operational amplifier as the K-th voltage. , the divided voltage of the first t second ladder resistor circuit is supplied to the second operational amplifier as a voltage of the first L,
In the third case in which the input data is switched with respect to the first case and the second case, the s + 1-th divided voltage of the first ladder resistance circuit is the K-th voltage. 1 is supplied to the operational amplifier, wherein the (t + 1) th divided voltage of the second ladder resistor circuit, wherein the L D / a converter circuit, characterized in that to be supplied to the second operational amplifier as a voltage of.
前記周波数制御データである前記入力データのＤ／Ａ変換を行うと共に、Ｄ／Ａ変換により得られた電圧を平滑化するフィルター回路を有する、請求項１乃至５のいずれか一項に記載のＤ／Ａ変換回路と、
前記Ｄ／Ａ変換回路の出力電圧と振動子を用いて、前記周波数制御データにより設定される前記発振周波数の発振信号を生成する発振回路と、
を含むことを特徴とする回路装置。 A processing circuit that performs temperature compensation processing of the oscillation frequency based on the temperature detection data, and outputs frequency control data of the oscillation frequency;
The D according to any one of claims 1 to 5, further comprising: a filter circuit that performs D / A conversion of the input data that is the frequency control data and smoothes a voltage obtained by the D / A conversion. / A conversion circuit;
An oscillation circuit that generates an oscillation signal having the oscillation frequency set by the frequency control data, using an output voltage of the D / A conversion circuit and an oscillator;
A circuit device comprising:
前記Ｄ／Ａ変換回路は、
前記処理回路からｉ＝ｎ＋ｍビットの前記周波数制御データを受けて、前記周波数制御データのｍビットのデータに基づいて前記周波数制御データのｎビットのデータを変調する変調回路を含むことを特徴とする回路装置。 The circuit device according to claim 6,
The D / A conversion circuit includes:
A modulation circuit that receives the frequency control data of i = n + m bits from the processing circuit and modulates the n-bit data of the frequency control data based on the m-bit data of the frequency control data. Circuit device.
前記変調回路の変調周波数をｆｍとし、前記チョッパー型の演算増幅器のチョッピング周波数をｆｐとした場合に、ｆｍ＝ｆｐであることを特徴とする回路装置。 The circuit device according to claim 7,
A circuit device, wherein fm = fp, where the modulation frequency of the modulation circuit is fm and the chopping frequency of the chopper type operational amplifier is fp.
前記周波数制御データである入力データのＤ／Ａ変換を行うと共に、Ｄ／Ａ変換により得られた電圧を平滑化するフィルター回路を有するＤ／Ａ変換回路と、
前記フィルター回路の出力電圧と振動子を用いて、前記周波数制御データにより設定される前記発振周波数の発振信号を生成する発振回路と、
を含み、
前記Ｄ／Ａ変換回路は、
チョッパー型の演算増幅器と、
前記処理回路からｉ＝ｎ＋ｍビットの前記周波数制御データを受けて、前記周波数制御データのｍビットのデータに基づいて前記周波数制御データのｎビットのデータを変調する変調回路と、
を含み、
前記変調回路の変調周波数をｆｍとし、前記チョッパー型の演算増幅器のチョッピング周波数をｆｐとした場合に、ｆｍ＝ｆｐであることを特徴とする回路装置。 A processing circuit that performs temperature compensation processing of the oscillation frequency based on the temperature detection data, and outputs frequency control data of the oscillation frequency;
A D / A conversion circuit having a filter circuit for performing D / A conversion of the input data as the frequency control data and smoothing a voltage obtained by the D / A conversion;
Using an output voltage and a vibrator of the filter circuit, an oscillation circuit that generates an oscillation signal of the oscillation frequency set by the frequency control data,
Including
The D / A conversion circuit includes:
A chopper-type operational amplifier,
A modulation circuit that receives i = n + m bits of the frequency control data from the processing circuit and modulates n-bit data of the frequency control data based on the m-bit data of the frequency control data;
Including
A circuit device, wherein fm = fp, where the modulation frequency of the modulation circuit is fm and the chopping frequency of the chopper type operational amplifier is fp.
前記変調回路の変調周波数をｆｍとし、前記変調回路の変調パターンのうち最も周波数が低い変調パターンの周波数をｆｍｍｉｎ＝ｆｍ／Ｎ（Ｎは２以上の整数）とし、前記フィルター回路のカットオフ周波数をｆｃとした場合に、ｆｃ＜ｆｍｍｉｎであることを特徴とする回路装置。 The circuit device according to any one of claims 7 to 9,
The modulation frequency of the modulation circuit is fm, the frequency of the lowest modulation pattern among the modulation patterns of the modulation circuit is fmmin = fm / N (N is an integer of 2 or more), and the cutoff frequency of the filter circuit is fc <fmmin, where fc <fmmin.
前記チョッパー型の演算増幅器のチョッピング周波数をｆｐとした場合に、ｆｃ＜ｆｍｍｉｎ＜ｆｐであることを特徴とする回路装置。 The circuit device according to claim 10,
When the chopping frequency of the chopper type operational amplifier is fp, fc <fmmin <fp.
前記振動子と、
を含むことを特徴とする発振器。 A circuit device according to any one of claims 6 to 11,
The vibrator;
An oscillator comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017048291A JP6926546B2 (en) | 2017-03-14 | 2017-03-14 | Circuits, oscillators, electronics and mobiles |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017048291A JP6926546B2 (en) | 2017-03-14 | 2017-03-14 | Circuits, oscillators, electronics and mobiles |
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| Publication Number | Publication Date |
|---|---|
| JP2018152754A JP2018152754A (en) | 2018-09-27 |
| JP2018152754A5 true JP2018152754A5 (en) | 2020-03-12 |
| JP6926546B2 JP6926546B2 (en) | 2021-08-25 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021215342A1 (en) * | 2020-04-21 | 2021-10-28 | 株式会社村田製作所 | Conversion adapter |
| WO2023182278A1 (en) * | 2022-03-25 | 2023-09-28 | ラピステクノロジー株式会社 | Da converting device, display driver, and display device |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03217106A (en) * | 1990-01-23 | 1991-09-24 | Nippon Dempa Kogyo Co Ltd | Digital temperature compensated oscillator |
| KR100219021B1 (en) * | 1990-04-06 | 1999-09-01 | 제이 엘. 차스킨, 버나드 스나이더, 아더엠. 킹 | Third order sigma delta oversampled a/d converter network with low component sensitivity |
| JP3142747B2 (en) * | 1994-08-01 | 2001-03-07 | 松下電器産業株式会社 | Oversampling DA converter |
| JPH10290118A (en) * | 1997-02-12 | 1998-10-27 | Meidensha Corp | Digital temperature compensation crystal oscillator |
| JP4110681B2 (en) * | 1999-08-02 | 2008-07-02 | ソニー株式会社 | Digital / analog conversion circuit and analog / digital conversion circuit using the same |
| GB0108656D0 (en) * | 2001-04-06 | 2001-05-30 | Koninkl Philips Electronics Nv | Digital to analogue converter |
| US6937178B1 (en) * | 2003-05-15 | 2005-08-30 | Linear Technology Corporation | Gradient insensitive split-core digital to analog converter |
| JP4158731B2 (en) * | 2004-03-17 | 2008-10-01 | 株式会社デンソー | Ladder resistance type D / A conversion circuit |
| JP2005266346A (en) * | 2004-03-18 | 2005-09-29 | Seiko Epson Corp | Reference voltage generation circuit, data driver, display device and electronic equipment |
| JP2006279377A (en) * | 2005-03-29 | 2006-10-12 | Handotai Rikougaku Kenkyu Center:Kk | Chopper amplifier circuit |
| KR100800494B1 (en) * | 2007-02-09 | 2008-02-04 | 삼성전자주식회사 | Apparatus and method for digital analog converting, and display panel driver comprising the same |
| JP2016134738A (en) * | 2015-01-19 | 2016-07-25 | セイコーエプソン株式会社 | Oscillator, electronic apparatus and mobile |
| JP6493661B2 (en) * | 2015-01-19 | 2019-04-03 | セイコーエプソン株式会社 | D / A conversion circuit, oscillator, electronic device, and moving object |
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2017
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