JP2017041842A - Current detection circuit - Google Patents

Current detection circuit Download PDF

Info

Publication number
JP2017041842A
JP2017041842A JP2015163937A JP2015163937A JP2017041842A JP 2017041842 A JP2017041842 A JP 2017041842A JP 2015163937 A JP2015163937 A JP 2015163937A JP 2015163937 A JP2015163937 A JP 2015163937A JP 2017041842 A JP2017041842 A JP 2017041842A
Authority
JP
Japan
Prior art keywords
amplifier
current detection
voltage dividing
load
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015163937A
Other languages
Japanese (ja)
Other versions
JP6646380B2 (en
Inventor
横山 健司
Kenji Yokoyama
健司 横山
康弘 逸見
Yasuhiro Henmi
康弘 逸見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Korg Inc
Original Assignee
Korg Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korg Inc filed Critical Korg Inc
Priority to JP2015163937A priority Critical patent/JP6646380B2/en
Publication of JP2017041842A publication Critical patent/JP2017041842A/en
Application granted granted Critical
Publication of JP6646380B2 publication Critical patent/JP6646380B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

PROBLEM TO BE SOLVED: To provide a current detection circuit capable of detecting the current flowing in the load of the BTL amplifier with a simple and general-purpose configuration.SOLUTION: The current detection circuit comprises a first amplifier 121 for outputting a predetermined signal, a second amplifier 122 for outputting a signal having an opposite phase to the output signal of the first amplifier, voltage dividing resistors 13 and 14 for dividing a potential difference between both ends of a load connecting the output terminal of the first amplifier and the output terminal of the second amplifier, the voltage dividing resistors 13 and 14, at the connection point of the voltage dividing resistors, having resistance values determined so that the amplitude of the output signal of the first amplifier and the amplitude of the output signal of the second amplifier cancel each other, a load current detection resistor 16 connected in series with the load 15, and a difference detection unit 17 for detecting the current flowing in the load on the basis of a potential difference between a potential at a connection point of the first and second voltage dividing resistors, a reference potential which is a predetermined potential, the ratio of the resistance values of the first and second voltage dividing resistors, and a resistance value of the load current detecting resistor.SELECTED DRAWING: Figure 1

Description

本発明は負荷に流れる電流を検出する電流検出回路に関する。   The present invention relates to a current detection circuit that detects a current flowing through a load.

特許文献1には、電源電圧の急変動により、オペアンプの動作点を定める基準電圧が電源電圧の1/2から遷移した場合であっても出力ダイナミックレンジを確保することができるBTLアンプが開示されている。BTLは、Balanced Tied Load,Bridged Transformer Less,Balanced Transformer Less等の略である。   Patent Document 1 discloses a BTL amplifier that can secure an output dynamic range even when a reference voltage that determines an operating point of an operational amplifier is shifted from ½ of a power supply voltage due to a sudden change in power supply voltage. ing. BTL is an abbreviation for Balanced Tied Load, Bridged Transformer Less, Balanced Transformer Less, and the like.

また特許文献2には、マスターアンプとスレーブアンプによって負荷をBTL駆動するとともに、負荷に直列に介在する電流検出抵抗の発生電圧をマスターアンプの反転入力側に帰還させることにより、負荷への通電電流を入力信号に応じて制御することができる定電流駆動回路が開示されている。特許文献2の定電流駆動回路によれば、電流検出抵抗の発生電圧が帰還されるマスターアンプの反転入力は、そのマスターアンプの負帰還動作によって基準電位に仮想短絡されることにより、ほぼ一定電位に保たれるようになるのでアンプの同相入力電圧範囲の制限を受けない。   Further, in Patent Document 2, the current is supplied to the load by driving the load BTL with the master amplifier and the slave amplifier and feeding back the generated voltage of the current detection resistor interposed in series with the load to the inverting input side of the master amplifier. Is disclosed as a constant current drive circuit that can be controlled in accordance with an input signal. According to the constant current drive circuit of Patent Document 2, the inverting input of the master amplifier to which the voltage generated by the current detection resistor is fed back is virtually short-circuited to the reference potential by the negative feedback operation of the master amplifier. Therefore, the common mode input voltage range of the amplifier is not limited.

特開2013−038538号公報JP 2013-038538 A 特開平7−38351号公報JP-A-7-38351

特許文献1には、負荷に流れる電流に応じて様々な制御を実行するという着眼がない。一方、特許文献2には、電流検出抵抗における発生電圧をマスターアンプの反転入力側に帰還させることにより、マスターアンプの反転入力を一定電位に保つという着眼がある。しかしながら同文献の定電流駆動回路は、負荷に流れる電流に応じて様々な制御を行うための汎用的な構成とはいえない。そこで本発明では、BTLアンプを用いた簡易かつ汎用的な構成で負荷に流れる電流を検出できる電流検出回路を提供することを目的とする。   Patent Document 1 does not focus on executing various controls according to the current flowing through the load. On the other hand, Patent Document 2 focuses on keeping the inverting input of the master amplifier at a constant potential by feeding back the voltage generated in the current detection resistor to the inverting input side of the master amplifier. However, the constant current drive circuit disclosed in this document cannot be said to be a general-purpose configuration for performing various controls according to the current flowing through the load. Therefore, an object of the present invention is to provide a current detection circuit that can detect a current flowing through a load with a simple and general-purpose configuration using a BTL amplifier.

本発明の電流検出回路は、第1の増幅器と、第2の増幅器と、第1、および第2の分圧抵抗と、負荷電流検出抵抗と、差分検出部を含む構成である。   The current detection circuit of the present invention includes a first amplifier, a second amplifier, first and second voltage dividing resistors, a load current detection resistor, and a difference detection unit.

第1の増幅器は、所定の信号を出力する。第2の増幅器は、第1の増幅器の出力信号と逆相の信号を出力する。第1、および第2の分圧抵抗は、第1の増幅器の出力端子と第2の増幅器の出力端子を接続する負荷の両端の電位差を分圧する分圧抵抗であって、第1、および第2の分圧抵抗の接続点において、第1の増幅器の出力信号の振幅と、第2の増幅器の出力信号の振幅とが打ち消し合うように、各抵抗値が定められている。負荷電流検出抵抗は、負荷に直列に接続されている。差分検出部は、第1、および第2の分圧抵抗の接続点の電位と所定の電位である基準電位の電位差と、第1、および第2の分圧抵抗の抵抗値の比と、負荷電流検出抵抗の抵抗値に基づいて、負荷に流れる電流を検出する。   The first amplifier outputs a predetermined signal. The second amplifier outputs a signal having a phase opposite to that of the output signal of the first amplifier. The first and second voltage dividing resistors are voltage dividing resistors for dividing a potential difference between both ends of a load connecting the output terminal of the first amplifier and the output terminal of the second amplifier. Each resistance value is determined so that the amplitude of the output signal of the first amplifier and the amplitude of the output signal of the second amplifier cancel each other at the connection point of the two voltage dividing resistors. The load current detection resistor is connected in series with the load. The difference detection unit includes a potential difference between a potential at a connection point of the first and second voltage dividing resistors and a reference potential which is a predetermined potential, a ratio of resistance values of the first and second voltage dividing resistors, and a load. Based on the resistance value of the current detection resistor, the current flowing through the load is detected.

本発明の電流検出回路によれば、BTLアンプを用いた簡易かつ汎用的な構成で負荷に流れる電流を検出できる。   According to the current detection circuit of the present invention, the current flowing through the load can be detected with a simple and general-purpose configuration using a BTL amplifier.

実施例1の電流検出回路の構成を示す回路図。FIG. 3 is a circuit diagram illustrating a configuration of a current detection circuit according to the first embodiment. 実施例2の電流検出回路の構成を示す回路図。FIG. 6 is a circuit diagram illustrating a configuration of a current detection circuit according to a second embodiment. 実施例3の電流検出回路の構成を示す回路図。FIG. 6 is a circuit diagram illustrating a configuration of a current detection circuit according to a third embodiment. 実施例4の電流検出回路の構成を示す回路図。FIG. 6 is a circuit diagram illustrating a configuration of a current detection circuit according to a fourth embodiment. 実施例5の電流検出回路の構成を示す回路図。FIG. 10 is a circuit diagram illustrating a configuration of a current detection circuit according to a fifth embodiment. 実施例6の電流検出回路の構成を示す回路図。FIG. 10 is a circuit diagram illustrating a configuration of a current detection circuit according to a sixth embodiment. 従来例と実施例1の動作比較用回路図。FIG. 3 is a circuit diagram for comparison of operation between a conventional example and Example 1. 従来例と実施例1の動作比較用波形図。FIG. 4 is a waveform diagram for comparison of operation between a conventional example and Example 1.

以下、本発明の実施の形態について、詳細に説明する。なお、同じ機能を有する構成部には同じ番号を付し、重複説明を省略する。   Hereinafter, embodiments of the present invention will be described in detail. In addition, the same number is attached | subjected to the structure part which has the same function, and duplication description is abbreviate | omitted.

以下、図1を参照して実施例1の電流検出回路の構成、および動作について説明する。図1は、本実施例の電流検出回路1の構成を示す回路図である。同図に示すように、本実施例の電流検出回路1は、信号入力部10と、帰還制御部11と、BTLアンプ12と、第1の分圧抵抗13と、第2の分圧抵抗14と、負荷15と、負荷電流検出抵抗16と、差分検出部17を含む構成である。BTLアンプ12は、第1の増幅器121と、第2の増幅器122を含む構成である。なお本実施例においてBTLアンプ12は、正電源電圧+Vcc、負電源電圧−Veeの両電源アンプである。 The configuration and operation of the current detection circuit according to the first embodiment will be described below with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of a current detection circuit 1 of the present embodiment. As shown in the figure, the current detection circuit 1 of this embodiment includes a signal input unit 10, a feedback control unit 11, a BTL amplifier 12, a first voltage dividing resistor 13, and a second voltage dividing resistor 14. And a load 15, a load current detection resistor 16, and a difference detection unit 17. The BTL amplifier 12 includes a first amplifier 121 and a second amplifier 122. Note BTL amplifier 12 in the present embodiment, the positive supply voltage + V cc, a dual-supply amplifiers ee negative supply voltage -V.

第1の増幅器121は、所定の信号を出力する。ここで、V(t)を時刻tを変数とする増幅器出力信号の電圧を表す関数とし、第1の増幅器121が出力する信号の直流成分(以下、基準電位Vともいう)は0であるものとし、第1の増幅器121の出力信号をnV(t)+0と表すものとする。ただし、nは任意の正の数とする。 The first amplifier 121 outputs a predetermined signal. Here, V (t) is a function representing the voltage of the amplifier output signal with time t as a variable, and the DC component (hereinafter also referred to as reference potential V B ) of the signal output from the first amplifier 121 is zero. Assume that the output signal of the first amplifier 121 is represented as nV (t) +0. Here, n is an arbitrary positive number.

第2の増幅器122は、第1の増幅器121の出力信号と逆相の信号である−V(t)+0を出力する。負荷15は、第1の増幅器121の出力端子と第2の増幅器122の出力端子を接続している。負荷電流検出抵抗16は、負荷15に直列に接続される。なお、後述する第1、及び第2の分圧抵抗13、14の抵抗値は十分に大きく、負荷15および負荷電流検出抵抗16に流れる電流Iは近似的に等しいものと見做せるものとする。 The second amplifier 122 outputs −V (t) +0, which is a signal having a phase opposite to that of the output signal of the first amplifier 121. The load 15 connects the output terminal of the first amplifier 121 and the output terminal of the second amplifier 122. The load current detection resistor 16 is connected to the load 15 in series. The resistance value of the first, and second voltage dividing resistors 13 and 14 will be described later is sufficiently large, the current I L flowing through the load 15 and the load current detecting resistor 16 as causes deemed equal to approximately To do.

第1、および第2の分圧抵抗13、14は、負荷15の両端の電位差を分圧する分圧抵抗である。第1、および第2の分圧抵抗13、14の接続点において、第1の増幅器121の出力信号の振幅と、第2の増幅器122の出力信号の振幅とが打ち消し合うように、各抵抗値が定められている。同図の例において値nを用いて抵抗値を定義するならば、第1の分圧抵抗13の抵抗値がnRであるとき、第2の分圧抵抗14の抵抗値はRである。   The first and second voltage dividing resistors 13 and 14 are voltage dividing resistors that divide the potential difference between both ends of the load 15. Each resistance value is set so that the amplitude of the output signal of the first amplifier 121 and the amplitude of the output signal of the second amplifier 122 cancel each other at the connection point of the first and second voltage dividing resistors 13 and 14. Is stipulated. If the resistance value is defined using the value n in the example of the figure, when the resistance value of the first voltage dividing resistor 13 is nR, the resistance value of the second voltage dividing resistor 14 is R.

同図に示すように、負荷電流検出抵抗16と、第2分圧抵抗14の接続点の電位は、―V(t)+0+Iと表される。ただし、Rは、負荷電流検出抵抗16の抵抗値を示し、既知であるものとする。また、第1の増幅器の出力端子の電位は前述したように、nV(t)+0と表される。第1、および第2の分圧抵抗13、14の接続点の電位Vは、 As shown in the figure, the potential at the connection point of the load current detection resistor 16 and the second voltage dividing resistor 14 is expressed as −V (t) + 0 + I L R S. However, R S indicates the resistance value of the load current detection resistor 16 and is known. Further, as described above, the potential of the output terminal of the first amplifier is expressed as nV (t) +0. The potential V C at the connection point of the first and second voltage dividing resistors 13 and 14 is:

Figure 2017041842
Figure 2017041842

となる。上記計算式に示したように、第1、第2の増幅器121、122の出力信号の電圧の振幅比がn:1であって、第1、第2の分圧抵抗13、14の抵抗値の比が同様にn:1であるとき、第1、第2の増幅器121、122の出力信号の交流成分は互いに打ち消し合い、V(t)の項はキャンセルされる。n=1とすれば、第1、第2の増幅器121、122の出力信号の電圧の振幅比は1:1であって、第1、第2の分圧抵抗13、14の抵抗値の比は1:1、つまり二つの分圧抵抗の抵抗値は等しくなる。 It becomes. As shown in the above calculation formula, the amplitude ratio of the voltages of the output signals of the first and second amplifiers 121 and 122 is n: 1, and the resistance values of the first and second voltage dividing resistors 13 and 14 are as follows. Similarly, when the ratio of n is n: 1, the AC components of the output signals of the first and second amplifiers 121 and 122 cancel each other, and the term V (t) is cancelled. If n = 1, the amplitude ratio of the voltages of the output signals of the first and second amplifiers 121 and 122 is 1: 1, and the ratio of the resistance values of the first and second voltage dividing resistors 13 and 14 is 1: 1. Is 1: 1, that is, the resistance values of the two voltage dividing resistors are equal.

同図に示すように、差分検出部17は、第1、および第2の分圧抵抗13、14の接続点と、グラウンドに接続され、二点間の電位差を検出する機能を備える。差分検出部17は、第1、および第2の分圧抵抗13、14の接続点の電位   As shown in the figure, the difference detector 17 is connected to the connection point of the first and second voltage dividing resistors 13 and 14 and the ground, and has a function of detecting a potential difference between the two points. The difference detection unit 17 is a potential at a connection point of the first and second voltage dividing resistors 13 and 14.

Figure 2017041842
Figure 2017041842

と基準電位V(本実施例においてV=0、すなわちグラウンドの電位)の電位差である And the reference potential V B (in this embodiment, V B = 0, that is, the ground potential).

Figure 2017041842
Figure 2017041842

に基づき、値nと、負荷電流検出抵抗の抵抗値Rに基づいて、負荷に流れる電流Iを検出する。差分検出部17は検出した電流Iを、帰還制御部11に帰還する。なお、本実施例では差分検出部17を独立した構成要件として表したが、差分検出部17は場合により省略することができる。例えば本実施例の電流検出回路1を単に電圧電流変換回路として用いる場合などには、差分検出部17を省略し、上述のVを単に帰還電圧として入力信号に加算するだけで足りる。 The basis, and the value n, based on the resistance value R S of the load current detecting resistor to detect the current I L flowing through the load. The difference detection unit 17 feeds back the detected current IL to the feedback control unit 11. In the present embodiment, the difference detection unit 17 is represented as an independent component, but the difference detection unit 17 may be omitted depending on circumstances. For example, when using a current detection circuit 1 of this embodiment only as a voltage-current conversion circuit is omitted difference detection unit 17, just sufficient simply added to the input signal as the feedback voltage V C of the above.

帰還制御部11は、電流Iに応じた所定の制御を実行する。具体的には、帰還制御部11は、信号入力部10からの信号と差分検出部17からの信号に応じて負荷(装置)を駆動するための元信号を生成する。生成された信号は相補信号出力回路を介して正相信号と逆相信号とされ負荷(装置)を駆動する。 Feedback control unit 11 executes a predetermined control corresponding to the current I L. Specifically, the feedback control unit 11 generates an original signal for driving a load (apparatus) according to the signal from the signal input unit 10 and the signal from the difference detection unit 17. The generated signal is converted into a normal phase signal and a reverse phase signal via a complementary signal output circuit, and drives a load (device).

最もシンプルな構成では、帰還制御部11を加算回路のみで構成することができる。差分検出部17の出力を入力信号に加えることで帰還をかければ、入力信号に応じて負荷回路に電流を流す、電圧電流変換回路として動作する。前述したように、BTLアンプが両電源の場合、基準電位がGND(グラウンド)となるので差分検出部17は独立な回路として用意しなくてもよい。負荷に与える電力の上限を設定する必要がある場合には、検出電流値の上限を設定し上限値との差分が0に漸近するように相補信号の波形を制御すればよい。   In the simplest configuration, the feedback control unit 11 can be configured with only an adder circuit. If feedback is applied by adding the output of the difference detection unit 17 to the input signal, it operates as a voltage-current conversion circuit that allows current to flow through the load circuit in accordance with the input signal. As described above, when the BTL amplifier is a dual power supply, the reference potential is GND (ground), so the difference detection unit 17 does not have to be prepared as an independent circuit. When it is necessary to set the upper limit of the power applied to the load, the upper limit of the detected current value may be set and the waveform of the complementary signal may be controlled so that the difference from the upper limit value gradually approaches zero.

本実施例の電流検出回路1によれば、分圧抵抗の接続点において、BTLアンプ12の二つの増幅器の出力信号の交流成分が打ち消されるように構成したため、差分検出部17は分圧抵抗の接続点の電位を参照することにより負荷に流れる電流を検出できる。上記構成は簡易かつ汎用的であるため、負荷に流れる電流の検出が必要なあらゆる製品に利用することができる。   According to the current detection circuit 1 of the present embodiment, since the AC component of the output signals of the two amplifiers of the BTL amplifier 12 is canceled at the connection point of the voltage dividing resistor, the difference detecting unit 17 has the voltage dividing resistor. The current flowing through the load can be detected by referring to the potential at the connection point. Since the above configuration is simple and versatile, it can be used for any product that requires detection of the current flowing through the load.

また、負荷をパルス波形を有する信号で駆動させる場合、従来の回路構成(負荷電流検出抵抗の両端の電位差を測定する構成)では高速大振幅の波形を扱うことになるため安定な動作を確保することが困難であった。   Also, when driving the load with a signal having a pulse waveform, the conventional circuit configuration (configuration for measuring the potential difference between both ends of the load current detection resistor) handles a high-speed large-amplitude waveform, thus ensuring stable operation. It was difficult.

図7に、従来例と本実施例を電圧波形で比較するための電位差検出回路を示し、図8に、図7に示した各計測点における電圧波形を示した。図7に示す電位差検出回路70は、第1抵抗701、第2抵抗702、第3抵抗703、第4抵抗704、オペアンプ705を用いて構成した回路例であり、電位差を計測する場合に従来から一般的に用いられている回路である。オペアンプ705の反転入力端子、非反転入力端子は第1抵抗701、第2抵抗702を介して、負荷電流検出抵抗16の両端に接続される。オペアンプ705の反転入力端子は、オペアンプ705の出力端子に第3抵抗703を介して接続される。オペアンプ705の非反転入力端子は、第4抵抗704を介してグラウンドに接続される。   FIG. 7 shows a potential difference detection circuit for comparing the conventional example and the present embodiment with voltage waveforms, and FIG. 8 shows voltage waveforms at each measurement point shown in FIG. The potential difference detection circuit 70 shown in FIG. 7 is a circuit example configured by using a first resistor 701, a second resistor 702, a third resistor 703, a fourth resistor 704, and an operational amplifier 705. Conventionally, a potential difference is measured. This is a commonly used circuit. The inverting input terminal and the non-inverting input terminal of the operational amplifier 705 are connected to both ends of the load current detection resistor 16 via the first resistor 701 and the second resistor 702. The inverting input terminal of the operational amplifier 705 is connected to the output terminal of the operational amplifier 705 via the third resistor 703. The non-inverting input terminal of the operational amplifier 705 is connected to the ground via the fourth resistor 704.

分圧抵抗13、14は本実施例の方式と負荷電流検出抵抗16の両端の電位差を計測する従来方式の効果を同一回路で比較する為に設けた。なおn=1とし、分圧抵抗13、14の抵抗値は何れもRであるものとする。   The voltage dividing resistors 13 and 14 are provided in order to compare the effect of the method of this embodiment and the conventional method of measuring the potential difference between both ends of the load current detection resistor 16 in the same circuit. It is assumed that n = 1 and the resistance values of the voltage dividing resistors 13 and 14 are both R.

E0は分圧抵抗13、14の接続点の電圧、E1はオペアンプ70の反転入力端子の電圧、E2は非反転入力端子の電圧をそれぞれ計測するために設けた計測点であり、分圧抵抗13,14の抵抗値は何れもR=33kΩであるものとする。波形表示のため、負荷電流検出抵抗16の抵抗値はRs=2Ωとしたが更に低い抵抗値を用いることが望ましい。   E0 is a voltage at the connection point of the voltage dividing resistors 13 and 14, E1 is a voltage at the inverting input terminal of the operational amplifier 70, E2 is a measuring point provided for measuring the voltage at the non-inverting input terminal, and the voltage dividing resistor 13 14 are assumed to be R = 33 kΩ. For the waveform display, the resistance value of the load current detection resistor 16 is Rs = 2Ω, but it is desirable to use a lower resistance value.

図8に示した波形は、GND電位(0V)に対するE0、E1,E2の電圧がPWM波形に応じて変化する様子を示している。これらの電圧波形を得るために、正弦波の信号入力に対応するPWM波形でスピーカ負荷15を駆動した。   The waveform shown in FIG. 8 shows how the voltages of E0, E1, and E2 with respect to the GND potential (0 V) change according to the PWM waveform. In order to obtain these voltage waveforms, the speaker load 15 was driven with a PWM waveform corresponding to a sine wave signal input.

負荷電流検出抵抗16の両端の電位差を計測する方式ではオペアンプ705の入力端子E1、E2にはE0よりも高電圧のパルス波形が加わっていることがわかる。   It can be seen that in the method of measuring the potential difference between both ends of the load current detection resistor 16, a pulse waveform having a voltage higher than that of E0 is applied to the input terminals E1 and E2 of the operational amplifier 705.

一方、本実施例の電流検出回路1では、分圧抵抗の接続点においてパルス成分を非常に少なくすることができるため、本実施例の電流検出回路1をPWM出力のようなデジタルパワーアンプの出力制御に用いる場合、差分検出部17にスルーレートが高く同相除去比の大きいパルス信号用の特殊なオペアンプを使用する必要がなく、差分検出部17に使用するオペアンプを通常のオペアンプとすることができ、コストの削減に寄与する。   On the other hand, in the current detection circuit 1 of the present embodiment, the pulse component can be greatly reduced at the connection point of the voltage dividing resistor. Therefore, the current detection circuit 1 of the present embodiment is output from a digital power amplifier such as a PWM output. When used for control, it is not necessary to use a special operational amplifier for a pulse signal having a high slew rate and a large common mode rejection ratio for the difference detection unit 17, and the operational amplifier used for the difference detection unit 17 can be a normal operational amplifier. Contributes to cost reduction.

なお、PWM出力のようなデジタルパワーアンプの出力制御に用いる場合には正負二値のパルス波形で駆動すればよいので、第1、第2の増幅器121、122には、例えばC−MOSのインバータ回路を直列接続することで得られる相補的な出力をBTL出力として用いることもできる。   When used for output control of a digital power amplifier such as PWM output, it is sufficient to drive with a positive / negative binary pulse waveform, so that the first and second amplifiers 121 and 122 include, for example, C-MOS inverters. Complementary outputs obtained by connecting circuits in series can also be used as BTL outputs.

実施例1では両電源のBTLアンプを使用した電流検出回路を開示した。実施例2では、片電源のBTLアンプを使用した場合の電流検出回路について説明する。以下、図2を参照して、本実施例の電流検出回路の構成、および動作について説明する。図2は、本実施例の電流検出回路2の構成を示す回路図である。同図に示すように、本実施例の電流検出回路2は、信号入力部10と、帰還制御部21と、BTLアンプ22と、第1の分圧抵抗13と、第2の分圧抵抗14と、第3の分圧抵抗23と、第4の分圧抵抗24と、負荷15と、負荷電流検出抵抗16と、差分検出部27を含む構成である。BTLアンプ22は、第1の増幅器221と、第2の増幅器222を含む構成である。なお本実施例においてBTLアンプ22は、正電源電圧+Vcc、負電源電圧0の片電源アンプである。 In the first embodiment, a current detection circuit using a BTL amplifier with both power supplies is disclosed. In the second embodiment, a current detection circuit in the case of using a single power supply BTL amplifier will be described. Hereinafter, the configuration and operation of the current detection circuit of this embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration of the current detection circuit 2 of the present embodiment. As shown in the figure, the current detection circuit 2 of this embodiment includes a signal input unit 10, a feedback control unit 21, a BTL amplifier 22, a first voltage dividing resistor 13, and a second voltage dividing resistor 14. And a third voltage dividing resistor 23, a fourth voltage dividing resistor 24, a load 15, a load current detecting resistor 16, and a difference detecting unit 27. The BTL amplifier 22 includes a first amplifier 221 and a second amplifier 222. In the present embodiment, the BTL amplifier 22 is a single power supply amplifier having a positive power supply voltage + Vcc and a negative power supply voltage 0.

第1の増幅器221は、所定の信号を出力する。時刻tを変数とする増幅器出力信号の電圧を表す関数V(t)、振幅比nを用い、第1の増幅器221が出力する信号の直流成分をVとし、第1の増幅器221の出力信号をnV(t)+Vと表すものとする。 The first amplifier 221 outputs a predetermined signal. Using the function V (t) representing the voltage of the amplifier output signal with the time t as a variable and the amplitude ratio n, the direct current component of the signal output from the first amplifier 221 is V B, and the output signal of the first amplifier 221 the assumed to represent the nV (t) + V B.

第2の増幅器222は、第1の増幅器221の出力信号と逆相の信号である−V(t)+Vを出力する。負荷15は、第1の増幅器221の出力端子と第2の増幅器222の出力端子を接続している。負荷電流検出抵抗16は、実施例1同様負荷15に直列に接続される。なお、第1〜第4の分圧抵抗13〜24の抵抗値は十分に大きく、負荷15および負荷電流検出抵抗16に流れる電流Iは近似的に等しいものと見做せるものとする。 The second amplifier 222 outputs a -V (t) + V B is the signal of the output signal and the opposite phase of the first amplifier 221. The load 15 connects the output terminal of the first amplifier 221 and the output terminal of the second amplifier 222. The load current detection resistor 16 is connected in series to the load 15 as in the first embodiment. The resistance value of the first to fourth voltage dividing resistors 13 through 24 is sufficiently large, the current I L flowing through the load 15 and the load current detecting resistor 16 is assumed to deemed equal to approximately.

第3および第4の分圧抵抗23、24は、第1の増幅器の出力端子と第2の増幅器の出力端子の電位差を所定の比率で分圧する分圧抵抗である。第3の分圧抵抗の抵抗値をnRとし、第4の分圧抵抗の抵抗値をRとすると、第3および第4の分圧抵抗23、24の接続点における電位は、基準電位Vと等しくなる。詳細には、第3、および第4の分圧抵抗23、24の接続点の電位V’は、 The third and fourth voltage dividing resistors 23 and 24 are voltage dividing resistors that divide the potential difference between the output terminal of the first amplifier and the output terminal of the second amplifier at a predetermined ratio. When the resistance value of the third voltage dividing resistor is nR X and the resistance value of the fourth voltage dividing resistor is R X , the potential at the connection point of the third and fourth voltage dividing resistors 23 and 24 is the reference potential. Equals V B. Specifically, the potential V C ′ at the connection point of the third and fourth voltage dividing resistors 23 and 24 is

Figure 2017041842
Figure 2017041842

となる。一方、第1、および第2の分圧抵抗13、14の接続点の電位Vは、 It becomes. On the other hand, the potential V C at the connection point of the first and second voltage dividing resistors 13 and 14 is

Figure 2017041842
Figure 2017041842

となる。上記計算式に示したように、第1、第2の増幅器221、222の出力信号の電圧の振幅比がn:1であって、第1、第2の分圧抵抗13、14の抵抗値の比が同様にn:1であるとき、実施例1と同様に、V(t)の項はキャンセルされる。n=1とすれば、第1、第2の増幅器121、122の出力信号の電圧の振幅比は1:1、第1、第2の分圧抵抗13、14の抵抗値の比も1:1、第3、第4の分圧抵抗23、24の抵抗値の比も1:1となる。 It becomes. As shown in the above calculation formula, the amplitude ratio of the voltages of the output signals of the first and second amplifiers 221 and 222 is n: 1, and the resistance values of the first and second voltage dividing resistors 13 and 14 are as follows. Similarly, when the ratio of n is n: 1, the term V (t) is canceled as in the first embodiment. If n = 1, the amplitude ratio of the voltages of the output signals of the first and second amplifiers 121 and 122 is 1: 1, and the ratio of the resistance values of the first and second voltage dividing resistors 13 and 14 is also 1: The ratio of the resistance values of the first, third, and fourth voltage dividing resistors 23 and 24 is also 1: 1.

同図に示すように、差分検出部27は、第1、および第2の分圧抵抗13、14の接続点と、第3、および第4の分圧抵抗23、24の接続点に接続され、二点間の電位差を検出する機能を備える。差分検出部27は、第1、および第2の分圧抵抗13、14の接続点の電位   As shown in the figure, the difference detection unit 27 is connected to the connection point of the first and second voltage dividing resistors 13 and 14 and the connection point of the third and fourth voltage dividing resistors 23 and 24. And a function of detecting a potential difference between two points. The difference detector 27 is a potential at the connection point of the first and second voltage dividing resistors 13 and 14.

Figure 2017041842
Figure 2017041842

と第3、および第4の分圧抵抗23、24の接続点の電位Vの電位差、すなわち And the potential difference of the potential V B at the connection point of the third and fourth voltage dividing resistors 23 and 24, that is,

Figure 2017041842
Figure 2017041842

に基づき、値nと、負荷電流検出抵抗の抵抗値Rに基づいて、負荷に流れる電流Iを検出する。差分検出部27は検出した電流Iを、帰還制御部21に帰還する。帰還制御部21は、電流Iに応じた所定の制御を実行する。 The basis, and the value n, based on the resistance value R S of the load current detecting resistor to detect the current I L flowing through the load. The difference detection unit 27 feeds back the detected current IL to the feedback control unit 21. Feedback controller 21 performs a predetermined control corresponding to the current I L.

本実施例の電流検出回路2によれば、実施例1の構成に加え、第3、第4の分圧抵抗の接続点の電位が基準電位となるように構成したため、片電源BTLアンプを用いた場合であっても、実施例1と同様の効果を奏する。   According to the current detection circuit 2 of the present embodiment, in addition to the configuration of the first embodiment, since the potential at the connection point of the third and fourth voltage dividing resistors becomes the reference potential, the single power source BTL amplifier is used. Even if it exists, there exists an effect similar to Example 1. FIG.

実施例2では、第1の増幅器221の出力端子と第2の増幅器222の出力端子の電位差を分圧する第3および第4の分圧抵抗23、24の接続点の電位を基準電位Vとして、片電源BTLアンプを用いた電流検出回路を実現した。本実施例は、BTLアンプの正極電源端子と負極電源端子の電位差を所定の比率で分圧する第5および第6の分圧抵抗の接続点の電位を基準電位Vとして取得するように構成した実施例2の変形例である。以下、図3を参照して本実施例の電流検出回路3の構成、および動作について説明する。図3は、本実施例の電流検出回路3の構成を示す回路図である。同図に示すように、本実施例の電流検出回路3は、信号入力部10と、帰還制御部21と、BTLアンプ22と、第1の分圧抵抗13と、第2の分圧抵抗14と、第5の分圧抵抗33と、第6の分圧抵抗34と、負荷15と、負荷電流検出抵抗16と、差分検出部27を含む構成であって、第5の分圧抵抗33と第6の分圧抵抗34以外の構成要件については、実施例2と同じである。 In the second embodiment, the potential at the connection point of the third and fourth voltage dividing resistors 23 and 24 that divides the potential difference between the output terminal of the first amplifier 221 and the output terminal of the second amplifier 222 is set as the reference potential V B. A current detection circuit using a single power supply BTL amplifier was realized. This embodiment is constructed so as to acquire the potential of the fifth and dividing resistor connection point of the sixth dividing the potential difference between the positive power supply terminal and the negative electrode power terminal BTL amplifier at a predetermined ratio as a reference potential V B It is a modification of Example 2. Hereinafter, the configuration and operation of the current detection circuit 3 of this embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram showing a configuration of the current detection circuit 3 of the present embodiment. As shown in the figure, the current detection circuit 3 of this embodiment includes a signal input unit 10, a feedback control unit 21, a BTL amplifier 22, a first voltage dividing resistor 13, and a second voltage dividing resistor 14. A fifth voltage dividing resistor 33, a sixth voltage dividing resistor 34, a load 15, a load current detection resistor 16, and a difference detection unit 27. The components other than the sixth voltage dividing resistor 34 are the same as those in the second embodiment.

図3に示すように、第5の分圧抵抗33と、第6の分圧抵抗34は、第1または第2の増幅器221、222の正極電源端子と負極電源端子の電位差を所定の比率で分圧する。第5の分圧抵抗33と、第6の分圧抵抗34の抵抗比をm:1とする。値mは、第5の分圧抵抗33と第6の分圧抵抗34の接続点の電位が基準電位Vとなるように調整されているものとする。 As shown in FIG. 3, the fifth voltage-dividing resistor 33 and the sixth voltage-dividing resistor 34 have the potential difference between the positive power supply terminal and the negative power supply terminal of the first or second amplifiers 221 and 222 at a predetermined ratio. Divide pressure. The resistance ratio of the fifth voltage dividing resistor 33 and the sixth voltage dividing resistor 34 is m: 1. The value m is assumed to be adjusted so that the potential of the fifth voltage dividing resistors 33 connection point of the sixth voltage dividing resistor 34 becomes the reference potential V B.

本実施例の電流検出回路3によれば、実施例1の構成に加え、第5、第6の分圧抵抗の接続点の電位が基準電位となるように構成したため、片電源BTLアンプを用いた場合であっても、実施例1と同様の効果を奏する。   According to the current detection circuit 3 of the present embodiment, in addition to the configuration of the first embodiment, since the potential at the connection point of the fifth and sixth voltage dividing resistors becomes the reference potential, the single power source BTL amplifier is used. Even if it exists, there exists an effect similar to Example 1. FIG.

実施例1〜3の電流検出回路では、負荷電流検出抵抗16が逆相出力端子側に接続された。実施例4では、負荷電流検出抵抗16が正相出力端子側に接続された電流検出回路を開示する。以下、図4を参照して本実施例の電流検出回路について説明する。図4は、本実施例の電流検出回路4の構成を示す回路図である。同図に示すように、本実施例の電流検出回路4のBTLアンプ12aは、第1の増幅器121aが―nV(t)+0(基準電位V=0)の逆相出力、第2の増幅器122aが、V(t)+0の正相出力となっている。電流検出回路4のそれ以外の構成要件については実施例1と同じである。従って、負荷電流検出抵抗16は、正相出力である第2の増幅器122aと負荷15を介さずに直接接続されていることになる。 In the current detection circuits of Examples 1 to 3, the load current detection resistor 16 was connected to the negative phase output terminal side. The fourth embodiment discloses a current detection circuit in which the load current detection resistor 16 is connected to the positive phase output terminal side. Hereinafter, the current detection circuit of this embodiment will be described with reference to FIG. FIG. 4 is a circuit diagram showing a configuration of the current detection circuit 4 of the present embodiment. As shown in the figure, in the BTL amplifier 12a of the current detection circuit 4 of the present embodiment, the first amplifier 121a has a negative phase output of −nV (t) +0 (reference potential V B = 0), the second amplifier 122a is a positive phase output of V (t) +0. Other structural requirements of the current detection circuit 4 are the same as those in the first embodiment. Therefore, the load current detection resistor 16 is directly connected to the second amplifier 122a which is a positive phase output without passing through the load 15.

この場合、第1、および第2の分圧抵抗13、14の接続点の電位Vは、 In this case, the potential V C at the connection point of the first and second voltage dividing resistors 13 and 14 is

Figure 2017041842
Figure 2017041842

となり、Vは実施例1と同じ値となる。なお負荷電流検出抵抗は、正相側と逆相側の双方に存在してもよい。この場合、それぞれの抵抗値に差があれば負荷の両端の電位差を分圧して得られる電位と基準電位Vの差分から、負荷電流Iを検出することが可能である。 Thus, V C has the same value as in the first embodiment. Note that the load current detection resistor may exist on both the positive phase side and the negative phase side. In this case, it is possible from the difference of potential and a reference potential V B obtained a potential difference across the load if there is a difference in the resistance values divides and detects the load current I L.

本実施例の電流検出回路4によれば、負荷電流検出抵抗16が正相出力端子側に接続された構成で実施例1と同様の効果を奏する。   According to the current detection circuit 4 of this embodiment, the load current detection resistor 16 is connected to the positive phase output terminal side, and the same effect as that of the first embodiment is obtained.

以下、図5を参照して実施例1の差分検出部17を加算回路で構成した実施例5の電流検出回路の構成、および動作について説明する。図5は、本実施例の電流検出回路5の構成を示す回路図である。同図に示すように、本実施例の電流検出回路5は、実施例1の差分検出部17の代わりに、オペアンプ57と、第7の分圧抵抗58と、第8の分圧抵抗59を含む。その他の構成要件については、実施例1と同じである。オペアンプ57の反転入力端子と、第1、第2の分圧抵抗13、14の接続点は、第8の分圧抵抗59により接続される。オペアンプ57の非反転入力端子は、グラウンドに接続される。オペアンプ57の反転入力端子と、出力端子は、第7の分圧抵抗58により接続される。オペアンプ57の出力端子の電圧をVとし、第7の分圧抵抗58の抵抗値をRとし、第8の分圧抵抗59の抵抗値をRとすると、オペアンプ57の反転入力端子に流入する電流は0であることから、オペアンプ57の反転入力端子の電位Vは、以下の式で表される。 Hereinafter, the configuration and operation of the current detection circuit according to the fifth embodiment in which the difference detection unit 17 according to the first embodiment is configured by an addition circuit will be described with reference to FIG. FIG. 5 is a circuit diagram showing the configuration of the current detection circuit 5 of the present embodiment. As shown in the figure, the current detection circuit 5 of the present embodiment includes an operational amplifier 57, a seventh voltage dividing resistor 58, and an eighth voltage dividing resistor 59 instead of the difference detection unit 17 of the first embodiment. Including. Other configuration requirements are the same as those in the first embodiment. The connection point between the inverting input terminal of the operational amplifier 57 and the first and second voltage dividing resistors 13 and 14 is connected by an eighth voltage dividing resistor 59. The non-inverting input terminal of the operational amplifier 57 is connected to the ground. The inverting input terminal and the output terminal of the operational amplifier 57 are connected by a seventh voltage dividing resistor 58. The voltage at the output terminal of the operational amplifier 57 and V O, and the resistance value of the seventh voltage dividing resistors 58 and R Y, the resistance value of the dividing resistor 59 of the eighth and R Z, to the inverting input terminal of the operational amplifier 57 Since the inflowing current is 0, the potential V of the inverting input terminal of the operational amplifier 57 is expressed by the following equation.

Figure 2017041842
Figure 2017041842

電位Vは、イマジナリグラウンドであるから、 Since the potential V is an imaginary ground,

Figure 2017041842
Figure 2017041842

となる。前述同様、 It becomes. As before,

Figure 2017041842
Figure 2017041842

であるから、これを上式に代入して、 Therefore, substituting this into the above formula,

Figure 2017041842
Figure 2017041842

従って、 Therefore,

Figure 2017041842
Figure 2017041842

となり、負荷電流Iに比例した電圧出力を得る。 Next, obtaining a voltage output proportional to the load current I L.

本実施例の電流検出回路5によれば、加算回路を用いて実施例1の電流検出回路1と同様の効果を奏する。なお、上述したRがほとんど0で、第8の分圧抵抗59を無視できる場合であっても同様の効果を奏する。 According to the current detection circuit 5 of the present embodiment, an effect similar to that of the current detection circuit 1 of the first embodiment is obtained using the adder circuit. The same effect can be obtained even when the above-described RZ is almost 0 and the eighth voltage dividing resistor 59 can be ignored.

以下、図6を参照して実施例2、3に開示した片電源BTLアンプを用いた電流検出回路の変形例である実施例6の電流検出回路の構成、および動作について説明する。図6は、本実施例の電流検出回路6の構成を示す回路図である。実施例2、3において基準電位Vを取り出すための構成であった第3〜第6の分圧抵抗23〜34の代わりに、本実施例では基準電位Vを供給する別電源である電源69を含むことを特徴とする。同図に示すように、差分検出部27は、第1、第2の分圧抵抗13、14の接続点と、電源69が供給する基準電位Vの差分に基づいて、負荷15に流れる電流Iを検出する。 Hereinafter, the configuration and operation of the current detection circuit according to the sixth embodiment, which is a modification of the current detection circuit using the single power supply BTL amplifier disclosed in the second and third embodiments, will be described with reference to FIG. FIG. 6 is a circuit diagram showing the configuration of the current detection circuit 6 of this embodiment. In this embodiment, instead of the third to sixth voltage dividing resistors 23 to 34 that are configured to take out the reference potential V B in the second and third embodiments, a power source that is another power source that supplies the reference potential V B is used. 69. As shown in the figure, the difference detection unit 27, first, a connection point of the second voltage dividing resistors 13 and 14, power supply 69 based on the difference between the reference potential V B supplies a current flowing through the load 15 IL is detected.

本実施例の電流検出回路6によれば、別電源である電源69を用いて実施例2や実施例3と同様に片電源BTLを用いた電流検出回路を実現することができる。   According to the current detection circuit 6 of the present embodiment, a current detection circuit using a single power source BTL can be realized using the power source 69 which is a separate power source, as in the second and third embodiments.

1 電流検出回路
10 信号入力部
11 帰還制御部
12 BTLアンプ
121 第1の増幅器
122 第2の増幅器
13 第1の分圧抵抗
14 第2の分圧抵抗
15 負荷
16 負荷電流検出抵抗
17 差分検出部
2 電流検出回路
21 帰還制御部
22 BTLアンプ
221 第1の増幅器
222 第2の増幅器
23 第3の分圧抵抗
24 第4の分圧抵抗
27 差分検出部
3 電流検出回路
33 第5の分圧抵抗
34 第6の分圧抵抗
4 電流検出回路
12a BTLアンプ
121a 第1の増幅器
122a 第2の増幅器
5 電流検出回路
57 オペアンプ
58 第7の分圧抵抗
59 第8の分圧抵抗
6 電流検出回路
69 電源
7 電流検出回路
70 電位差検出回路
701 第1抵抗
702 第2抵抗
703 第3抵抗
704 第4抵抗
705 オペアンプ
DESCRIPTION OF SYMBOLS 1 Current detection circuit 10 Signal input part 11 Feedback control part 12 BTL amplifier 121 1st amplifier 122 2nd amplifier 13 1st voltage dividing resistor 14 2nd voltage dividing resistor 15 Load 16 Load current detection resistance 17 Difference detection part 2 Current detection circuit 21 Feedback control unit 22 BTL amplifier 221 1st amplifier 222 2nd amplifier 23 3rd voltage dividing resistor 24 4th voltage dividing resistor 27 Difference detection unit 3 Current detection circuit 33 5th voltage dividing resistor 34 sixth voltage dividing resistor 4 current detection circuit 12a BTL amplifier 121a first amplifier 122a second amplifier 5 current detection circuit 57 operational amplifier 58 seventh voltage dividing resistor 59 eighth voltage dividing resistor 6 current detection circuit 69 power supply 7 Current detection circuit 70 Potential difference detection circuit 701 First resistor 702 Second resistor 703 Third resistor 704 Fourth resistor 705 Operational amplifier

Claims (6)

所定の信号を出力する第1の増幅器と、
前記第1の増幅器の出力信号と逆相の信号を出力する第2の増幅器と、
前記第1の増幅器の出力端子と前記第2の増幅器の出力端子を接続する負荷の両端の電位差を分圧する第1、および第2の分圧抵抗であって、前記第1、および第2の分圧抵抗の接続点において、前記第1の増幅器の出力信号の振幅と、前記第2の増幅器の出力信号の振幅とが打ち消し合うように、各抵抗値が定められた第1、および第2の分圧抵抗と、
前記負荷に直列に接続された負荷電流検出抵抗と、
前記第1、および第2の分圧抵抗の接続点の電位と所定の電位である基準電位の電位差と、前記第1、および第2の分圧抵抗の抵抗値の比と、前記負荷電流検出抵抗の抵抗値に基づいて、前記負荷に流れる電流を検出する差分検出部と、
を含む電流検出回路。
A first amplifier that outputs a predetermined signal;
A second amplifier for outputting a signal having a phase opposite to that of the output signal of the first amplifier;
First and second voltage dividing resistors for dividing a potential difference between both ends of a load connecting an output terminal of the first amplifier and an output terminal of the second amplifier, wherein the first and second voltage dividing resistors The first and second resistance values are determined such that the amplitude of the output signal of the first amplifier and the amplitude of the output signal of the second amplifier cancel each other at the connection point of the voltage dividing resistor. And the partial pressure resistance of
A load current detection resistor connected in series to the load;
The potential difference between the potential at the connection point of the first and second voltage dividing resistors and a reference potential which is a predetermined potential, the ratio of the resistance values of the first and second voltage dividing resistors, and the load current detection A difference detection unit that detects a current flowing through the load based on a resistance value of the resistor;
Including current detection circuit.
nを任意の正の数とし、
所定の基準電位の信号を出力する第1の増幅器と、
前記所定の基準電位の信号であって、前記第1の増幅器の出力信号と逆相かつ前記第1の増幅器の信号との振幅比がn:1となる信号を出力する第2の増幅器と、
前記第1の増幅器の出力端子と前記第2の増幅器の出力端子を接続する負荷の両端の電位差をn:1に分圧する第1、および第2の分圧抵抗と、
前記負荷に直列に接続された負荷電流検出抵抗と、
前記第1、および第2の分圧抵抗の接続点の電位と前記基準電位の電位差と、前記nと、前記負荷電流検出抵抗の抵抗値に基づいて、前記負荷に流れる電流を検出する差分検出部と、
を含む電流検出回路。
Let n be any positive number,
A first amplifier that outputs a signal having a predetermined reference potential;
A second amplifier that outputs a signal having the predetermined reference potential, the signal having a phase opposite to that of the output signal of the first amplifier and an amplitude ratio of n: 1 with respect to the signal of the first amplifier;
First and second voltage dividing resistors for dividing a potential difference between both ends of a load connecting the output terminal of the first amplifier and the output terminal of the second amplifier to n: 1;
A load current detection resistor connected in series to the load;
Difference detection for detecting a current flowing through the load based on a potential difference between a connection point of the first and second voltage dividing resistors and the reference potential, the n, and a resistance value of the load current detection resistor. And
Including current detection circuit.
請求項1または2に記載の電流検出回路であって、
前記基準電位をグラウンドとした
電流検出回路。
The current detection circuit according to claim 1 or 2,
A current detection circuit using the reference potential as a ground.
請求項1または2に記載の電流検出回路であって、
前記第1の増幅器の出力端子と前記第2の増幅器の出力端子の電位差を所定の比率で分圧する第3および第4の分圧抵抗を含み、
前記基準電位を前記第3および第4の分圧抵抗の接続点の電位とした
電流検出回路。
The current detection circuit according to claim 1 or 2,
Including third and fourth voltage dividing resistors for dividing the potential difference between the output terminal of the first amplifier and the output terminal of the second amplifier at a predetermined ratio;
A current detection circuit in which the reference potential is a potential at a connection point of the third and fourth voltage dividing resistors.
請求項1または2に記載の電流検出回路であって、
前記第1または第2の増幅器の正極電源端子と負極電源端子の電位差を所定の比率で分圧する第5および第6の分圧抵抗を含み、
前記基準電位を前記第5および第6の分圧抵抗の接続点の電位とした
電流検出回路。
The current detection circuit according to claim 1 or 2,
Including fifth and sixth voltage dividing resistors for dividing the potential difference between the positive power supply terminal and the negative power supply terminal of the first or second amplifier at a predetermined ratio;
A current detection circuit in which the reference potential is a potential at a connection point of the fifth and sixth voltage dividing resistors.
請求項1または2に記載の電流検出回路であって、
前記基準電位を供給する電源を含む
電流検出回路。
The current detection circuit according to claim 1 or 2,
A current detection circuit including a power supply for supplying the reference potential;
JP2015163937A 2015-08-21 2015-08-21 Current detection circuit Active JP6646380B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015163937A JP6646380B2 (en) 2015-08-21 2015-08-21 Current detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015163937A JP6646380B2 (en) 2015-08-21 2015-08-21 Current detection circuit

Publications (2)

Publication Number Publication Date
JP2017041842A true JP2017041842A (en) 2017-02-23
JP6646380B2 JP6646380B2 (en) 2020-02-14

Family

ID=58203697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015163937A Active JP6646380B2 (en) 2015-08-21 2015-08-21 Current detection circuit

Country Status (1)

Country Link
JP (1) JP6646380B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108195405A (en) * 2018-03-06 2018-06-22 中国科学技术大学 Microchannel plate ion detection circuit
CN110108924A (en) * 2019-05-30 2019-08-09 上海良信电器股份有限公司 DC current measuring circuit, method and the breaker of breaker
CN116094312A (en) * 2023-04-10 2023-05-09 荣湃半导体(上海)有限公司 Input voltage reduction circuit for IGBT driving chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003514426A (en) * 1999-11-09 2003-04-15 ザット コーポレーション Improved floating balanced output circuit
JP2007324991A (en) * 2006-06-01 2007-12-13 Victor Co Of Japan Ltd Current detection circuit
JP2013150182A (en) * 2012-01-20 2013-08-01 Renesas Electronics Corp Output circuit
US20130265035A1 (en) * 2012-04-10 2013-10-10 Federico Mazzarella System and method for current measurement in the presence of high common mode voltages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003514426A (en) * 1999-11-09 2003-04-15 ザット コーポレーション Improved floating balanced output circuit
JP2007324991A (en) * 2006-06-01 2007-12-13 Victor Co Of Japan Ltd Current detection circuit
JP2013150182A (en) * 2012-01-20 2013-08-01 Renesas Electronics Corp Output circuit
US20130265035A1 (en) * 2012-04-10 2013-10-10 Federico Mazzarella System and method for current measurement in the presence of high common mode voltages

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108195405A (en) * 2018-03-06 2018-06-22 中国科学技术大学 Microchannel plate ion detection circuit
CN110108924A (en) * 2019-05-30 2019-08-09 上海良信电器股份有限公司 DC current measuring circuit, method and the breaker of breaker
CN116094312A (en) * 2023-04-10 2023-05-09 荣湃半导体(上海)有限公司 Input voltage reduction circuit for IGBT driving chip

Also Published As

Publication number Publication date
JP6646380B2 (en) 2020-02-14

Similar Documents

Publication Publication Date Title
US7633317B2 (en) High-side current sense circuit with common-mode voltage reduction
JP2013123083A (en) Auto-zero amplifier and feedback amplification circuit using the amplifier
JP2010200216A (en) Class-d amplifier
JP6646380B2 (en) Current detection circuit
US7446554B2 (en) Direct current measuring apparatus and limiting circuit
CN109782053B (en) Power supply device
JP2008009968A (en) Voltage generating apparatus, current generating apparatus, and test apparatus
JP5057950B2 (en) Insulation resistance tester
JP2007324991A (en) Current detection circuit
JP5717427B2 (en) Resistance measuring device
JP6574668B2 (en) Impedance measurement circuit
JP2011221778A (en) Ac constant current output device
RU2627123C1 (en) Inverting scaling amplifier with frequency error compensation
JP4607075B2 (en) DC motor current detection device and galvano scanner system
JP5190103B2 (en) Voltage generator, current generator
JP2016090379A (en) measuring device
JP7337723B2 (en) Current supply circuit and resistance measuring device
US8981816B2 (en) Multi-input voltage-to-frequency conversion circuit
KR102426279B1 (en) Drive circuit
JP2015125133A (en) Differential output current detection device and differential output current detection method
JP5559905B1 (en) Electronic circuit
JP2006170797A (en) Unbalance capacity detecting device, sensor unbalance capacity detecting method, and transducer used therefor
JP5839387B2 (en) Magnetic field detector
JP2007212192A (en) Current measuring circuit and testing apparatus using same
WO2012053992A4 (en) Current source with active common mode rejection

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180702

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190311

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190402

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190513

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20191001

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191023

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200110

R150 Certificate of patent or registration of utility model

Ref document number: 6646380

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250