JP2015046749A5 - - Google Patents

Description

In FIG. 1, a data processing circuit 1 is composed of, for example, a one-chip integrated circuit (IC), and includes a serial transfer data generation unit 2, a parallel transfer clock generation unit 3, a PWM modulation data generation unit 4, and a selector 5. And a serializer 6. Here, predetermined serialized data (serial data to be serially transferred (hereinafter also referred to as serial transfer data or serial data) ) ser_data is input to the serial transfer data generation unit 2. The serial transfer data generation unit performs predetermined conversion processing such as (parallel data generating unit) 2 serialized data ser_data a predetermined parallel data data1, for example coding and outputs to the selector 5. Further, the parallel transfer clock generation unit (parallel data generation unit) 3 receives the oscillation period setting value data (clock period setting value) period_data and the skew adjustment value data skew_data of the clock for parallel transfer. The parallel transfer clock generator 3 generates a parallel transfer clock based on the input data and outputs the parallel transfer clock to the selector 5. Further, the PWM modulation data generation unit 4 receives the PWM modulation data duty setting input signal pwm_in. The PWM modulation data generation unit 4 performs pulse width modulation on a predetermined carrier wave pulse signal according to the input signal pwm_in, and outputs the parallel data data3 after the pulse width modulation to the selector 5. Next, the selector 5 selects one of the data data 1 to 3 based on the selection signal sel and outputs the selected data to the serializer 6. Here, the data data1 to 3 and the data data_in each have a predetermined same bit width.

Claims (11)

And the parallel data generating unit for generating a predetermined parallel data by performing a predetermined signal conversion on serial data to be input,
A pulse width modulation data generating unit that generates a parallel data after pulse width modulation by pulse width modulating a predetermined carrier pulse signal according to an input signal;
Based on the selection signal input, a parallel data output from the parallel data generating unit, a selector for selecting and outputting one of the parallel data output from said pulse width modulation data generating unit,
A serializer that converts the parallel data output from the selector into a serial output signal and outputs the serial output signal;
The data processing circuit, wherein the pulse width modulation data generation unit generates parallel data for setting a duty ratio in the serial output signal based on input pulse width modulation data. The parallel data generation unit includes a parallel transfer clock generation unit that generates parallel data of a parallel transfer clock based on period setting value data and a skew adjustment value of the parallel transfer clock. The data processing circuit described. The parallel data generating unit, the data processing circuit according to claim 1, wherein the conversion of serial data of 8-bit width parallel data 10 bits wide. The parallel transfer clock generation unit oscillates in a cycle set by the clock cycle setting value in the serial output signal, and generates parallel data for performing skew adjustment based on the skew adjustment value. The data processing circuit according to claim 2 . The serializer includes a shift register circuit including a plurality of columns of shift registers, and each serial output signal output from the plurality of columns of shift registers is divided from a first clock signal synchronized with input parallel data. the data processing circuit according to any one of claims 1-4, characterized in that the synchronized second clock signal of a multi-phase was. The pulse width modulation data generation unit generates parallel data after pulse width modulation by modulating the pulse width of the carrier pulse signal based on input reference voltage data. The data processing circuit according to any one of 5 . The pulse width modulation data generation unit generates parallel data after pulse width modulation by modulating a pulse width of the carrier pulse signal based on an input rotational speed of a target motor. Item 6. The data processing circuit according to any one of Items 1 to 5 . The pulse width modulation data generation unit generates parallel data after pulse width modulation by modulating a pulse width of the carrier wave pulse signal based on an input target motor rotation angle. The data processing circuit according to any one of 1 to 5 . The pulse width modulation data generating unit, by modulating the pulse width of the carrier pulse signal based on a target illuminance inputted, claims 1-5, characterized in that to generate the parallel data after pulse width modulation A data processing circuit according to any one of the above.   6. The pulse width modulation data generation unit generates parallel data after pulse width modulation by modulating a pulse width of the carrier pulse signal based on an input target temperature. A data processing circuit according to any one of the above. A control device for controlling a controlled device,
A data processing circuit according to any one of claims 5 to 10 ,
A control apparatus that controls the controlled apparatus using parallel data after pulse width modulation output from the data processing circuit.