KR100219021B1 - Third order sigma delta oversampled a/d converter network with low component sensitivity - Google Patents

Abstract

Low Sample Sensitivity Oversampled Three-Dimensional Sigma Delta Analog-to-Digital Converter Network Interpolation An improved modulator network for oversampled (sigma-delta) analog-to-digital converters introduces an error between the digital output signal and the analog input signal. And a one-dimensional modulator for single integration of the error between the digital output signal and the analog signal output from the two-dimensional modulator. The modulators supply their output signals to the digital error cancellation circuit, which suppresses the quantization noise generated in the two-dimensional modulator at the discretion supplied to the decimation filter. The network is the resolution, component mismatch, and nonlinearity of this type of analog-to-digital converter. It significantly reduces its sensitivity to practical non-idealities that normally limit finite gain, select time, and signal dynamic range.

Description

Oversampled Third-order Sigma-Delta Analog-to-Digital Converter Network with Low Component Sensitivity

1 is a block circuit diagram of a conventional sigma-delta analogue-to-digital converter.

2A, 2B, 2D, and 2E show representative power spectra associated with the operation of the analog-to-digital converter of FIG. 1, and FIG. 2C shows representative filter characteristics of the decimation filter of FIG.

3 is a block diagram illustrating a tertiary sigma-delta analogue-to-digital converter network in accordance with the present invention.

4 is a functional block diagram illustrating one variant of the third diagram form for a tertiary sigma-delta analogue-to-digital converter network embodying the present invention.

5 is a functional block diagram illustrating a particular embodiment of a tertiary sigma-delta analogue-to-digital converter network in accordance with the present invention.

FIG. 6 is a circuit block diagram of a sampled data single-ended switch capacitor embodiment of the tertiary sigma-delta analog-to-digital converter network of FIG.

FIG. 7 is a circuit block diagram of a sampled data differential switch capacitor embodiment of the tertiary sigma-delta analog-digital converter network of FIG.

8 is a waveform diagram of a clock signal used in the circuit of FIG.

9 is a circuit block diagram of a decimation filter that can be used in the three-dimensional sigma delta analog-to-digital converter network of FIGS.

FIG. 10 is a circuit block diagram illustrating a third order sigma delta analogue-to-digital converter network in accordance with the present invention as another form of the FIG.

FIG. 11 is a functional block diagram showing one modification of the form of FIG. 10 of a three-dimensional sigma delta analogue-to-digital converter network embodying the present invention.

12 is a circuit block diagram of a decimation filter that can be used in the three-dimensional sigma delta analog-to-digital converter network of FIGS. 10 and 11.

FIG. 13 is a circuit block diagram illustrating a three-dimensional sigma delta analogue-to-digital converter network according to the present invention in another form in the form of FIG. 3 and FIG.

FIG. 14 is a functional block diagram illustrating one variation of the form of FIG. 13 for a three-dimensional sigma delta analog-to-digital converter network embodying the present invention.

FIG. 15 is a circuit block diagram of a decimation filter that can be used in the three-dimensional sigma delta analogue-to-digital converter network of FIGS. 13 and 14;

* Explanation of symbols for main parts of the drawings

20: secondary modulator 30: primary modulator

22, 24, 26: integrator 23: amplifier

26, 28: A / D converter 28, 40: D / A converter

46: digital double differentiator 60, 80: delay register

74: multiplier 78: differential

84, 86, 88, 90: amplifier

The present invention relates to a tertiary sigma-delta analogue-to-digital converter, and more particularly to an oversampled tertiary sigma-delta analogue-to-digital converter network with low component mismatch sensitivity and limited amplifier gain.

With oversampled interpolation (or sigma delta) modulation and digital low pass filtering and decimation, high resolution analog-to-digital (A / D) signal conversion can be achieved with low resolution components. Oversampling refers to the operation of a modulator operating at a rate that is several times the signal Nyquist rate, and decimation refers to enjoying the clock rate at three Nyquist rates.

Sigma delta modulators (also called 'delta sigma modulators') have been used for a considerable period of time in analog-to-digital converters. The general content thereof can be obtained from the following technical literature, which is included as part of the present specification.

A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters, J.C. Candy, IEEE Transactions of Communications, Vol. COM-22, No. 3, pp. 298-305, March 1974.

2) Using Triangularly `Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator, J. C. Candy et al, IEEE Transactions on Communications, Vol. C0M-24, No. 11, 1268-1275, November 1976.

3) '' A Use of Double Integration in Sigma Delta Modulation, J.C. Candy, IEEE Transactions on Communications, Vol. COM-33, No. 3, pp. 249-258, March 1985.

In order to achieve higher resolution when the sampling rate is constant, efforts to develop multiple orders of sigma delta modulation have been heavily invested in the design of oversampled analog-to-digital converters. In this specification, order means the order of the sigma delta modulator, which is directly determined by how often an error occurs over time between the input signal and the output signal of the sigma delta modulator, whereas the sigma delta of the multi-stage The order of the sigma delta modulator in the A / D converter is directly determined by how much the input signal of the stage is integrated over time to reach the output connection 4 of the stage.

In this type of analog-to-digital converter, resolution is mainly dependent on two factors: 1) the ratio of the modulator clock to the Nyquist rate (also called the 'oversampling rate'), and 2) the order of the modulator. Controlled. The order here is similar to the order of the frequency selective filter and represents the relative degree of spectral shape provided by the modulator. High order analog-to-digital converter network as used herein refers to a tertiary or higher order network.

In filters, the higher the order, the higher the selectivity, but the more complex the hardware. Recently implemented high resolution oversampled analog-to-digital converters have used both large oversampling ratios and high modulator orders in consideration of the two factors. However, due to practical application problems, the degree of oversampling rate and modulator order can be limited. For example, for a given modulator clock rate, since the oversampling rate is inversely proportional to the Nyquist rate after decimation, the oversampling rate cannot be arbitrarily increased without sacrificing the conversion rate. Another limitation concerns the modulator order. Increasing the order to two or more using a single quantizer prevents practical application because stability is ensured only under certain conditions.

Another method is to use a low-order modulator connected in series to provide a high-order noise shape to ensure stable operation. However, the matching of modulators in this structure is a very important variable, so the overall accuracy of the transducer is determined by the level of mismatch. The need for adjacent component matching and high operational amplifier (or 0P amplifier) gains means that the circuit can only be manufactured in low yields and requires trimming, thus high production costs.

Early work in the art has been directed to the implementation of primary and secondary modulators because of stability issues associated with three or more orders. Proc. IEEE 1986 Int., Published in February 1986 by T. Hayashi et al. The multi-stage delta sigma modulator without the dual integrator loop described in Solid-State Circuits Conf., Pp 182-183 describes how secondary performance can be achieved using a series connection of two primary stages. The quantization error of the first stage is supplied to the second stage after the digital derivative to include a replica of the output signal of the second stage and the quantization noise of the frequency shape. Finally, from the output signal of the first stage, the second stage Subtracting the output signal of the signal yields a signal containing only the quantization noise of the second stage with a secondary noise shape. However, this method requires a perfect match of the characteristics of the two primary modulators and the high OP amplifier gain.

The application of the Hayashi proposed method to a tertiary analog-to-digital converter network using a triple serial connection of a primary modulator is described in IEEE J. Solid-State Circuits, published in December 1987 by Y. Matsuya et al. A 16-bit oversampling A / D conversion technique using triple integral noise shapes is described in SC-22, No. 6, pages 921-929. However, this method requires more complete component matching and also requires a high 0P amplifier gain to achieve the theoretically obtainable resolution.

A slightly different method is a 13-bit ISDN-B and ADC using a two-stage third-order noise figure from Proc. 1988 Custom Integrated Circuit Conf., 21.2.3 to 4, published in June 1988 by L. Lorgo and MA Copeland. There is a description, in which the secondary modulator is connected in series with the primary modulator to achieve the third order noise shape. This method has the advantage of somewhat reducing component matching requirements from other embodiments.

The improved third-order sigma-delta analogue-to-digital converter developed by the present inventors achieves third-order noise shaping with reduced sensitivity to component mismatch, finite amplifier gain, and other non-ideal circuit properties (called non-ideality). do. An improved structure of a tertiary sigma delta analogue-to-digital converter that can be implemented as a sampled dataswitch capacitor circuit has been sought by the inventors. We also use a finite gain amplifier so that the resolution of the A / D converter approaching the theoretical limit and using a modulator network structure with relatively low sensitivity to general circuit non-ideality, the third-order sigma delta analogue- We have sought to provide third-order quantization noise shapes for digital converters.

The new third-order sigma-delta analogue-to-digital converter network developed by the present inventors is a non-ideal in practical application that limits the resolution of conventional third-order sigma-delta analogue-to-digital converter networks, namely component mismatch, amplifier nonlinearity, finite gain. Therefore, sensitivity to excessive stabilization time and limited signal dynamic range is greatly reduced. Simulation with non-ideality shows that 16-bit resolution at 80 KHI conversion can be achieved by a new A / D converter network operating at oversampling of 64. This result can be achieved despite only 2% component matching and as low as 1000 of OP amp gain. This result, despite the minimum circuit specification, means that low-cost, high-productivity A / D converter networks are now feasible. MOS, CMOS, BiMOS, GaAs, or bipolar integrated circuit technology can be used to implement a complete monolithic A / D converter network without disjoint components other than decoupling capacitors. Since the new A / D converter network is of moderate complexity, it is possible to fully implement a digital signal processing chip having a high resolution multichannel analog interface.

Computed tomography (CT) scanners use a fan beam energy source and a central ray projected through a specific point in space near the center of the object being scanned, the energy source of which Move around a circular trajectory centered at a specific point. The arcuate strip of the detector element is spaced from the energy source, on the other side of the particular point, on the opposite side of the energy source and tracks the rotation of the energy source around the particular point in space. Positioned to absorb a portion of the radiant energy in each adjacent segment of the fan beam, and the remaining radiant energy or light sum in each segment of the fan beam is measured by each detector on the arcuate detector strip. The detector response for each successive increment of rotation of the energy source and the arcuate detector strip on the opposite side constitute a separate view of the object being scanned. The detector response in the continuous view is stored in the memory because the processing of the response is performed after the scan is completed rather than in real time. As such, the detector response from each view during subsequent processing is preweighted by a carefully formulated finite impulse filter kernel before being projected back into the image space to produce the gray scale value of the pixel (or pixel). ) And prefiltered. During each view, the sum of the rays passing through each pixel center is weighted and summed to produce gray scale values of the pixels by back projection. That is, since each ray sum represents the sum of the edges absorbed from the bundle of rays forming a segment of the fan beam in its transverse direction through the continuous portion of the object including the portion where the pixel is located, the segment of the fan beam The magnitude of the energy defect due to any one of the pixels crossed by can be found by performing an autocorrelationprocedure including all the sums of rays for the bundle of rays passing through the pixel. The autocorrelation procedure suppresses shading caused by the pixels before and after the major pixels of the ray sum, which is the basis for producing tomographic images by computed tomography. In the further combining of the sum of the rays involved in the execution of the autocorrelation procedure, each sum of the rays must be weighted in consideration of the divergence of the fan beam before the packet of rays associated with that pixel passes through the pixel.

Although Fourier inversion for computed tomography has an inherent speed advantage over reverse projection reconstruction, it is considered inappropriate for use in fan beam scanners due to excessive sensitivity to noise. The convolution and backprojection reconstruction methods are suitable for viewing pipe linings and produce images with little undesirable artifacts from processing. G. As shown in Computer Biologic Medicine, October 6, 1976, Vol. 6, pages 259-271. T. Herman, A. V. Lakshminarrayan, A. Naparstek, Convolution Reconstruction Technique for Divergent Beams, describe the above. It is also described in B. K. Gilbert, S., pp. 98-115 of IEEE Transactionson Biomedical Engineering, Volume 2, BME-28, published in February 1981. K. Kenue, R. A. Robb, A. Chu, A. H. Lent, E. E. Swartxlander's article Rapid Execution of Fan Beam Image Reconstruction Algorithms Using Efficient Computational Techniques and Special Purpose Processors.

The strip of detector elements comprises hundreds of linearly arranged scintillators and hundreds of linearly arranged photodiodes disposed behind them. The scintillator converts the X-ray image into an optical image, and the photodiode converts the photons of the device of the optical image into electric charges. The photodiode is provided with a trans-resistance amplifier that provides a low input impedance for sensing each preamplifier, for example port diode current, and a low output impedance for driving the subsequent circuit. In a conventional CT system, the photodiode-preamplifier combination is distributed among the subgroups of the entire group of combinations, and in each subgroup the analog output voltage from the preamplifier is at the input of the shared analog-to-digital (A / D) converter. Time division multiplexed.

In practice, it is difficult to combine the A / D converter conversion characteristics of the various subgroups because the resolution of a very large number of bits (ie 16 to 20 bits) in the converter output signal is required to perform the reverse projection calculation. It turned out. The linearity of the conversion characteristics of the A / D converter is made as good as possible, but when the photodiodes of each subgroup of the photodiode-preamplifier combination are adjacent to each other in the strip of the detector element, the final tomography is due to the difference in the conversion characteristics. Banding artifacts appear in the picture. The banding artifacts appear as intensity changes with significantly lower spatial frequencies, so they appear unpleasant to the final observer of the final tomographic image. In order to reduce the visibility of the artifacts due to the difference in A / D converter conversion characteristics, the position of the detector element of the photodiode was actually changed in each subgroup of the photodiode-preamplifier combination. Thus, in the tomography image, the low spatial frequency component of the artifact may be lowered, but in the tomography image, the high spatial frequency component of the artifact is increased. It is possible to perform spatial low pass filtering by removing only the spatial frequency detail of the artifact. Changing the connection of the photodiode-preamplifier combination to the time-division multiplexed A / D converter causes undesirable electrical internal connections among the elements of the CT system and uses time-division multiplexing over a high-speed digital bus. Complicate the transmission.

Changing the connection of the photodiode-preamplifier combination to the time division multiplexed A / D converter allows the preamplifier and A / D converters to be as physically as close as possible to the photodiode in order to minimize pick up of external electrical signals as noise. To interfere. A / D converters and time division multiplexed preamplifiers are normally constructed in the form of monolithic integrated circuits (ICs), and extension cables are needed to connect the photodiodes to the IC followed by a photodiode modification. Since the output impedance level of the photodiode is about 30 Hz, pickup of external electrical signals on the cable can be easily expected.

Another way to reduce the possibility of low spatial frequency components of artifacts due to differences in A / D converter conversion characteristics is to provide their own A / D converters for each of the photodiode-preamplifier combinations. In fact, this eliminates the autocorrelation of the A / D converter conversion characteristics that cause the occurrence of banding artifacts. It also removes the analog range multiplexing and the dynamic range limitations that arise from the analog multiplexing. Providing its own A / D converter on each of the photodiode-preamp combinations provides sufficient linearity and the number of bits available to provide a tomographic picture with acceptable low artifacts due to differences in A / D converter conversion characteristics. A / D converters have a problem in that A / D converters are simple and inexpensive with sufficient configurations to be used in hundreds of units.

The simplicity of the sigma-delta A / D converter was one factor that led the inventor to consider using one next to each of the photodiode-preamplifier combinations of the CT scanner in an effort to avoid the occurrence of banding artifacts. Sigma-delta A / D converters that follow a single bit analog-to-digital converter in the feedback loop of a sigma delta modulator may also have extremely linear conversion characteristics. The inventors also provide decimation of the sigma delta A / D converter by providing carefully formulated finite impulse filtering needed to suppress high frequency preamplifier noise before the detector response is back projected into the picture space to produce a pixel or gray scale value of the pixel. We have explored the possibility that the simulation filter can perform a dual function. A sample data FIR filter using a tap digital delay line clocked at an oversampling rate, or a functionally equivalent structure, automatically adjusts its bandwidth to accommodate different oversampling rates.

The problem encountered when time-division multiplexing the digital outputs from multiple sigma delta A / D converters that digitize the photodiode response is a finite impulse response (FIR) decimation within the time allotted to each photodiode to detect a portion of the optical image. It is necessary to process enough input signal samples at the oversample speed so that the filter has enough input signal samples to span the filter kernel, i.e. enough input samples to which all FIR filter tap weights are weighted. This becomes more difficult when the decimation filter of a sigma delta A / D transducer provides carefully formulated finite impulse filtering needed to suppress high frequency preamplifier noise prior to the detector response. It has been found that the oversampling rate may be excessive when trying to use a single one-dimensional sigma delta modulator for each A / D converter at a bit of CT scanner speed and detector resolution. The oversampled third-order sigma delta converter described herein is particularly suitable for use after each photo diode-preamplifier combination in a CT scanner to avoid the occurrence of banding artifacts.

[Summary of invention]

An oversampled interpolated (sigma delta) analog-to-digital converter network embodying the present invention comprises a secondary modulator that receives an analog signal to be converted as its input signal and responds to a digital output signal of the analog-to-digital conversion. The digital converter is an undesirable quantization noise component of the digital output signal of the secondary modulator, which produces a quantization error that appears in the form of a double differential, and subtracts 2 from the quantization error generated by the analog-digital converter in the secondary modulator. A primary modulator that receives the digital output signal of the dimensional modulator and responds to the digital output signal of the analog-to-digital converter, and a primary modulator to obtain a digital output signal that depicts the analog signal received as an input signal by the secondary modulator. Combine the digital output signal of the secondary modulator, The quantized noise components are few and a digital error cancellation circuit.

EXAMPLE

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a conventional sigma delta analogue-to-digital converter with an oversampled interpolation (sigma delta) modulator 10 connected to a low pass decimation filter 12 and the filter l2 connected to a sampling rate compressor 14. An example is shown. The role of modulator 10 is to spectrally shape the quantization noise of the low resolution analog-to-digital converter so that the quantization noise is concentrated at high frequencies. The input signal x (n) to the modulator 100 is a sine wave whose frequency is Fs and is sampled by the modulator 10 at a sampling rate F _M. Subsequent low-pass filtering and decimation can be used to reduce most of the quantization noise, with reduced conversion rate F _M / N where N is the oversampling rate, or input clock (or sample) rate (F _M ). Is the ratio of the output clock speed (F) to the high resolution digital output signals.

In FIG. 1, the following functions are provided: input signal x (n), modulator output signal u (n), filter output signal w (n), A / D converter output signal y (n) and filter impulse response characteristic h (n ) Is shown. The frequency spectra corresponding to this signal are X (f), U (f), W (f), Y (f), and filter characteristics X (f), respectively. 2b, 2d, 2e and 2c, respectively, which represent the circuit states of FIG. 1 at positions (a), (b), (d), (e) and (c), respectively. . These frequency spectra represent the noise shape provided by the modulator 10 and the high frequency noise rejection provided by the low pass decimation filter 12 prior to the sampling rate conversion performed by the compressor 14.

A simple block diagram of a tertiary sigma delta analogue-to-digital converter network to which the present invention is applied is shown in FIG. 3 and includes a secondary modulator 20 connected to the primary modulator 30. The secondary modulator 20 includes a pair of serially connected integrators 22 and 24, an analog-to-digital converter 26 connected to the output of the integrator 24, and an analog-to-digital converter through a subtractive summing unit 32. While connected to the first feedback loop between the output of 26 and the input of the integrator 22, an analog-to-digital converter 26 is provided via an amplifier 23 having gain 2 and a subtractive synthesis unit 34 connected in series therewith. Digital-to-analog (D / A) converter 28 coupled to the second feedback loop between the output of < RTI ID = 0.0 > input < / RTI >

Secondary modulator 20 responds to analog input signal x (t) and has a quantized noise signal d ₂ Q shaped at low frequency ω < π / T (where T is the sample age period and T = 1 / FM). _In addition to generating ₁ / dt ₂ , it generates a digital output signal of approximately x + d ₂ Q ₁ / dt ₂ that includes component x, which is a digital representation of the ideal analog input signal. The noise component Q ₁ from the secondary modulator 20 is double differentiated by the two integrator loops and becomes high frequency. The signal applied to the analog-to-digital converter 26 is the analog signal x + d ₂ Q ₁ / dt ₂ -Q ₁ which is equal to the digital output signal x + d ₂ Q ₁ / dt ₂ minus the quantization noise Q ₁ , 1 Is applied to the difference modulator 30.

The primary modulator 30 includes a single integrator 36 connected to the analog to digital converter 38. The analog-to-digital converter 40 is coupled to a feedback loop between the output of the analog-to-digital converter 38 and the input of the integrator 36 via a subtractive summing unit 42. The digital-to-analog converter 40 is coupled to a feedback loop between the output of the analog-to-digital converter 38 and the input of the integrator 36 via a subtractive summing unit 42. Quantization noise Q2 generated during analog-to-digital conversion by analog-to-digital converter 38 in primary modulator 30 is differentiated by a single integrator loop and is higher in the output signal from primary modulator 3o. Is raised to frequency. Primary modulator 30, the low-frequency ω« π / T in, the additional differential quantization noise signal dQ ₂ / dt is approximately equal to the added signal exact copy of the input signal _{X + d 2 Q 1 / dt} 2 - Q 1 Generates a digital output signal of + dQ ₂ / dt.

The digital subtractor 44 is connected to the output of the secondary modulator 20 and the output of the primary modulator 30 to determine the difference between the digital output signals of the modulators 20, 30. The digital double differentiator 46 is connected to the output of the digital subtractor 44 to differentiate the digital difference signal from the digital subtractor 44 twice. The digital adder 48 outputs the output of the secondary modulator 20 and the output of the digital double differentiator 46 to add the digital output signal of the modulator 20 to the digital output signal generated by the digital double differentiator 46. Is connected to. The digital output signal generated by the subtractor 48 is applied to the digital decimation filter 50.

Neglecting the output quantization noise (dQ ₂ / dt) of the modulator 30, the difference between the two digital output signals of the modulators 20, 30 is exactly the same as the negative quantization noise (-Q1) of the secondary modulator 20. same. The double differential signal (-d ₂ Q ₁ / dt ₂ ) output from the digital double differentiator 46 is added to the digital output signal of the secondary modulator 20 by the digital adder 48 and thus the second modulator 20. Cancel quantization noise.

Considering the quantized noise signal dQ ₂ / dt, which was previously ignored, the noise signal Q ₂ is differentiated once by the primary modulator 30 to generate the signal dQ ₂ / dt. This is further differentiated by the digital differential 46 twice, leaving only the noise signal d ₃ Q ₂ / dt ₃ differentiated three times in the output signal Y (t) of the adder 48 as the only noise. This corresponds to a tertiary shape of quantization noise with significantly reduced baseband components and high frequency power emphasis. The three differential noise signals d ₃ Q ₂ / dt ₃ are efficiently removed from the final digital 17 output signal by the digital decimation filter 50.

A third order delta analog-to-digital converter network is implemented in a data switch capacitor circuit sampled according to the discrete time domain function block diagram of FIG. The real purpose of an oversampled modulator is to scale the analog signal level to match the reference voltage. Thus, the discrete time variant is shown in FIG. 4 and indicates that such a variant is possible in Even Balming's new transducer network.

In FIG. 4, each integrator 22, 24, 26 is shown as an adder (or summation) unit 62 followed by a one cycle delay register 60. Digital double differentiator 46 is shown as a pair of serially connected differentiators 78, each of which includes a delay register 80 and a digital subtractor 82 connected thereafter.

An amplifier 84 with a gain factor k _1a is located between the input of the integrator 22 and the output of the summing unit 32 in the secondary modulator 20. Amplifier 86 having gain factor k _1b connects the output of integrator 22 to the input of integrator 24 through summing unit 34. Another amplifier 88 having a gain factor 2k _1a k _1b is located in the feedback loop of the secondary modulator 20 between the output of the analog-to-digital converter 28 and the sub-input of the summing unit 34. The second feedback loop of 20 is formed by connecting the output of the transducer 28 to the negative input of the summing unit 32. An amplifier 92 with a gain j ₁ couples the output of the integrator 24 to the subtractive summing unit 42 in the primary modulator 30 and an amplifier with a gain factor k ₂ sums in the modulator 30. Located at the input of integrator 36 following unit 42.

A digital multiplier 74 having a multiplication factor g ₁ connects the output of the analog-to-digital converter 38 of the primary modulator 30 to the digital subtractor 44, and the digital-to-analog converter 40 connects to the analog-to-digital converter. The output of the 38 is connected to the subtractive summing unit 42. The output of the analog-to-digital converter 26 of the secondary modulator 20 is connected via the delay register 76 to the negative input of the digital subtractor 44 and It is connected to the digital adder 48. The dotted line 9 represents the separation between the digital circuit 21 and the analog circuit 19.

In Figure 4, the coefficients k _1a , k _1b . k ₂ and j ₁ are analog scaling factors and g 1 is a digital multiplication coefficient. The coefficients should have the relationship

j ₁ g ₁ = ₁ / (k _1a k _1b ) (1)

The above relationship means a case where only 1-bit analog-to-digital converter and 1-bit digital-to-analog converter are used. Usually, the coefficient K is chosen to be less than or equal to 1 to reduce the level of internal voltage in the modulator to avoid clipping. As a result of analyzing the network of FIG. 4, in the discrete signal domain,

vo (n) = vi (n-3) + g ₁ [e ₂ (n)-3e ₂ (n-1) + 3e ₂ (n-2)-e ₂ (n-3)] (2)

And in the corresponding frequency domain

Vo (Z) = z _-3 Vi (Z) + g ₁ (1-z _-1 ) ₃ E ₂ (z) (3)

Where n is a discrete time instant nT (T is a sample period), z is a discrete time frequency variable, or quantization error of a second stage. There is a compromise between voltage level and output noise strength, e.g. with scaling, the condition k _1a k _1b 1 becomes g ₁ 1 and the output error is proportional as indicated by equations (2) and (3). To increase.

The embodiment of FIG. 4 implies the use of 1-bit A / D converters and D / A converters, which can achieve performance improvements by using multi-bit A / D and D / A converters. In the case where the quantization level L is 1 bit or more, that is, L1, k _1a = k _1b = k ₂ = 1 and j ₁ g ₁ = 1 in FIG.

A specific embodiment of the oversampled third order sigma delta A / D converter network according to the invention is shown in FIG. 5, where L = 1, k _la = k _lb = k ₂ = 1/2, j ₁ = 1, g ₁ = 4. Thus, the amplifiers 84,86 in the secondary modulator 20 and the amplifier 90 in the primary modulator 30 each have a gain factor 1/2, and the digital multiplier 74 has a multiplication factor 4.

(The amplifier 92 having the gain factor j ₁ = 1 and the amplifier 88 having the gain factor 2k _1a k _1b = 1/2 used in the circuit of FIG. 4 is not shown in the circuit of FIG. 5). This embodiment requires only 1-bit A / D and D / A converters.

The switch capacitor implementation of the network of FIG. 5 is shown in FIG. 6 and uses single-ended signal flow and a strayless integrator. This integrator is illustrated, for example, on pages 277 to 280 of the analog MOS integrated circuit for signal processing by R. Gregorian (New York, Ill., 1986). In the secondary modulator 20 the integrator 22 is implemented as a high gain differential amplifier (OP amplifier) 100 having a feedback capacitor 102 and a switch input capacitor 104. The switch S ₁ is connected to an analog input signal. It is provided to switch capacitor 104 between feedback loops of modulator 20. A switch S ₂ is provided for switching the output voltage of the capacitor 104 between two inputs of the differential amplifier 100. Similarly, integrator 24 is implemented as a high gain differential amplifier (OP amplifier) 110 having a feedback capacitor 112 and a pair of switch input capacitors 114 and 103. Switch S ₃ is a differential amplifier 100 ) of the analog between the output signal and the ground is provided for switching a capacitor 114, a switch S ₉ is provided for switching a capacitor 103 between the feedback loop and the ground of the modulator 20. the switch S ₄ is It is provided to switch the output voltage of the capacitors 114 and 103 between two inputs of the differential amplifier 110. A comparator 116 operating at the sampling rate ψ 1 is provided for switching the partial pressure. Comparator 116 operating at sampling rate ψ 1 converts the analog output signal of differential amplifier 110 into a binary output signal. The binary output signal is stored by latch 118 and is applied to the negative input and digital adder of digital subtractor 44 via delay register 76. The output signal of latch 118 also switches the feedback loop between the positive reference voltage (+ Vref) and the negative reference voltage (-Vref) depending on whether the latched output signal of comparator 116 is positive or negative. Control S5.

In the primary modulator 30, the integrator 36 is implemented as a high gain differential amplifier (OP amplifier) 120 having a feedback capacitor 122 and a switch input capacitor 124. The switch S ₆ is a differential amplifier ( A switch is provided to switch the capacitor between the analog output signal of 110 and the feedback loop of modulator 30. A switch S ₇ is provided to switch the output voltage of capacitor 124 between two inputs of differential amplifier 120. do. A comparator 126 operating at a sampling rate ψ 1 converts the analog output signal of the differential amplifier 120 into a binary output signal. The binary output signal is stored by latch 128 and multiplied by 4 by multiplier 74 and applied to digital subtractor 44. The output signal of latch 128 also switches the feedback loop between the positive reference voltage (+ Vref) and the negative reference voltage (-Vref) depending on whether the polarity of the latched output signal from comparator 126 is positive or negative. Grant switch S ₈ . The digital difference signal generated by the digital subtractor 44 is differentiated twice by the digital double differentiator 46, and this differential signal is applied to the digital adder 48. As already known, the switches that can be realized by the metal oxide semiconductor switching element are all shown in common phase words.

Switch S _1- S ₄ , S ₆ , S ₇ . S ₉ is an analog switch controlled by clock phase signals ψ ₁ , ψ ₂ generated in an oscillator or clock circuit (not _shown ). The clock signals do not overlap and are 180 ° out of phase.

When the switches S _{1 to} S ₄ , S ₆ , S ₇ , and S ₉ are in the positions shown in FIG. 6, the capacitor 104 is charged to the amplitude of the analog input signal, while the capacitor 114 is connected to the amplifier 100. Is charged to the output voltage, and the capacitor 124 is charged to the output voltage of the amplifier (110). At the same time capacitor 103 is completely discharged.

The switches S ₅ , S ₈ connected to the positive reference voltage are respectively controlled by the output signals of the latches 118, 128. Thus, the higher the latched value of the output signal of the comparator (116 or 126), the switch S ₅ is S ₈ is connected to each cathode reference voltage, a latch value of the output signal of the comparator (116 126) low, negative reference voltage Is connected to.

If phase ψ2 occurs, switch S _{1 to} S ₄ . The positions of S ₆ , S ₇ and S ₉ are reversed from those shown in FIG. 6. Thus, the D / A converter 28 supplies the selected reference voltage, indicated as an anode through the switch S ₅ , which is added to the voltage of the capacitor 104 and supplied to the inverting input of the amplifier 100. The input signal is synthesized in capacitor 102 until clock phase ψ 1 occurs. At the same time, the sum of the past (ie, phase ψ 1) output voltage of amplifier 100 and the reference voltage from switch S ₅ stored in capacitor 114 is supplied to the inverting input of amplifier 110 and capacitor 124. The previous (i.e., phase ψ 1) output voltage of amplifier 110 stored in < RTI ID = 0.0 >) is supplied to the inverting input of amplifier 120. Thus, each of the amplifiers 100, 110, and 120 performs the integration of the input voltage supplied to their respective inverting input terminals until phase ψ 1 occurs again.

If the input signal of comparator 116 is positive, switch S ₅ is connected to positive reference voltage (+ Vref), and if the input signal is negative, switch S ₅ is connected to negative reference voltage (-Vref). The output voltage of the integrator 22 is the value obtained by integrating the difference between the positive or negative reference voltage and the input signal according to the position of the switch S5. Output signal can also represent the difference between the analog input signal and the digital signal representing the analog input signal as an integrated value.

The integrator 22 acts as a non-inverting integrator for the analog input signal and also as an inverting integrator for the 1-bit D / A converter 28 controlled by the comparator 116. The output signal of the integrator 22 is For each phase ψ2, (V _in -V _{D / A1} ) k _1a , where V _{D / A1} represents the output voltage of the D / A converter 28, and the output signal of the integrator 22 of the phase ψ1 The integrator 36 operates similarly except that its input signal is the output signal of the integrator 24 minus the output signal of the D / A converter 40. That is, the output signal of integrator 36 changes by (V ₂ -V _{D / A2} ) k ₂ for every phase ψ ₂ , where V ₂ is maintained in phase ψ 1 with the output voltage of integrator 36 and V _{D / A2} is the output voltage of the D / A converter 40.

The configuration of integrator 24 is slightly different from that of integrators 22 and 36 in that separate capacitors 114 and 103 are used for the two input signals. This is necessary because different capacitor ratios are required for the two input signals of integrator 24. In particular, the output signal of integrator 22 should be integrated as a ratio of k _1b , and the output signal of D / A converter 28 should be integrated as a ratio of -2k _1a k _1b . Thus, a combination of non-inverting and inverting switch capacitor integrators is used as integrator 24. By using a redundant structure, the plurality of input signals are regulated by a common connection at a switch S ₄ adjacent to the summing junction of the amplifier 110. Since each separate input capacitor 114, 103 is switched between ground and the negative input of amplifier 110, switch S ₄ can be shared even though individual switches S ₃ , S ₉ are required for the connection of the two input signals. Can be. The output signal of the integrator 24 is changed by k _1b V ₂ -2k _1a k _1b V _{D / A2} for every phase ψ ₂ and is maintained for phase ψ 1. Under the condition k _1a = 1/2, the two input capacitors 114 and 103 have the same value, and as in the integrators 22 and 36, only one capacitor may be used.

The circuit of FIG. 6 can completely deal with capacitor error. Each of the two switch capacitor integrators 22, 36 uses one switch capacitor 104, 124 to take the difference between the two input signals. Thus, the subtraction operation is free from errors. The remainder of the switch capacitor integrator 24 uses separate switch capacitors 114 and 103 to take the difference between the two input signals, but here the sum error can be neglected based on the input. The other sum or difference operation is executed digitally and there is no error. The only error component associated with the sum is the deviation of the product k _1a k _1b from the equivalent of 1 / j ₁ g ₁ . This is the quantization noise from the first stage,

[1-(j ₁ g ₁ / k _1a k _1b )] (1-z ^-1 ) ² E ₁ (z) (4)

Leakage effect, so that the total output voltage Vo (z)

Vo (Z) = Z _-3 Vi (Z) + g ₁ (1-Z ^-1 ) ³ E ₂ (Z) +

[1-j ₁ g ₁ / (k _1a k _1b )] (1-z ^-1 ) ² E ₁ (z) (5)

To be. Here, E ₁ represents the quantization noise of the first stage. The degree of mismatch, i.e. 1-j ₁ g ₁ / (k _1a k _1b ), is already multiplied by a term with a second order noise shape, i.e. (1-z ^-1 ) ² E ₁ (z), so k _1a or A relatively large error of k _1b can be tolerated without large decay. For example, a 5% error in the product k _1a k _1b raises the overall quantization noise by less than 1 dB at an oversampling ratio of 64: 1.

More simulations were performed on the new oversampled modulator. The variables of the analog-digital converter are as follows.

The simulation results can be summarized as follows.

The present invention thus constitutes an improved modulator network that achieves third order noise shape and greatly reduces sensitivity to component matching and most other practical non-idealities. Simulations have shown that a 16-bit signal-to-noise ratio can be obtained despite 2% component matching and 1000 op amp gains. Integrated circuits containing such modulators can be manufactured in high yield without trimming or ca1ibration, and without stringent process conditions. Therefore, the present invention can obtain an economical high resolution multi-channel analog-to-digital converter.

Although the modulator components described above, namely integrators, analog-to-digital converters and digital-to-analog converters, have been described as having single-ended outputs, the third order sigma delta analogue-to-digital converters of the present invention have differential outputs for improved rejection of supply noise. This can be done by using a differential signal path using an integrator with. This is shown in FIG.

FIG. 7 shows a network using a differential amplifier representing a circuit used in an oversampled third-order sigma delta A / D converter network test chip, and FIG. 8 shows a clock waveform used in the circuit of FIG. The circuit of FIG. 7 differs from the single-ended switch capacitor A / D converter network of FIG. 6 in that it uses three phases instead of two-phase clocking, and the circuit of FIG. 7 differs from FIG. 6 in spurious supply noise. It uses fully harmonized (or derivative) signals for better rejection of and common mode signals, and uses chopper stabilization circuit 200 to suppress low-frequency OP amplifier noise, and operates as a differential and single-ended input circuit. Can be. Each integrator 22, 24, 36 used in the circuit of FIG. 7 includes a harmonic output and a harmonic input.

Considering the operation of the FIG. 7 circuit, the presence of the chopper circuit 200 as part of the integrator 22 is initially ignored by assuming that the chopper phase ψ _CHP is always asserted. It is also assumed that the input signal is also a harmonic input signal. In this situation, the clock phase is defined differently, but its operation is similar to that of the single-ended circuit of FIG. That is, in the circuit of FIG. 6, clock phases ψ1 and ψ2 correspond to phases ψ3 and ψ1, respectively. If phase ψ 2 is temporarily ignored, the operation is the same as described in FIG. 6 except that the output side is connected to ground when the input signal is sampled during phase ψ 3 by two input capacitors 201 and 202. The only difference is that they are commonly connected via the switch S ₁₀ . By this common connection, only the differential component of the input signal is obtained. The common mode signal is sampled if it is present if the capacitors 201, 202 are switched to ground instead of switching to each other, but the charge charged to the input capacitors 201, 202 in the configuration shown in the figure It only depends on the difference of the input signal, not the average value. This effect similarly occurs for the input capacitors 203 and 204 of the second stage integrator 24 of the network and the input capacitors 205 and 206 of the third stage integrator 36 of the network.

As described above, the output side of the input capacitor for each integrator stage will not be connected to a voltage source or ground, so the voltage of each of these capacitors will have an arbitrary value. Similarly, the voltage level at the input to a 0P amplifier that receives a signal from its input capacitor is not fixed. Thus, a connection to ground is used during phase ψ 2 to form a potential on the output side (or right side) of the input capacitor and the input side (left side) of each input capacitor remains connected to receive the reference signal.

Another slight difference from the circuit of FIG. 6 is that the 1-bit D / A converters 210, 211 and 212 use a single pole double-throw switch (S ₅ , S ₈ ) shown in FIG. 6 network. Instead, it is implemented directly at the input side (left side) of the input capacitors 201,202; 203,204; 205,206. However, the effect is the same, because the switches of each of the D / A converters 201, 211, 212 are controlled by a signal equal to a predetermined clock phase that is logically added to the latched comparator signal. According to this embodiment, the two switches do not need to be connected in series, thus eliminating the need for speed penalties in high frequency circuit operation associated therewith.

The logic for the individual switch positions in the D / A converters 201, 211 and 22 is as follows.

Here, CMP1D is a signal latched by the latch circuit 218 as an output signal of the comparator 216 at the output of the second stage integrator 24, and CMP2D is a signal of the comparator 226 at the output of the third stage integrator 36. It is a signal latched by the latch circuit 228 as an output signal. Clock waveform ψ 2 is shown in FIG.

Considering the function of the chopper circuit, the MOS switching device indicated by the double pole and the double throw switch 200 on either side of the first OP amplifier 222 is controlled according to the control of the ψ _CHP chopper clock signal and ψ _CHN chopper clock signal. Periodically invert the signal polarity at the input and output of the op amp. The inversion of the clocks ψ _CHP and ψ _CHN described in the waveform diagram of FIG. 8 may be done in any scale, which may be from an integer multiple of the output conversion speed to the maximum speed of the modulator frequency. The non-inverting path through the OP amplifier 222 is selected by the chopper at the input and output when clock ψ _CHP is high, whereas an inverted configuration is made when phase ψ _CHN is high. When clock ψ _CHN is high, inversion occurs simultaneously at the input and output of the op amp, so there is no effect on the signal passing through the integrator. However, the noise from the op amp itself passes only through the chopper's output switch, which likewise changes its polarity at a rate determined by the frequency of the chopper clock. This is equivalent to multiplying a periodic square wave signal with an amplitude of ± 1 by noise, thus modulating the op amp noise up to the frequency of the chopper square wave and all of its harmonics. As a result, very low frequency flicker (or 1 / f) noise is removed at the baseband frequency of the modulator. Flicker noise is described on pages 500 to 505 of the above-described analog MOS integrated circuit for signal processing. [0037] The following digital flickering by decimation filter (not shown in Figure 7) eliminates modulated l / f noise. . In fact, chopping at the same rate as the decimation filter's output speed, or at a higher integer multiple (if a comb filter is used), places the fundamental and harmonics of the square wave at the zero frequency of the decimation filter. It facilitates the removal of the modulation noise. However, those skilled in the art will appreciate that the present invention is not limited to the use of digital decimation filters, and any signal processing circuit capable of suppressing high frequency quantization noise components may be used.

The inventors have found that the realization of the new A / D converter network and the realization of another Sigma delta type A / D converter network under development are greatly improved by using the chopper stabilization of the op amp used in the initial integrator for the error signal. It was found to be augmented. F. Yassa, S. Garverick, G. Ngo, R. Hartley, J. Prince, J. Lam, S. Noujaim, R. Korsunsky and J. Thomas, `` IEEE 1989 COSTOMINTEGRATED CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, CH2671-6 / 89/0000 to 0125 $ 1.00c.1989, IEEE 20.5.1 to 20.5.5. A multichannel digital demodulator for LVDT and RVDT position sensors adds to the input to achieve high sensitivity for low amplitude signals. The use of chopper stabilization in a sigma delta (or delta sigma) modulator is also described to generate a dither signal and also to eliminate amplifier offsets and component mismatches. The zero of the decimation filter, such as Yassa, used after the sigma delta modulator, matches the frequency of the chopping signal and further suppresses the modulator signal and other modulators generated at the chopping frequency. Chopper stabilization shifts the flicker (or l / f) noise of an amplifier in the frequency spectrum from the baseband of the chopping frequency to the sideband, with the lower portion of the sideband aliased to the baseband to some extent. Unless high resolution is required from the oversampling A / D converter network, the baseband aliased l / f noise is adjacent to each other even if the chopping signal frequency (cycles / sec) is equal to the output speed of the decimation filter (samples / sec). Is less than the difference between quantization levels.

However, if you increase the resolution at the digital output, the baseline aliased l / f noise is between the adjacent quantization levels if the frequency of the chopping signal (cycles / sec) is equal to the output speed of the decimation filter (samples / sec). Is greater than the difference. The inventors have found that the problem is solved when the chopping speed is increased more than one times more than the output speed of the decimation filter. It has also been found that faster speeds increase the nonlinearity resulting from the installation of the chopper stabilizer amplifier after each switching. Therefore, it is generally not a good idea to increase the chopping speed to half of the oversample age. Rather, in terms of achieving the highest resolution in terms of bits, in an oversampling A / D converter network, it is better to choose the chopping speed to be a lower multiple of the output of the decimation filter. The plurality of low speeds should be chosen so that the characteristics related to 1 / f noise and the characteristics related to nonlinearity resulting from the setting of the chopper stabilization amplifier after each switching are as close as possible to the point where they intersect each other in value. The difference between adjacent quantization levels is then minimized to use the optimal resolution bits.

9 illustrates a form that the digital decimation filter 50 of FIG. 3 can take. 9 shows E. Dijkstra, O. Sinc in the form described in the paper by Nye, C. Piguet, M. Degrauwe on the use of modulo comb filters in sigma delta modulators (PROCEEDINGS OF THE IEEE CONFERENCE ON ACOUSTICS, SPEECH PROCESSING, p. 2001-2004). Represents an ^n- type comb filter. The third-order sigma delta analog-to-digital converter network of FIG. 3 forms a quantization noise spectrum to have sixth order sine wave characteristics as follows.

S _N (ωT) = k _QN [2 sin (ωT / 2)] ^{2 L}

Where k _QN represents the power spectral density (PSD) of the non-shape (white) quantization noise and L = 3 represents the order of the sigma delta modulator. The sinc ⁿ type comb filter can appropriately suppress the quantization noise when n is greater than L. The comb filter of FIG. 9 (where n = 4) is the k _QN [2 sin (ωT / 2)] ^{6 in} the summed output signal of the adder 48 in the 3rd order sigma delta analog-to-digital converter network of FIG. Properly suppress quantization noise.

The comb filter of FIG. 9 is summed from the digital adder 48 of the sigma delta modulators of FIG. 3, 4, or 5 that is quadrupled in n integrators (n = 4 in the comb filter of FIG. 9). Receives an output signal as its input signal, each integrator 300 each delay register 302 for feeding back the respective digital adder 301 and the summation output of the adder 301 to the input of the adder 301. ). In the decimation process, the quadruple integral response of the series circuit is subsampled to n: 1 in the digital sampler 310 as can be provided by a multiple bit latch. The secondary sample response of the digital sampler 310 is differentiated four times in series with n different derivatives (n = 4 in the comb filter of FIG. 9), with each differentiator 320 being the current of the input signal of the differentiator 320. The sample includes a digital adder 321 that adds the sample to a past sample stored in the delay register 322, thereby generating a summed output signal that is a derivative of the input signal of the differentiator 320 over time. The response from the final differentiator 320 is scaled down by n ⁿ in the digital scaler 330 and becomes the response of the ultimate decimation filter 50.

FIG. 10 shows a variation of the tertiary sigma delta analog-to-digital converter network of FIG. 3, which is another embodiment of the invention. Instead of differentially dividing the differential output signal of subtractor 44 over time and adding the result to the output signal of secondary modulator 20 to remove quantization noise from secondary modulator 20, a secondary modulator The output signal of 20 is double integrated in the digital double integrator 51, and the response of the digital double integrator 5l is added to the output signal of the secondary modulator 20 in the digital adder 52. The summation output signal of the adder 52 includes the sum of the low pass filtered (two-integrated) digital values of the analog input signal and the primary quantization noise of the primary modulator 30. Quantization noise from the secondary modulator 20 does not appear in the summation output signal of the adder 52, which is supplied to the digital decimation filter 53 responsive to the digital output signal y (t).

FIG. 11 shows a variation of the tertiary sigma delta analog-to-digital converter network of FIG. 4, which is another embodiment of the invention and of the type shown in FIG. Digital dual integrator 51 is shown in more detail in FIG. 10 as a pair of serially connected integrators 54, each integrator 54 summing the digital adder 55 and the adder 55 to its input. A delay register 56 for feeding back the output.

12 shows a form that the digital decimation filter 53 can take. A digital decimation filter 53 connected to receive the sum output signal of the digital adder 52 of FIG. 10 or 11 as an input signal receives the sum signal of the digital adder 48 of FIG. And receive the same response as the digital decimation filter 50. The two integrators 300 in front of the digital decimation filter 50 are of no use in the digital decimation filter 53, because they are secondary to the third-order sigma delta analog-to-digital converter network of FIG. 10 or 11. This is because the output signal of the modulator 20 has a digital double integrator 51 but does not have a digital double integrator 46 for the output signal of the digital subtractor 44.

FIG. 13 shows a variation of the tertiary sigma delta analogue-to-digital converter network of FIGS. 3 and 10, the variation being another embodiment of the present invention. The differential output signal of the subtractor 44 is only differentiated once with respect to time in a single digital integrator 78, the output signal of the secondary modulator 20 is integrated only once in the digital integrator 54, and the digital integrator 78 And the response of the digital integrator 54 is added in the digital adder 57. The summation output signal of the adder 57 includes the sum of the low pass filtered (one-time integration) digital value of the analog input signal and the secondary quantization noise of the primary modulator 30. Quantization noise of the secondary modulator 20 is supplied to a digital decimation filter 58 that does not appear in the summation output signal of the adder 57 and responds to the digital output signal y (t).

FIG. 14 shows a variation of the tertiary sigma delta analogue-to-digital converter network of FIGS. 4 and 11, the variation being another embodiment of the present invention and of the type shown in FIG. Differentiator 78 adds the current sample of the difference signal of subtractor 44 to the past sample stored in delay register 80 to generate a digital output signal that is a derivative of the difference signal of subtractor 44 over time. Integrator 54 includes a digital adder 55 and a delay register 56 that feeds back the sum output of adder 55 to its input.

15 illustrates a form that the digital decimation filter 58 may take. A digital decimation filter 58 coupled to receive the sum output signal of the digital adder of FIG. 13 or 14 as an input signal is configured to receive the sum output signal of the digital adder 48 of FIG. 3 or 4 as an input signal. Supply the same response as the connected digital decimation filter 50. The integrator 300 in front of the digital decimation filter 50 is of no use in the digital decimation filter 58. The third order sigma delta analog-to-digital converter network of FIG. 13 or 14 has a digital integrator 54 for the output signal of the secondary modulator 20 and one for the output signal of the digital subtractor 44. This is because it has only the digital differential (78).

Although only specific embodiments of the present invention have been described so far, those skilled in the art can make various modifications and variations as described in the specification. Accordingly, the following claims should be construed as including all modifications and variations included within the true spirit of the invention.

Claims (34)

A secondary modulator comprising a first integrator connected in series and a first analog-to-digital converter coupled to an output of the second integrator, the output of the first integrator being coupled to the input of the second integrator The first integrator receives an analog input signal, and the first analog-to-digital converter converts the analog output signal of the second integrator to the first digital corresponding to the addition of the analog input signal and the second differential quantization noise component. A second modulator, a third integrator, and an output of the second integrator, wherein the analog output signal corresponds to the first digital output signal which is smaller than the quantization noise of the secondary modulator. Means for coupling to an input of a three integrator and the analog output signal of the second integrator to the analog output signal and a first order quantized noise component A primary modulator comprising a second analog-to-digital converter coupled to the output of the third integrator to convert to a second digital output signal corresponding to the addition and corresponding to the analog input signal without quantization noise from the secondary modulator And means for coupling a first digital output signal and a second digital output signal of the secondary modulator and the primary modulator to generate a digital output signal. 2. The apparatus of claim 1, wherein said means for combining said first digital output signal and said second digital output signal of said secondary modulator and said primary modulator comprises: an output of said first analog-to-digital converter and a second analog-to-digital converter; And a digital subtractor means coupled to the output of said digital subtractor means for providing a digital differential signal representing the difference between the output signals of said first analog-to-digital converter and said second analog-to-digital converter. Analog-to-digital converter network. 3. The apparatus of claim 2, wherein said means for combining said first digital output signal and said second digital output signal of said secondary modulator and said primary modulator is coupled to an output of said digital subtractor means and subtracts said digital derivative signal from a second derivative. A digital adder means coupled to an output of the first analog-to-digital converter and the digital second derivative, and to add an output signal of the first analog-to-digital converter to an output signal of the digital second derivative; A third order sigma delta analogue-to-digital converter network coupled to the output of the digital adder means and further comprising digital decimation filter means for suppressing all third order differential quantization noise in the output signal of the digital adder means. . 3. The apparatus of claim 2, wherein said means for coupling said first digital output signal and said second digital output signal of said secondary modulator and said primary modulator is coupled to an output of said first analog-to-digital converter. A digital double integrator that double-integrates the output signal of the digital converter, a digital subtractor coupled to the output of the digital subtractor means and the output of the digital double integrator, and adds the output signal of the digital subtractor means to the output signal of the digital double integrator; A third sigma delta further comprising an adder means and a digital decimation filter means coupled to the output of the digital adder means and which counteracts all third order differential quantization noise in the output signal of the digital adder means. Analog-to-digital converter network. 3. The apparatus of claim 2, wherein said means for combining said first digital output signal and said second digital output signal of said secondary modulator and said primary modulator is coupled to an output of said digital subtractor means and differentiates said digital difference signal. A digital integrator, a digital integrator coupled to the output of the first analog-to-digital converter and integrating the output signal of the first analog-to-digital converter, and coupled to an output of the digital differentiator and the digital integrator and output of the digital differentiator. Digital adder means for adding a signal to the output signal of the digital integrator and a digital decimation filter means coupled to the output of the digital adder means and suppressing all three differentiated quantization noises in the output signal of the digital adder means are added. Tertiary sigma delta analogue, characterized in that included That-digital converter network. 2. The first digital-analog converter of claim 1, wherein the secondary modulator is coupled to a first feedback loop and a second feedback loop, respectively, between an output of the analog-to-digital converter and inputs of the first and second integrators. Wherein the primary modulator comprises a second digital-analog converter coupled to a third feedback loop between the output of the second analog-to-digital converter and the input of the third integrator. Analog-to-digital converter network. 7. The apparatus of claim 6, wherein said means for combining said first digital output signal and said second digital output signal of said secondary modulator and said primary modulator comprises: an output of said first analog-to-digital converter and a second analog-to-digital converter; And a digital subtractor means coupled to the output of the digital subtractor means for providing a digital differential signal representing a difference between the output signals of the first analog-to-digital converter and the second analog-to-digital converter. network. 8. The apparatus of claim 7, wherein the means for combining the first digital output signal and the second digital output signal of the secondary modulator and the primary modulator is coupled to the output of the digital subtractor means and second derivatives the digital difference signal. A digital adder means coupled to an output of the first analog-to-digital converter and the digital second derivative, and to add an output signal of the first analog-to-digital converter to an output signal of the digital second derivative; And a digital decimation filter means coupled to the output of the digital adder means and suppressing all third order differential quantization noise in the output signal of the digital adder means. 8. The apparatus of claim 7, wherein said means for combining said first digital output signal and said second digital output signal of said secondary modulator and said primary modulator is coupled to an output of said first analog-to-digital converter. A digital double integrator that double integrates an output signal of an analog-to-digital converter, and a digital combiner that is coupled to the output of the digital subtractor means and the digital double integrator and adds the output signal of the digital subtractor means to the output signal of the digital double integrator. A third order sigma delta analogue characterized by further comprising an adder means and a digital decimation filter means coupled to the output of the digital adder means and suppressing all tertiary differential quantization noise in the output signal of the digital adder means. Digital Converter Network. 8. The apparatus of claim 7, wherein the means for combining the first digital output signal and the second digital output signal of the secondary modulator and the primary modulator is coupled to the output of the digital subtractor means and differentiates the digital difference signal. A digital differentiator, an integrator coupled to the output of the first analog-to-digital converter and integrating the output signal of the first analog-to-digital converter, coupled to an output of the digital differential and to an output of the digital integrator Digital adder means for adding an output signal of the digital integrator to the output signal of the digital integrator, and a digital decimation filter means coupled to the output of the digital adder means and suppressing all third-order differential quantization noise in the output signal of the digital adder means. Tertiary sigma delta analogue-digital further comprising Deconverter network. 7. The apparatus of claim 6, wherein the means for coupling the output of the second integrator to the input of the third integrator comprises a heavy amplifier of gain j ₁ and the network is coupled to the output of the second analog-to-digital converter. And a digital multiplier for multiplying the second digital output signal by a digital multiplication factor (g ₁ ), the secondary modulator applying an analog scaling factor (k _1a ) for scaling the signal supplied to the first integrator. And a third circuit means having a first circuit means having and an analog scaling factor (k _1b ) for scaling the output signal of the first integrator. 12. The apparatus of claim 11, wherein the primary modulator comprises subtractor means coupled to an output of an amplifier having a gain j ₁ and an output of the second digital-to-analog converter, and to a scaled deformation of the analog output signal of the subtractor means. And a third circuit means having an analog scaling factor (k ₂ ) for feeding to the integrator. 8. The apparatus of claim 7, wherein the means for coupling the output of the second integrator to an input of the third integrator comprises an amplifier of gain j ₁ and the network is coupled to the output of the second analog-to-digital converter. And further comprising a digital multiplier for multiplying the second digital output signal by the coefficient g ₁ , wherein the first integrator has an analog scaling factor k _1a for scaling the output signal, the first feedback loop being the A first subtractor means responsive to an analog input signal and an output signal of the first digital-to-analog converter and a first having an analog scaling factor k _1a for supplying the scaled output signal of the subtractor means to the first integrator And circuit means, wherein the second feedback loop comprises an analog for scaling the output signal of the first digital-to-analog converter. Scaling factor (2k _1a k _1b) and said first digital-and further comprising a second subtractor means having one input responsive to the scaled output signal of the analog converter, the first integrator and the second integrator Series combining the analog scaling factor (k _1b ) and the second subtractor means for scaling the output signal of the first integrator and for supplying the scaled output signal of the first integrator to the second input of the second subtractor means. And an output of the second subtractor means coupled to the input of the second integrator, wherein the coefficients have a relationship of j ₁ g ₁ = 1 / k _1a k _1b network. 14. The apparatus of claim 13, wherein each of the first, second and third integrators comprises an analog adder for receiving an input signal at a first input and a delay register coupled to the output of the analog adder. A tertiary sigma delta analogue-to-digital converter network characterized in that the output is combined in a feedback configuration of the second input of the analog adder. 2. The tertiary sigma delta analog-to-digital converter network of claim 1 wherein each of the first, second and third integrators has a harmonic input and a harmonic output. The third sigma delta of claim 1, wherein the first integrator includes a chopper stabilizing amplifier in which chopping of the input signal and the output signal is performed at a predetermined chopping speed, and a feedback capacitance between the output and the input. Analog-to-digital converter network. The decimation filter of claim 1, further comprising a decimation filter for comb-filtering the digital output signal from the means for combining the first digital signal and the second digital signal, wherein the decimation filter includes: A tertiary sigma delta analogue-to-digital converter network characterized by having zero at its harmonics. An analog corresponding to the first digital output signal in response to an analog input signal to generate a first digital output signal corresponding to the sum of the analog input signal and the second derivative quantized noise component and as small as the quantization noise of the secondary modulator. A secondary modulator for generating an output signal, a primary modulator for generating a second digital output signal corresponding to the sum of the analog output signal and the first differential quantization noise component in response to the analog output signal of the secondary modulator; A digital subtractor for determining a difference between the first digital output signal and a second digital output signal to generate a digital differential signal comprising a primary noise component from the primary modulator free of quantization noise from the secondary modulator. Second derivative of the digital differential signal to obtain a second unquantized job from the secondary modulator A digital second derivative that generates a synthesized digital signal comprising a third order quantized noise component from the primary modulator that is as small as the component, and adds the first digital output signal and the synthesized digital signal to the first differential noise component and A third sigma delta comprising a digital adder for generating a third digital output signal from which the second derivative noise component is removed, and a digital decimation filter for suppressing the third differential noise component in the third digital output signal Analog-to-digital converter network. 19. The apparatus of claim 18, wherein the digital secondary differentiator comprises a pair of series coupled digital differentiators, each of the digital differentiators each having a delay example and a first input coupled to an output of the delay register and a second input coupled to the delay. A tertiary sigma delta analogue-to-digital converter network comprising a digital subtractor coupled to the input of a register. 20. The integrator of claim 19, wherein the secondary modulator comprises first and second integrators coupled in series such that the output of the first integrator is coupled to the input of the second integrator, and the second integrator connected to the output of the second integrator. An analog-to-digital converter for converting an analog output signal of the first digital output signal to a third integrator having an input coupled to the output of the second integrator and an output of the third integrator. A tertiary sigma delta analogue-to-digital converter network, coupled to convert the analog output signal of the second integrator into the second digital output signal. A first comparator and a second integrator coupled in series so that an output of the first integrator is connected to an input of a second integrator, a first comparator coupled to an output of the second integrator and generating a first digital output signal; A first coupling means for coupling a switch reference voltage source and said first switch reference voltage source to an output of said first comparator, wherein said first integrator further comprises a first analog output signal in response to an analog input signal and said first switch reference voltage source; Is provided to the second integrator, the second integrator provides the selected analog output signal to the first comparator in response to the first analog output signal and the first switched reference voltage source and the first comparator is configured to select the selected analog signal. Providing the first digital output signal in response to an output signal comprises first combining means, a third integrator coupled to the output of the second integrator, A second comparator coupled to an output of a third integrator and providing a second digital output signal, second coupling means for coupling a second switch reference voltage source and the second switch reference voltage source to an output of the second comparator, The third integrator provides a selected second analog output signal to the second comparator in response to the selected analog output signal and the second switch reference voltage source, and the second comparator responds to the second selected analog output signal. A second combining means for generating the second digital output signal, a digital multiplier for multiplying the second digital output signal by a multiplication factor, and coupled to the digital multiplier and the first comparator therebetween. A digital subtracter for generating a digital difference signal, and a digital subtracter coupled to the digital subtractor to differentiate the digital difference signal twice A digital adder for generating a digital signal, a digital adder for adding the first digital output signal and the synthesized digital signal to generate a third digital output signal, and the analog input signal in response to the third digital output signal. A third-order sigma delta analog-to-digital converter network characterized by including a digital decimation filter that generates a digital signal. The apparatus of claim 21, wherein each of the first integrator, the second integrator, and the third integrator comprises: a differential amplifier having a first input, a second input and an output, a feedback capacitor connected between the output and the first input, Selectively charging and discharging the input capacitor by connecting an input capacitor and the input capacitor to a received analog voltage or reference voltage, and selectively connecting the input capacitor to the first input when the input capacitor is connected to the reference voltage. A tertiary sigma delta analogue-to-digital converter network comprising switching means for connecting. 22. The apparatus of claim 21, wherein the digital secondary differentiator comprises a pair of digital differentiators connected in series, each differentiator comprising a respective delay register and a first input coupled to the output of the respective delay register. A tertiary sigma delta analogue-to-digital converter network, wherein the input comprises a respective digital subtractor coupled to the input of the respective delay register. 22. The method of claim 21, wherein said first coupling means for coupling said first switch reference voltage source to an output of said first comparator comprises a first latch for storing said first digital output signal, said second switch reference voltage source And the second coupling means for coupling the output of the second comparator to a second latch that reads the second digital output signal, wherein the first latch couples the digital subtractor to the first comparator. Sigma Delta Analog-to-Digital Converter Network. A first comparator and a second integrator coupled in series so that an output of the first integrator is connected to an input of a second integrator, and a first comparator coupled to an output of the second integrator to generate a first digital output signal; A first coupling means for coupling a switch reference voltage source and said first switch reference voltage source to an output of said first comparator, wherein said first integrator further comprises a first analog output signal in response to an analog input signal and said first switch reference voltage source; Is provided to the second integrator, the second integrator provides a selected analog output signal to the first comparator in response to the first analog output signal and the first switched reference voltage source, and the first comparator A first combining means for providing said first digital output signal in response to a selected analog output signal, a third integrator coupled to the output of said second integrator, A second comparator coupled to an output of a third integrator for providing a second digital output signal, second coupling means for coupling a second switch reference voltage source and the second switch reference voltage source to an output of the second comparator, The third integrator provides a second selected analog output signal to the second comparator in response to the selected analog output signal and the second switch reference voltage source, wherein the second comparator responds to the second selected analog output signal. And a digital multiplier for multiplying the second digital output signal by a multiplication factor; and a digital multiplier coupled to the digital multiplier and the first comparator. A digital subtractor for generating a differential digital signal by generating a digital subtractor for generating a differential signal and integrating the first digital output signal twice. And a digital adder for adding the digital difference signal and the sum digital signal to generate a third digital output signal, and a digital decimation filter for generating a digital signal representing the analog input signal in response to the third digital output signal. A tertiary sigma delta analogue to digital converter network comprising a. 27. The apparatus of claim 25, wherein each of the first, second and third integrators comprises: a differential amplifier having a first input, a second input and an output, a feedback capacitor connected between the output and the first input, Selectively connecting an input capacitor to the received analog voltage or reference voltage to charge or discharge the input capacitor and selectively connect the input capacitor to the first input when the input capacitor is connected to the reference voltage. A tertiary sigma delta analogue-to-digital converter network comprising switching means for connecting. 27. The digital divider of claim 26, wherein the digital dual integrator comprises a pair of digital integrators connected in series, each digital integrator comprising a respective delay register, a first input and a second coupled to the output of the respective delay register. And a respective digital subtracter having an input and an output coupled to the input of each delay register. 26. The apparatus of claim 25, wherein the first combining means comprises a first latch for storing the first digital output signal, and the second combining means includes a second latch for storing the second digital output signal, And wherein the first latch couples the digital subtractor to the first comparator. A first comparator and a second integrator coupled in series so that an output of the first integrator is connected to an input of a second integrator, a first comparator coupled to an output of the second integrator and generating a first digital output signal; A first coupling means for coupling a switch reference voltage source and the first switch reference voltage source to an output of the first comparator, wherein the first integrator comprises a first analog output signal in response to an analog input signal and the first switch reference voltage source; Is provided to the second integrator, the second integrator provides a selected analog output signal to the first comparator in response to the first analog output signal and the first switch reference voltage source, and the first comparator First combining means for providing said first digital output signal in response to an analog output signal, a third integrator coupled to the output of said second integrator, and A second comparator coupled to an output of a third integrator for providing a second digital output signal, second coupling means for coupling a second switch reference voltage source and the second switch reference voltage source to an output of the second comparator, The third integrator provides a second selected analog output signal to the second comparator in response to the selected analog output signal and the second switch reference voltage source, and the second comparator responds to the second selected analog output signal. A second combining means for generating the second digital output signal, a digital multiplier for multiplying the second digital output signal by a multiplication factor, and a digital multiplier and a first comparator coupled thereto. A digital subtractor for generating a differential signal, and a summation differential by combining the digital subtractor once with the digital subtractor A digital derivative that generates a digital signal, a digital integrator that integrates the first digital output signal once and generates a digitally integrated signal, and adds the sum of the differential digital signal and the sum of the integrated digital signal. And a digital adder for generating a three digital output signal and a digital decimation filter for generating a digital signal representing the analog input signal in response to the third digital output signal. . 30. The apparatus of claim 29, wherein the first integrator, the second integrator, and the third integrator comprise a differential amplifier having a first input, a second input and an output, a feedback capacitor coupled between the output and the first input, and an input. Selectively connecting a capacitor and the input capacitor to a received analog voltage or reference voltage to charge or discharge the input capacitor and selectively connect the input capacitor to the first input when the input capacitor is connected to the reference voltage. A tertiary sigma delta analogue-to-digital converter network, each comprising switching means for connecting. 31. The digital divider of claim 30, wherein the digital differentiator comprises a respective digital subtractor having a respective delay register, a first input coupled to the output of the respective delay register and a second input coupled to the input of the respective delay register. And wherein the digital integrator comprises a digital adder having a respective delay register, a first input, a second input coupled to the output of the respective delay register and an output coupled to the input of the respective delay register. Car Sigma Delta Analog-to-Digital Converter Network. 30. The apparatus of claim 29, wherein the first coupling means comprises a first latch for storing the first digital output signal, and the second coupling means includes a second latch for storing the second digital output signal, And said first latch couples said digital subtractor to said first comparator. An oversampling analog-to-digital converter having a sigma delta modulator connected in series behind the decimation filter, the decimation filter having an output rate that is a fraction of 1 / R of the oversampling rate at which a digital sample of its input signal is supplied; Supply a digital output signal to an oversampling analog-to-digital converter, wherein R is an integer of at least 4, and the sigma delta modulator is connected as a Miller integrator to generate an integrator output signal that is the time integral of the error signal An amplifier, means for quantizing the integrator output signal and generating at a digital oversampling rate of the input signal for the decimation filter, a digital-to-analog converter for generating an analog feedback signal corresponding to the digital input signal for the decimation filter; Oversampling the analog feedback signal An oversampling analog-to-digital converter, which is a sigma delta modulator comprising means for differentially coupling to an analog input signal for an analog-to-digital converter to generate the error signal, the oversampling analog-to-digital converter having less than half the oversampling rate and more than the output rate. Means for operating said chopper stabilized amplifier at a high chopping speed. An oversampling analog-to-digital converter having a sigma delta modulator connected in series behind the decimation filter, the decimation filter having an output rate that is a fraction of 1 / R of the oversampling rate at which a digital sample of its input signal is supplied; Supply a digital output signal to an oversampling analog-to-digital converter, wherein R is an integer of at least 4, and the sigma delta modulator is connected as a Miller integrator to generate an integrator output signal that is the time integral of the error signal Means for quantizing the integrator output signal to generate digital samples of the decimation filter input signal at an oversampling rate, and a digital-analog for generating an analog feedback signal corresponding to the decimation filter digital input signal. A transducer and the analog feedback signal to the o A sigma delta modulator comprising means for differentially coupling an analog input signal for a sampling analog-to-digital converter to generate the error signal, wherein the oversampling rate of the analog-to-digital converter is at a chopping rate that is half of this sampling rate. In an oversampling analog-to-digital converter at a speed high enough to allow many unacceptable distortions of the digital output signal of the decimation filter due to stabilization after switching of the chopper stabilization amplifier when the chopper stabilization amplifier is in operation, In the chopper stabilizing amplifier the chopping rate is chosen to be an even divisor less than half of the oversampling rate such that any distortion of the digital input signal to the decimation filter can be tolerated at the frequency baseband. And the chopping speed in the chopper stabilizing amplifier is chosen to be higher than the output speed, thereby maintaining 1 / f noise at the allowable low amplitude level and the chopping speed being equal to or equal to the output speed. And over-sampling analog-to-digital converter, wherein more bits of resolution are obtained from the oversampling analog-to-digital converter than half the oversampling rate.

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